M68HC05 Microcontrollers M68HC05AG/D Rev. 3/2002 WWW.MO

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M68HC05 Microcontrollers M68HC05AG/D Rev. 3/2002 WWW.MO

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M68HC05
M68HC05
Microcontrollers
M68HC05AG/D Rev. 3/2002
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M68HC05
provide most up-to-date information, revision documents World Wide will most current. Your printed copy earlier revision. verify have latest information available, refer following revision history table summarizes changes contained this document. your convenience, page number designators have been linked appropriate location.
Motorola Stylized Logo registered trademarks Motorola, Inc. DigitalDNA trademark Motorola, Inc.
Motorola, Inc., 1989, 1996, 2002
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Revision History
Revision History
Date April, 1997 Revision Level Description Format organizational changes Updated current publication styles Appendix Instruction Details Corrected Boolean formulae compare accumulator with memory (CMP) instruction Appendix Instruction Details Corrected Boolean formulae subtract (SUB) instruction Page Number(s) Throughout
March, 2002
NOTE:
this document originally released 1989, there have been some changes Motorola's procedures. example, there references this document electronic bulletin board system (BBS) freeware. been replaced with World Wide Web. freeware other referenced documentation please refer
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Applications Guide M68HC05
List Sections
Section General Description
Section Microcontroller Operation Section MC68HC705C8 Functional Data Section Applications. Appendix Instruction Details Appendix Review Questions
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List Sections
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Applications Guide M68HC05
Table Contents
Section General Description
Contents Introduction Definitions Background. Computer Systems Description Microcontroller Applications Overview Project Description
Section Microcontroller Operation
Contents Introduction Number Systems
Computer Codes. 2.4.1 Computer Memory 2.4.2 Computer Architecture 2.4.3 Registers 2.4.4 Memory Uses 2.4.5 Memory Maps. Timing
Programming 2.6.1 Flowchart 2.6.2 Mnemonic Source Code. 2.6.3 Software Delay Program
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Table Contents
2.6.4 2.6.5 Assembler Listing View Program
Operation 2.7.1 Detailed Operation Instructions 2.7.1.1 Store Accumulator (Direct Addressing Mode) 2.7.1.2 Load Accumulator (Immediate Addressing Mode) 2.7.1.3 Conditional Branch. 2.7.1.4 Subroutine Calls Returns 2.7.2 Playing Computer.
On-Chip Peripherals 2.8.1 Serial Communications Interface (SCI) 2.8.2 Serial Peripheral Interface (SPI). 2.8.3 16-Bit Timer System. 2.8.4 Memory Peripherals 2.8.5 Other On-Chip Peripherals.
Section MC68HC705C8 Functional Data
Contents Introduction
Description. 3.3.1 Hardware Features. 3.3.2 Software Features 3.3.3 General Description Pins Connections. 3.4.1 Functions 3.4.1.1 3.4.1.2 3.4.1.3 (Maskable Interrupt Request) 3.4.1.4 RESET 3.4.1.5 TCAP 3.4.1.6 TCMP 3.4.1.7 OSC1 OSC2 3.4.1.8 PA7-PA0 3.4.1.9 PB7-PB0
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Table Contents
3.4.1.10 PC7-PC0 3.4.1.11 PD5-PD0 3.4.2 Typical Basic Connections On-Chip Memory 3.5.1 Memory Types 3.5.2 Memory Central Processor Unit 3.6.1 Registers 3.6.1.1 Accumulator 3.6.1.2 Index Register 3.6.1.3 Condition Code Register 3.6.1.4 Program Counter 3.6.1.5 Stack Pointer 3.6.2 Arithmetic/Logic Unit (ALU) 3.6.3 Control 3.6.4 Resets 3.6.4.1 Power-On Reset 3.6.4.2 Computer Operating Properly (COP) Watchdog Timer Reset 3.6.4.3 Clock Monitor Reset. Addressing Modes 3.7.1 Inherent Addressing Mode 3.7.2 Immediate Addressing Mode .103 3.7.3 Extended Addressing Mode 3.7.4 Direct Addressing Mode 3.7.5 Indexed Addressing Modes 3.7.5.1 Indexed, Offset 3.7.5.2 Indexed, 8-Bit Offset 3.7.5.3 Indexed, 16-Bit Offset 3.7.6 Relative Addressing Mode 3.7.7 Test Branch Instructions 3.7.8 Instructions Organized Type Instruction Summary
Interrupts. 3.9.1 Software Interrupt (SWI). 3.9.2 External Interrupt .131
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Table Contents
3.9.3 3.9.4 3.9.5 Timer Interrupt Serial Communications Interface (SCI) Interrupt Serial Peripheral Interface (SPI Interrupt .132
3.10 Microcontroller Input/Output 3.10.1 Parallel .133 3.10.2 Serial 3.11 Serial Communications Interface (SCI) 3.11.1 Transmitter 3.11.2 Receiver 3.11.3 Registers 3.11.3.1 Baud Rate Register (BAUD) 3.11.3.2 Serial Communications Control Register (SCCR1) .144 3.11.3.3 Serial Communications Control Register (SCCR2) .144 3.11.3.4 Serial Communications Status Register (SCSR) .145 3.11.3.5 Serial Communications Data Register (SCDAT) 3.11.4 Data Formats 3.11.5 Hardware Procedures 3.11.6 Software Procedures 3.11.6.1 Initialization Procedure. 3.11.6.2 Normal Transmit Operation 3.11.6.3 Normal Receive Operation. .149 3.11.7 Application Example 3.12 Synchronous Serial Peripheral Interface (SPI) 3.12.1 Data Movement 3.12.2 Functional Description 3.12.3 Descriptions .156 3.12.3.1 Serial Data Pins (MISO, MOSI) 3.12.3.2 Serial Clock (SCK) 3.12.3.3 Slave Select (SS) 3.12.4 Registers 3.12.4.1 Serial Peripheral Control Register (SPCR) 3.12.4.2 Serial Peripheral Status Register (SPSR) 3.12.4.3 Serial Peripheral Data Register (SPDR) .161
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Table Contents
3.13
Application Example
3.14 Programmable Timer 3.14.1 Functional Description 3.14.2 Timer Counter Alternate Counter Registers 3.14.3 Input-Capture Concept .169 3.14.4 Input-Capture Operation. 3.14.5 Output-Compare Concept 3.14.6 Output-Compare Operation 3.14.7 Timer Control Register (TCR) 3.14.8 Timer Status Register (TSR) .175 3.14.9 Timer Application Example. 3.15 STOP/WAIT Instruction Effects .177 3.15.1 Power-Consumption Modes 3.15.2 Effects On-Chip Peripherals 3.15.2.1 Timer Action During Stop Mode .180 3.15.2.2 Action During Stop Mode 3.15.2.3 Action During Stop Mode 3.15.2.4 Wait Mode Effects 3.16 OTPROM/EPROM Programming 3.16.1 Erasing 3.16.2 Programming 3.16.3 Program Register 3.16.4 Option Register
Section Applications
Contents Introduction Hardware Development Methods
Software Development Methods. .191 4.4.1 Freeware 4.4.2 Third-Party Software Thermostat Project Details 4.5.1 Hardware Details .197 4.5.2 Project Programming
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Table Contents Appendix Instruction Details
Contents Introduction M68HC05 Instruction with Carry. without Carry Logical Arithmetic Shift Left Arithmetic Shift Right Branch Carry Clear. BCLR Clear Memory Branch Carry Branch Equal BHCC Branch Half Carry Clear. BHCS Branch Half Carry Branch Higher Branch Higher Same Branch Interrupt High Branch Interrupt Test Memory with Accumulator Branch Lower Branch Lower Same Branch Interrupt Mask Clear Branch Minus. Branch Interrupt Mask Branch Equal Branch Plus. Branch Always. BRCLR Branch Clear Branch Never BRSET Branch BSET Memory Branch Subroutine. Clear Carry Clear Interrupt Mask Clear
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Table Contents
Compare Accumulator with Memory. Complement Compare Index Register with Memory Decrement. Exclusive-OR Memory with Accumulator Increment Jump Jump Subroutine Load Accumulator from Memory Load Index Register from Memory Logical Shift Left. Logical Shift Right Multiply Unsigned Negate Operation. Inclusive-OR Rotate Left thru Carry Rotate Right thru Carry. Reset Stack Pointer. Return from Interrupt. Return from Subroutine Subtract with Carry Carry Interrupt Mask Store Accumulator Memory STOP Enable IRQ, Stop Oscillator Store Index Register Memory. Subtract Software Interrupt Transfer Accumulator Index Register Test Negative Zero Transfer Index Register Accumulator WAIT Enable Interrupt, Stop Processor.
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Table Contents Appendix Review Questions
Contents Introduction Review Questions. Review Questions, Answers, Explanations
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Applications Guide M68HC05
List Figures
Figure 2-10 2-11 2-12 2-13 Title Page
Typical Computer System Temperature Control Flowchart. Thermostat Project Block Diagram Expanded Block Diagram M68HC05 Registers. Memory Circuitry Typical Memory Example Flowchart Flowchart Mnemonics Delay Routine Flowchart Mnemonics Explanation Assembler Listing Assembler Listing Memory Example Program Subroutine Call Sequence Playing Computer Worksheet Completed Worksheet
MC68HC705C8 Microcontroller Block Diagram 40-Pin Dual-In-Line Package Assignments 44-Lead PLCC Package Assignments Oscillator Connections Typical Basic Connections M68HC05 Block Diagram. MC68HC705C8 Memory Programming Model Accumulator 3-10 Index Register 3-11 Condition Code Register (CCR)
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List Figures
Figure 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 3-38 3-39 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 Title Page
Program Counter (PC). Stack Pointer (SP) Hardware Interrupt Flowchart Interrupt Stacking Order Port Data Direction Registers Port Data Direction Registers Port Data Direction Registers Parallel Port Circuitry .135 Port Fixed Input Port Transmitter Block Diagram .138 Receiver Block Diagram Baud Rate Register Rate Generator Division Serial Communications Control Register Serial Communications Control Register Serial Communications Status Register Serial Communications Data Register. Double Buffering Data Formats .147 Normal Transmit Operation Flowchart Normal Receive Operation Flowchart. Application Example Program Block Diagram. .154 Shift Register Operation Data/Clock Timing Diagram. Serial Peripheral Control Register Serial Peripheral Status Register. Serial Peripheral Data Register Application Example Diagram. Application Example Flowchart. Application Example Program. Programmable Timer Block Diagram. .167 16-Bit Counter Reads Input-Capture Operation Output-Compare Operation Timer Control Register.
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List Figures
Figure 3-48 3-49 3-50 3-51 3-52 4-10 4-11
Title
Page
Timer Status Register Timer Application Example Program .178 STOP/WAIT Flowchart Program Register. Option Register Thermostat Project Schematic Diagram Precision Temperature Sensing Circuit Port Summary Port Summary Port Summary Port Summary Display Checkout Flowchart Display Checkout Program Listing. Keypad Checkout Flowchart Keypad Checkout Program Listing Main Program Flowchart
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List Figures
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Applications Guide M68HC05
List Tables
Table Title Page
Decimal, Binary, Hexadecimal Equivalents Timeout Period versus CM0. Register/Memory Instructions Read/Modify-Write Instructions. Branch Instructions .118 Control Instructions. .119 Instruction Summary Opcode Vector Address Interrupts Reset Functions Prescaler Baud Rate Frequency Output. Transmit Baud Rate Output ASCII-Hexadecimal Code Conversion .151 Thermostat Project Parts List
3-10 3-11 3-12
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List Tables
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Applications Guide M68HC05
Section General Description
Contents
Introduction Definitions Background. Computer Systems Description Microcontroller Applications Overview Project Description
Introduction
Welcome world microcontrollers! this applications guide, will develop project using Motorola MC68HC705C8 microcontroller unit (MCU) familiar application home thermostat. MC68HC705C8 member M68HC05 Family MCUs. project will demonstrate only many possible microcontroller functions that use. This guide assumes that have knowledge microcontrollers applications experience. Section General Description begins with definitions, gives background information, describes computer systems. overview microcontroller applications also presented application project discussed. Section Microcontroller Operation describes detail microcontrollers operate.
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General Description
Section MC68HC705C8 Functional Data contains functional data Motorola MC68HC705C8 MCU. This section gives specific information needed this application. More information found slightly different form BR594/D, MC68HC705C8 Technical Summary, which available separately. Section Applications shows develop applications gives thermostat project details. Appendix Instruction Details provides detailed description each instruction MC68HC05 instruction set. Appendix Review Questions contains review questions, answers, explanations.
Definitions
heart computer central processor unit (CPU). microprocessor single chip. computer system plus peripherals such input/output (I/0) devices, memory, program, timing reference. microcontroller very small product that contains many functions found computer system. microcontroller uses microprocessor CPU) well memory peripherals same chip. microcontroller (MCU) packaged single chip that programmed user with series instructions loaded into memory.
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General Description Background
Background
Before MCUs, controllers were hard-wired electronic devices whose operation determined circuits wires contained within them. operation MCU-based controller determined primarily program instead components wires. function that implemented using hard-wired digital integrated circuits (ICs) also implemented performed MCU.
size complexity devices increase, MCUs become attractive reasons: hard-wired approach requires adding perform more complex tasks; whereas, MCUs require only longer program. Microcontrollers more versatile. change hard-wired system usually involves replacing rerouting wires. Most modifications system made simply changing program. MCUs very useful where many decisions calculations required. easier computational power computer than discrete logic. Microcontrollers being used replace existing designs because they simpler than conventional logic. Since approach programmable, many additional features possible little added cost. Programmability makes possible multiple common piece hardware since only control program needs changed.
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General Description Computer Systems Description
Whatever their size, computer systems consist same fundamental parts: CPU, devices, memory, program(s), timing reference (clock) shown Figure 1-1. processes information accordance with program instructions data particular language called machine code. controls system operations provides control signals enabling disabling various peripherals devices.
Input devices supply information from outside world. Some input devices convert analog signals into digital signals that understand manipulate. Other input devices translate realworld information into signals required MCUs. Examples this temperature sensor, switch, keypad, typewriter-style keyboard. computer system might have number these input devices.
PROGRAM
MEMORY
SWITCH INPUTS CENTRAL PROCESSOR UNIT (CPU) OUTPUTS
DISPLAY
KEYPAD
BEEPER
TEMPERATURE SENSOR
CLOCK RELAY
CRYSTAL
Figure 1-1. Typical Computer System
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General Description Computer Systems Description
Output devices controlled signals from MCU. external interface required some output devices translate levels into different voltage current levels. Liquid crystal displays, video display terminals, heating/cooling equipment examples output devices. Memory store information, including instructions data that uses. basic memory types random access memory (RAM) read-only memory (ROM).
used temporary storage data instructions. computer system write information into read information from arbitrary random order. volatile that contents lost when power removed. data instructions program) stored permanently when manufactured. read information from cannot write information into information nonvolatile that does change even when power removed. programmable read-only memory (PROM) type that programmed user. erasable programmable read-only memory (EPROM) type PROM that erased exposing ultraviolet light. Once erased, EPROM reprogrammed with instructions data. OTPROM type EPROM that manufactured inexpensive plastic package. Since plastic package opaque ultraviolet light, OTPROM programmed only once. Like ROM, PROM, EPROM, OTPROM nonvolatile types memory. program contains instructions data. computer system uses program perform some desired processes. computer clock used timing sequencing various operations. crystal usually used provide reference frequency clock.
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General Description Microcontroller Applications Overview
development microcontroller application limited only skill imagination, since elements microcontroller system easily assembled. applications generally allow many functions that make process control simpler more powerful, often reduced cost. Many applications require analog inputs outputs. resulting system equivalent traditional analog controller with number control loops. Control loops regulate output function more inputs. Control loops illustrated flowchart Figure 1-2.
START CONTROL LOOP
HEATING SELECTED TURN HEATING
TEMP COLD TURN HEATING
TURN HEATING
COOLING SELECTED TURN COOLING
TEMP TURN COOLING
TURN COOLING
Figure 1-2. Temperature Control Flowchart
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General Description Project Description
Some applications have costly sensors control mechanisms. cost sensors required input cost control devices required output usually much greater than cost standard MCU. advantage system software replace complex expensive hardware previously required. cost software tradeoff against cost additional hardware space requires.
Programming allows complex functions that could easily accomplished with hard-wired devices. Changes functions made programs improved replaced with hardware changes.
Project Description
basic thermostat controller chosen this project because should familiar readers because includes fundamental elements common applications. Figure illustrates home thermostat controller that control both heating conditioning. Since thermostat based MCU, complex functions added. thermostat could include timed setback feature that allows specifying certain times when there will reduced demand heating conditioning, thus giving some energy savings. more unusual feature would measure outdoor temperature control indoor-to-outdoor temperature difference. This would very difficult accomplish with conventional electromechanical thermostat.
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General Description
DATA ENTRY KEYPAD
CRYSTAL
DISPLAY
INTERFACE
INDOOR TEMPERATURE SENSOR
MICROCONTROLLER
BEEPER
INTERFACE OUTDOOR TEMPERATURE SENSOR INTERFACE
RELAY
HEAT
RELAY
COOL
RELAY
Figure 1-3. Thermostat Project Block Diagram four fundamental elements this system inputs, outputs, time, microcontroller other elements together. inputs include push-buttons keypad) enter time temperature information into sensors measure indoor outdoor temperatures. Outputs include display show system conditions signals interfaces that control heating conditioning equipment. Time derived from crystal connected MCU. will later, this crystal would used even application have time-of-day requirements, program controls entire operation thermostat. Section Applications this manual contains project details.
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Applications Guide M68HC05
Section Microcontroller Operation
Contents
Introduction Number Systems
Computer Codes. 2.4.1 Computer Memory 2.4.2 Computer Architecture 2.4.3 Registers 2.4.4 Memory Uses 2.4.5 Memory Maps. Timing Programming 2.6.1 Flowchart 2.6.2 Mnemonic Source Code. 2.6.3 Software Delay Program 2.6.4 Assembler Listing 2.6.5 View Program Operation 2.7.1 Detailed Operation Instructions 2.7.1.1 Store Accumulator (Direct Addressing Mode) 2.7.1.2 Load Accumulator (Immediate Addressing Mode) 2.7.1.3 Conditional Branch. 2.7.1.4 Subroutine Calls Returns 2.7.2 Playing Computer. On-Chip Peripherals 2.8.1 Serial Communications Interface (SCI) 2.8.2 Serial Peripheral Interface (SPI). 2.8.3 16-Bit Timer System. 2.8.4 Memory Peripherals 2.8.5 Other On-Chip Peripherals.
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Microcontroller Operation Introduction
microcontroller unit (MCU) complete computer system single silicon chip. great many controller applications, satisfy system requirements with additional integrated circuits (ICs). very cost high degree flexibility, these powerful devices finding their into many applications that were previously accomplished with combinational logic even mechanical means. result, there many experienced engineers need become familiar with function application Motorola MCUs. This section, which specifically designed those engineers, also good reference engineers familiar with MCUs from some other manufacturer. block Figure 1-3. Thermostat Project Block Diagram expanded shown Figure show functional blocks within MCU. block central element digital binary computer much like mainframe computers used business except that much smaller. goal this section study internal operation this interacts with other functional blocks within MCU. Although this discussion based relatively simple CPU, principles apply even most powerful mainframe computers. system simple logic elements buses that sequentially interpret execute finite instructions. Starting from specific address memory after reset, mindlessly fetches executes simple instruction after another. Each instruction composed several even simpler steps. small substeps comprising each instruction determined wiring within CPU. transistors, logic gates, buses which comprise called hardware. instructions follows accomplish application task determined user design engineer called software program. Before into discussion internal operations CPU, some basic concepts must understood. following paragraphs discuss numbering systems special codes used computers.
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Microcontroller Operation Number Systems
OSCILLATOR CLOCKS CRYSTAL RESET
CENTRAL PROCESSOR UNIT (CPU)
PROGRAM MEMORY (POWER) ADDRESS DATA MEMORY DATA
(GROUND)
PERIPHERALS DIGITAL INPUTS
DIGITAL OUTPUTS
Figure 2-1. Expanded Block Diagram
Number Systems
Computers work best with information different form than people use. Humans typically work base (decimal) numbering system (probably because have fingers). Digital binary computers work base (binary) numbering system because this allows information represented sets digits, which only zeros ones. turn, zero represented presence absence logic voltage signal line states simple switch.
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Microcontroller Operation
decimal (base numbers, weight each digit times great digit immediately right. rightmost digit decimal integer ones place, digit left tens digit, binary (base numbers, weight each digit times great digit immediately right. rightmost digit binary integer ones digit, next digit left twos digit, next fours digit, then eights digit, Although computers quite comfortable working with binary numbers even binary digits, humans find very inconvenient work with many digits time. base (hexadecimal) numbering system offers practical compromise. hexadecimal digit exactly represent four binary digits, thus, 8-bit binary number expressed hexadecimal digits. correspondence between hexadecimal digit four binary digits represents simple enough that humans work with computers easily learn mentally translate between two. hexadecimal (base numbers, weight each digit times great digit immediately right. rightmost digit hexadecimal integer ones place, digit left sixteens digit, Table demonstrates relationship between decimal, binary, hexadecimal representations values. These three different numbering systems just different ways represent same physical quantities. letters through used represent hexadecimal values corresponding through because each hexadecimal digit represent different quantities; whereas, customary numbers only include unique symbols through Thus, some other singledigit symbols used represent hexadecimal values through
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Microcontroller Operation Number Systems
Table 2-1. Decimal, Binary, Hexadecimal Equivalents
Base Decimal 1024 65,535 Base Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0001 0000 0001 0001 0110 0100 1111 1111 0100 0000 0000 1111 1111 1111 1111 Base Hexadecimal FFFF
avoid confusion about whether number decimal hexadecimal, hexadecimal numbers preceded symbol. example, means decimal "sixty-four"; whereas, means hexadecimal "six-four", which equivalent decimal 100. Some other computer manufacturers follow hexadecimal values with capital 64H). Hexadecimal good express discuss numeric information processed computers because easy people mentally convert between hexadecimal digits their 4-bit binary equivalent. hexadecimal notation much more compact than binary while maintaining binary connotations.
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Microcontroller Operation Computer Codes
Computers must handle many kinds information other than just numbers. Text (alphanumeric characters) instructions must encoded such that computer understand this information. most common code text information American Standard Code Information Interchange ASCII). ASCII code establishes widely accepted correlation between alphanumeric characters specific binary values. Using ASCII code, corresponds capital corresponds space character, etc. ASCII code translates characters 7-bit binary codes, practice information most often conveyed 8-bit characters with most significant equal zero. This standard code allows equipment made various manufacturers communicate because machines this same code. Computers another code give instructions CPU. This code called operation code opcode. Each opcode instructs execute very specific sequence steps that together accomplish intended operation. Computers from different manufacturers different sets opcodes because these opcodes internally hardwired logic. instruction specific opcodes that knows execute. Even though opcodes differ from computer another, digital binary computers perform same kinds basic tasks similar ways. MC68HC05 understand basic instructions. Some these basic instructions have several slight variations, each requiring separate opcode. instruction MC68HC05 includes unique instruction opcodes. will discuss actually executes instructions little later this section after more basic concepts have been presented. opcode such understood CPU, very meaningful human. solve this problem, system mnemonic instruction formats used. opcode corresponds INCA mnemonic, which read "increment accumulator." Although there printed information show correlation between mnemonic instructions opcodes they represent, this information seldom used programmer because translation process automatically
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Microcontroller Operation Computer Codes
handled separate computer program called assembler. assembler program that converts program written mnemonics into list machine codes (opcodes) that used CPU. engineer develops instructions computer mnemonic form then uses assembler translate these instructions into opcodes that understand. will discuss instructions, writing programs, assemblers later this applications guide, should understand that people prepare instructions computer mnemonic form computer understands only opcodes; thus, translation step required change mnemonics opcodes, this function assembler. Before leaving this discussion number systems codes, will look additional codes have heard about. Octal (base notation used some early computer work seldom used today. Octal notation uses numbers through represent sets three binary digits same hexadecimal used represent sets four binary digits. octal system advantage using customary number symbols (unlike hexadecimal symbols through discussed earlier). disadvantages caused octal abandoned hexadecimal notation used today. First all, most computers bits word; these words break down nicely into sets three bits. (Some early computers used 12-bit words which break down into four sets three bits each.) second problem that octal compact hexadecimal. example, ASCII value capital 10000012 binary, 4116 hexadecimal, 1018 octal. When human talking about ASCII value easier "four-one" than "one-zero-one." When mentally translating from hexadecimal binary, easy convert each hexadecimal digit into four binary bits. more difficult make octal-to-binary translation because have remember throw away leading zero first group three binary bits. probably think twice about that last statement, that exactly point. Binary coded decimal (BCD) hybrid notation used express decimal values binary form. uses four binary bits represent each decimal digit. Since four binary digits express different
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Microcontroller Operation
physical quantities, there will bit-value combinations that considered invalid (specifically, hexadecimal values through Values kept pseudo-decimal form during calculations. When computer does operation, performs binary addition then adjusts result back form. simple example, consider addition 1010. computer adds 0000 10012 0000 00012 0000 10102, 10102 equivalent A16, which valid value. When computer finishes calculation, check performed result still valid value. there carry from digit another there invalid code, sequence steps would performed correct result proper form (0000 10102 corrected 0001 00002 (BCD this example). most cases, inefficient notation computer calculations. better change from decimal binary information entered, computer calculations binary, change binary result back decimal needed display. First, computers capable doing calculations because they need digit-to-digit carry indicator which present computers (though Motorola MCUs have this half-carry indicator). Secondly, forcing computer emulate human behavior inherently less efficient than allowing computer work native binary system.
2.4.1 Computer Memory Before operation discussed detail, some conceptual knowledge computer memory required. many beginning programming classes, memory presented being similar matrix pigeon holes where save messages other information. pigeon holes referring like mailboxes large apartment building. This good analogy needs little refinement used explain inner workings CPU. will confine discussion 8-bit that very specific.
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Microcontroller Operation Computer Codes
8-bit CPU, each pigeon hole mailbox) thought containing eight on/off switches (eight bits data called byte data). Unlike pigeon hole, cannot more information writing smaller, there such thing empty pigeon hole (though contents memory location unknown undefined given time). switches would where each switch would represent single binary digit. binary corresponds switch being binary zero corresponds switch being off. Each pigeon hole (memory location) unique address that information stored reliably retrieved.
2.4.2 Computer Architecture Motorola M68HC05 M68HC11 8-bit MCUs have specific organization which called Neumann architecture after American mathematician same name. this architecture, memory array interconnected address data bus. address used identify which pigeon hole being accessed, data used convey information either from memory location (pigeon hole) from memory location CPU. Motorola implementation this architecture, there special pigeon holes (called registers) inside CPU, which small scratch control panel CPU. These registers similar memory that information written into them remembered. However, important remember that these registers directly wired into part addressable memory available CPU. information (other than registers) accessible envisioned CPU) single several thousand pigeon holes. This organization sometimes called 'memory-mapped I/O' system because treats memory locations alike whether they contain program instructions, variable data, input-output (I/O) controls. There other computer architectures, this applications guide intended explore these variations. Fortunately,
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Microcontroller Operation
Motorola architecture discussing easiest understand use. This architecture encompasses most important concepts digital binary computers; thus, information presented this applications guide will applicable even study other architectures. number wires address determines total possible number pigeon holes; number wires data determines amount information that stored each pigeon hole. MC68HC705C8, address bits, making maximum 819210 separate pigeon holes jargon would this access locations). Since data MC68HC705C8 eight bits, each pigeon hole hold byte information. byte eight binary digits, hexadecimal digits, ASCII character, decimal value from 255.
2.4.3 Registers Different CPUs have different sets registers. differences primarily number size registers. Figure shows registers found M68HC05. While this relatively simple registers, representative types registers used explain fundamental concepts. register, 8-bit scratch-pad register, also called accumulator because often used hold operands result arithmetic operation. register 8-bit index register, which also serve simple scratch pad. main purpose index register point area memory where will load (read) store (write) information. Sometimes index register called pointer register. will learn more about index registers when discuss indexed addressing modes.
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Microcontroller Operation Computer Codes
ACCUMULATOR INDEX REGISTER PROGRAM COUNTER CONDITION CODE REGISTER STACK POINTER
CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM
Figure 2-2. M68HC05 Registers program counter (PC) register used keep track address next instruction executed. When reset (starts up), loaded from specific pair memory locations called reset vector. reset vector locations contain address first instruction executed CPU. instructions executed, logic increments such that always points next piece information that will need. number bits exactly matches number wires address bus. This determines total potentially available memory space that accessed CPU. case MC68HC705C8, bits long; therefore, access Kbytes (8192) memory. Values this register expressed four hexadecimal digits where upper-order three bits corresponding 16-bit binary address always zero. condition code (CC) register 8-bit register holding status indicators that reflect result some prior operation. three high-order bits this register used always stay logic one.
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Branch instructions these status bits make simple either decisions. stack pointer (SP) used pointer next available location last-in-first-out (LIFO) stack. stack thought pile cards, each holding single byte information. given time, card stack take card stack. Cards within stack cannot used unless cards piled removed first. accomplishes this stack effect points memory location (pigeon hole), which thought next available card. When pushes piece data onto stack, data value written into pigeon hole pointed then decremented points next previous memory location (pigeon hole). When pulls piece data stack, incremented points most recently used pigeon hole, data value read from that pigeon hole. When first started after reset stack pointer (RSP) instruction, points specific memory location certain pigeon hole).
2.4.4 Memory Uses computer memory holds information needed computer instructions, variable data, even status controls. Some memory locations contain fixed data like instructions tables constant data. This information typically held read-only memory (ROM) although there special requirement that this information located ROM. second type information used computers variable information that changes often during operation system. This type data typically held read-write random-access memory (RAM). Information read from written various locations arbitrary random order. third type information found computer system status control information. This type memory location allows computer system information from outside world. This type memory location unusual because information sensed and, changed something other than CPU.
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simplest kind memory locations simple input port simple output port. 8-bit MCU, simple input port would consist eight pins that read CPU. simple output port would consist eight pins that control (write to). practice, simple output port location usually implemented with eight latches feedback paths that allow read back what previously written address output port. Figure shows equivalent circuit RAM, input port, typical output port having readback capability. real MCU, this circuit would repeated eight times make single 8-bit location, input port, output port. When stores value address that corresponds Figure (a), WRITE signal activated latch data from data line into flip-flop [1]. This latch static remembers value written until value written this location power removed). When reads address this bit, READ signal activated, which enables multiplexer [2]. This multiplexer couples data from output flip-flop into data line. real MCU, bits actually much simpler than shown here, they functionally equivalent this circuit. When reads address input port shown Figure (b), READ signal activated, which enables multiplexer [3]. multiplexer couples buffered data from onto data line. write this address would have meaning. When stores value address that corresponds output port Figure (c), WRITE signal activated latch data from data line into flip-flop [4]. output this latch, which buffered buffer driver [5], appears digital level output pin. When reads address this output port, READ signal activated, which enables multiplexer [6]. This multiplexer couples data from output flip-flop onto data line.
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READ
DATA (n=0, 1.OR WRITE
READ DATA (n=0, 1.OR
BUFFER DIGITAL INPUT
Input Port
READ
DATA (n=0, 1.OR WRITE
BUFFER DRIVER
DIGITAL OUTPUT
Output Port with Readback
Figure 2-3. Memory Circuitry
2.4.5 Memory Maps Since there several thousand memory locations system, important have convenient track locations. memory pictorial representation total memory space. Figure typical memory showing subset memory resources MC68HC705C8. Some memory areas (reserved Motorola use) were purposely left this figure make easier understand. complete version this memory found Figure 3-7. MC68HC705C8 Memory Map.
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$0000 $001F $0020
BYTES MOTOROLA BYTES INSET
$004F $0050 BYTES $00BF $00C0
STACK BYTES $00FF $0100
USER PROM 7680 BYTES
PORT DATA REGISTER PORT DATA REGISTER PORT DATA REGISTER PORT FIXED INPUT REGISTER PORT DATA DIRECTION REGISTER PORT DATA DIRECTION REGISTER PORT DATA DIRECTION REGISTER UNUSED UNUSED UNUSED CONTROL REGISTER STATUS REGISTER DATA REGISTER BAUD RATE REGISTER CONTROL REGISTER CONTROL REGISTER STATUS REGISTER DATA REGISTER TIMER CONTROL REGISTER TIMER STATUS REGISTER INPUT-CAPTURE REGISTER (HIGH) INPUT-CAPTURE REGISTER (LOW) OUTPUT-COMPARE REGISTER (HIGH) OUTPUT-COMPARE REGISTER (LOW) TIMER COUNT REGISTER (HIGH) TIMER COUNT REGISTER (LOW) ALT. COUNT REGISTER (HIGH) ALT. COUNT REGISTER (LOW) EPROM PROGRAM REGISTER RESET REGISTER CONTROL REGISTER UNUSED
$1EFF $1F00
MOTOROLA BYTES
$1FF3 $1FF4 $1FFF
USER PROM VECTORS BYTES
VECTOR (HIGH) VECTOR (LOW) VECTOR (HIGH) VECTOR (LOW) TIMER VECTOR (HIGH) TIMER VECTOR (LOW) VECTOR (HIGH) VECTOR (LOW) VECTOR (HIGH) VECTOR (LOW) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE)
$1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF
INSET PORT DATA DIRECTION REGISTER
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Figure 2-4. Typical Memory
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four-digit hexadecimal values along left edge Figure addresses beginning with $0000 increasing $1FIFF bottom. $0000 corresponds first memory location selected (when drives address lines internal address logic zero). $1FFF corresponds last memory location selected (when drives address lines internal address logic one). labels within vertical rectangle identify what kind memory (RAM, PROM, registers, etc.) resides particular area memory.
Some areas, such registers, need shown more detail because important know names each individual location. vertical rectangle interpreted 8192 pigeon holes (memory locations). Each these 8192 memory locations contains eight bits data shown inset Figure 2-4. first memory locations ($0000-$00FF) accessed with direct addressing mode many instructions. this addressing mode, assumes that upper hexadecimal digits address always zeros; thus, only low-order digits address need explicitly given instruction. on-chip registers bytes located $0000-$00FF area memory. memory (Figure 2-4), expansion area memory identifies each register location with low-order digits address rather than full four-digit address. example, two-digit hexadecimal value appears right port data register, which actually located address $0000 memory map. that have some background knowledge computer memory, continue with discussion CPU.
Timing
high-frequency clock source (typically derived from crystal connected MCU) used control sequencing instructions. Typical MCUs divide basic crystal frequency more arrive bus-rate clock. Each memory read write takes bus-rate clock cycle. case MC68HC705C8 MCU, 4-MHz
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(maximum) crystal oscillator clock divided arrive 2-MHz (maximum) internal processor clock. Each substep instruction takes cycle this internal processor clock (500 ns). Most instructions take five these substeps; thus, capable executing about 500,000 instructions every second.
Programming
this point, will write short program mnemonic form, translate into machine code, discuss would execute program. This exercise will provide insight into internal operation computers general. instruction explanations process writing programs will more understandable with this background. program will read state switch connected input pin. When switch closed, program will cause connected output light about second then out. will light again until switch been released closed again. length time switch held closed will affect length time lighted. Although this program very simple, demonstrates most common elements application program. First, demonstrates program sense input signals such switch closures. Second, this example program controlling output signal. Third, on-time about second demonstrates program used measure real time. Because algorithm sufficiently complicated, cannot accomplished trivial manner with discrete components minimum, one-shot with external timing components would required). This example demonstrates that user-defined program (software) replace complex circuits.
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2.6.1 Flowchart Figure flowchart example program. Flowcharts often used planning tool writing software programs because they show function flow program under development. importance notes, comments, documentation software cannot overemphasized. Just would consider circuit-board design complete until there schematic diagram, parts list, assembly drawing, should consider program complete until there commented listing comprehensive explanation program such flowchart.
2.6.2 Mnemonic Source Code Once flowchart plan completed, programmer develops series assembly language instructions accomplish functions called each block plan. programmer limited selecting instructions from instruction being used this case MC68HC05). programmer writes instructions mnemonic form which easy understand. Figure shows mnemonic source code next flowchart example program what instructions used accomplish each block flowchart. meanings mnemonics used right side Figure found Appendix Instruction Details. During development program instructions, noticed that time delay needed three places. subroutine developed that would generate 50-ms delay. This subroutine used directly places (for switch debouncing) made one-second delay easier produce. keep this figure simple, comments that would usually included within source program documentation omitted. comments will shown complete assembly listing Figure 2-9.
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FLOWCHART BEGIN
INITIAL CONDITIONS: PORT OUTPUTS DATA PATTERN 1110 0000 PORT
READ SWITCH
CLOSED DELAY DEBOUNCE
TURN
DELAY SECOND
TURN
SWITCH STILL CLOSED DELAY DEBOUNCE
Figure 2-5. Example Flowchart
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FLOWCHART BEGIN
MNEMONIC PROGRAM
INITIAL CONDITIONS: PORT OUTPUTS DATA PATTERN 1110 0000 PORT
INIT
#$FF DDRC #$E0 PORTC
READ SWITCH
PORTB
CLOSED DELAY DEBOUNCE
DLY50
TURN
BCLR
PORTC
DELAY SECOND
DLYLP
DECA BSET
DLY50 DLYLP PORTC
TURN
SWITCH STILL CLOSED DELAY DEBOUNCE
OFFLP
BRSET
PORTB, OFFLP
DLY50
Figure 2-6. Flowchart Mnemonics
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2.6.3 Software Delay Program Figure shows expanded flowchart 50-ms delay subroutine. subroutine relatively small program which performs some commonly required function. Even function needs performed many times course program, subroutine only written once. Each place where this function needed, programmer would call subroutine with branch-to-subroutine (BSR) jump-tosubroutine (JSR) instruction.
START SUBROUTINE
(JSR)
SAVE ACCUMULATOR
DLY50
TEMP1
LOAD VALUE CORRESPONDING 50mS OUTLP DECREMENT COUNT INNRLP
CLRX DECX DECA
INNRLP
COUNT EXPIRED RESTORE ACCUMULATOR
OUTLP
TEMP1
RETURN FROM SUBROUTINE
Figure 2-7. Delay Routine Flowchart Mnemonics Before starting execute instructions subroutine, address instruction which follows BSR) automatically stored temporary memory locations. When finishes executing instructions within subroutine, return-from-subroutine (RTS) instruction performed last instruction subroutine. instruction causes recover previously saved return
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address; thus, continues program with instruction following BSR) instruction that originally called subroutine. delay routine Figure involves inner loop (INNRLP) within another loop (OUTLP). inner loop consists instructions executed times before reaches branch condition fails. This amounts cycles µs/cycle times 256, which equals 1.536 inner loop. outer loop executes times. total execution time outer loop 32(1536 32(1545) 49.44 miscellaneous instructions this routine other than those outer loop total cycles; thus, total time required execute DLY50 routine 49.461 including time required instruction that calls DLY50. 16-bit timer system MC68HC705C8 also used measure time. timer-based approach actually preferred because perform other tasks during delay, delay time dependent exact number instructions executed DLY50.
2.6.4 Assembler Listing After complete program subprogram written, must converted from mnemonics into binary machine code that later execute. separate computer system, such used perform this conversion machine language. computer program called assembler used. assembler reads mnemonic version program (also called source version program) produces machine-code version program form that programmed into memory MCU. assembler also produces composite listing showing both original source program (mnemonics) object code translation. This listing used during debug phase project part documentation software program. Figure shows listing which results from assembling example program. Comments were added before program assembled.
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Section Applications should thoroughly studied before attempting sample programs this guide. Some sample programs were developed another member M68HC05 Family which slightly different memory than MC68HC705C8. Minor modifications necessary successfully these programs MC68HC705C8. Refer Figure following discussion. This figure shows some lines listing with reference numbers indicating various parts line. first line example assembler directive line. This line really part program; rather, provides information assembler that real program converted properly into binary machine code. EQU, short equate, used give specific memory location binary number name which then used other program instructions. this case, directive being used assign name PORTB value $01, which address port MC68HC705C8. easier programmer remember mnemonic name PCRTB rather than anonymous numeric value $01. When assembler encounters these names, name automatically converted corresponding binary value much same that instruction mnemonics converted into binary instruction codes.
0001 00a0 00a8 -[1]
PORTB -[3]
-[4]
PORTB -[5]
Direct address port (sw) Program will start $00A0 Read Port -[6]->
Figure 2-8. Explanation Assembler Listing
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Simple 68HC05 Program Example Read connected bit-7 port closed When closes, light about Sec; when port wait release, then repeat. Debounce 50ms 0001 0002 0005 0006 009f PORTB PORTC DDRB DDRC TEMP1 Direct address port (sw) Direct address port (LED) Data direction control, port Data direction control, port byte temp storage location Program will start $00A0
00a0
$00A0 '705C8 INIT
00a0 00a2 00a4 00a6
00a8 00aa 00ac 00af 00bl 00b3 00b6 00b7 00b9 00bb 00be 00cl
#$FF Begin initialization DDRC port outputs Port configured inputs default from reset. #$E0 green LEDs beeper PORTC Turn Some pins port board) happen connected devices which don't apply this example program. pattern turns stuff turns BCLR DECA BSET BRSET PORTB DLY50 6,PORTC DLY50 DLYLP 6,PORTC 7,PORTB,OFFLP DLY50 Read Port Loop till (Neg trick) Delay about debounce Turn (bit-6 zero) Decimal assembles Delay Loop counter loops times (20-19,19-18-1-0) Turn back Loop here till. Debounce release Look next closure
DLYLP
OFFLP
00c3 00c5 00c7 00c8 00c9 00cb 00cc 00ce 00d0
DLY50-Subroutine delay '-50ms Saves original accumulator value will always zero return DLY50 TEMP1 Save accumulator outer loop times OUTLP CLRX used inner loop count INNRLP DECX O-FF, FF-FE,.1-0 loops INNRLP 6cyc*256*1 µS/cyc 1.536ms DECA 32-31, 31-30,.1-0 OUTLP 1545cyc*32*1 µS/cyc 49.440ms TEMP1 Recover saved Accumulator Return
Figure 2-9. Assembler Listing
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second line shown Figure another assembler directive. mnemonic ORG, which short originate, tells assembler where program will start (the address start first instruction following directive line). directives used more than once program tell assembler different parts program specific places memory. Refer memory select appropriate memory location where program should start.
this assembler listing, first fields, [2], generated assembler, last four fields, [3], [4], [5], [6], original source program written programmer. Field label (TOP) which referred other instructions. example program, last instruction "BRA TOP", which simply means will continue execution with instruction that labeled "TOP". When programmer writing program, addresses where instructions will located typically known. Worse yet, branch instructions, rather than using address destination, uses offset (difference) between current value destination address. Fortunately, programmer does have worry about these problems because assembler takes care these details through system labels. This system labels convenient programmer identify specific points program (without knowing their exact addresses); assembler later convert these mnemonic labels into specific memory addresses even calculate offsets branch instructions that them. Field instruction field. mnemonic short load accumulator. Since there variations (different opcodes) load accumulator instruction, additional information required before assembler choose correct binary opcode during execution program. Field operand field, providing information about specific memory location value operated instruction. assembler uses both instruction mnemonic operand specified source program determine specific opcode instruction. different ways specifying value operated called addressing modes more complete discussion addressing modes
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presented later). syntax operand field slightly different each addressing mode assembler determine correct intended addressing mode from syntax operand. this case, operand PORTB, which assembler automatically converts (recall directive). assembler interprets direct addressing mode address between $0000 $00FF, thus selecting opcode $136, which direct addressing mode variation LIDA instruction. PCRTB been preceded symbol, that syntax would have been interpreted assembler immediate addressing mode value, opcode would have been chosen instead $B6. Field called comment field used assembler translate program into machine code. Rather, comment field used programmer document program. Although does this information during program execution, good programmer knows that most important parts good program. comment this line program says "read port This comment tells someone reading listing port being read, which essential understanding program works. entire line made into comment line using asterisk first character line. addition good comments listing, also important document programs with flowchart other detailed information explaining overall flow operation program.
2.6.5 View Program Figure 2-10, memory MC68HC705C8, shows example program fits memory MCU. This figure same Figure except that different portion memory space been expanded show contents locations program. Figure 2-10 shows that sees example program linear sequence binary codes, including instructions operands successive memory locations. begins this program with program counter (PC) pointing first byte program. Each instruction opcode tells many any) what type operands with that instruction. this way, remain
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aligned instruction boundaries even though mixture opcodes operands looks confusing Most application programs would located ROM, EPROM, OTPROM. This example program loaded into area avoid having program (and later erase) EPROM. There special requirement that instruction must ROM-type memory execute. concerned, program just series binary patterns which sequentially processed.
Carefully study program listing Figure memory Figure 2-10. Find first instruction DLY50 subroutine Figure then find same bytes Figure 2-10. should have found following line from near bottom Figure 2-9.
00c3 DLY50 TEMP1 Save accumulator
outlined section memory Figure 2-10 area should have identified.
Operation
This section will first discuss detailed operation instructions then explain would execute example program. detailed descriptions typical instructions intended make think like CPU. then through example program using teaching technique called "playing computer" which pretend interpreting executing instructions program.
2.7.1 Detailed Operation Instructions Before seeing would execute example program, would help know detail) breaks down instructions into fundamental operations performs these tiny steps accomplish desired instruction. will see, many small steps execute very quickly very accurately within each instruction, none small steps very complicated.
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$0000 $001F $0020
BYTES MOTOROLA BYTES
$004F $0050 BYTES EXAMPLE PROGRAM
$009F $00A0
$00FF $0100
USER PROM 7680 BYTES
$1EFF $1F00
MOTOROLA BYTES
$1FF3 $1FF4 $1FFF
USER PROM VECTORS BYTES
$00A0 $00A1 $00A2 $00A3 $00A4 $00A5 $00A6 $00A7 $00A8 $00A9 $00AA $00AB $00AC $00AD $00AE $00AF $00B0 $00B1 $00B2 $00B3 $00B4 $00B5 $00B6 $00B7 $00B8 $00B9 $00BA $00BB $00BC $00BD $00BE $00BF $00C0 $00C1 $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF $00D0
$00C3 $00C4
Figure 2-10. Memory Example Program logic circuitry inside would seem straightforward design engineer accustomed working with logic even relay logic. What sets apart from these other forms digital logic packing density. Very large scale integration (VLSI) techniques have made possible equivalent thousands integrated circuits single silicon die. arranging these logic gates form CPU, general-purpose instruction executer
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capable acting universal logic element. placing different combinations instructions device, perform virtually definable function. typical instruction takes five cycles internal processor clock. Although normally important know exactly what happens during each these execution cycles, help through instructions detail understand works internally. 2.7.1.1 Store Accumulator (Direct Addressing Mode) Look instruction Appendix Instruction Details. table bottom page, that direct addressing mode version store accumulator instruction. also that instruction requires bytes, specify opcode ($B7) second specify direct address where accumulator will stored. (The bytes shown machine code column table.) will discussing addressing modes more detail later, following brief description will help understanding executes this instruction. direct addressing modes, assumes address range $0000 through $00IFF; thus, there need include upper byte address operand instruction (since always $00). table bottom description found Appendix Instruction Details shows that direct addressing version instruction takes four cycles execute. During first cycle this instruction, reads opcode $B7, which identifies instruction direct addressing version instruction advances next memory location. During second cycle, places value from internal address reads low-order byte direct address ($02 example). uses third cycle this instruction internally construct full address where accumulator stored, also advances points next address memory (the address opcode next instruction).
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this example, appends assumed value (because direct addressing mode) that read during second cycle instruction arrive complete address $0002. During fourth cycle this instruction, places this constructed address ($0002) internal address bus, places accumulator value internal data bus, asserts write signal. That writes contents accumulator $0002 during fourth cycle instruction.
This explanation left certain details, such setting condition code flags, gives idea what occurs within during execution single instruction. 2.7.1.2 Load Accumulator (Immediate Addressing Mode) Next, look instruction Appendix Instruction Details. immediate addressing mode version this instruction appears machine code column table bottom page. This version instruction takes internal processor clock cycles execute. opcode tells byte data that immediately follows opcode this value accumulator. During first cycle this instruction, reads opcode advances point next location memory (the address immediate operand ii). During second cycle instruction, reads contents byte following opcode into accumulator advances point next location memory (i.e., opcode byte next instruction). While accumulator being loaded, bits condition code register were cleared according data that loaded into accumulator. Boolean logic formulae these bits appears near middle instruction page. will value loaded into accumulator $00; otherwise, will cleared. will most significant value loaded logic one; otherwise, will cleared. (negative) condition code used detect sign twos-complement number. twos-complement numbers, most
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significant used sign bit, indicates negative value, zero indicates positive value. also used simple indication state most significant binary value. 2.7.1.3 Conditional Branch Branch instructions allow select program flow paths, depending upon state particular memory various condition code bits. condition checked branch instruction true, program flow proceeds specified location memory. condition checked branch true, proceeds instruction following branch instruction. Decision blocks flowchart correspond conditional branch instructions program. Most branch instructions contain bytes, opcode relative offset byte. Branch clear (BRCLR) branch (BRSET) instructions require three bytes: opcode, one-byte direct address specify memory location tested), relative offset byte. relative offset byte interpreted twos-complement signed value. branch condition checked true, this signed offset added reads next instruction from this calculated address. branch condition true, just continues next instruction after branch instruction. following excerpt from Figure demonstrates useful conditional branch based condition code that sometimes overlooked.
00a8 00aa 00ac PORTB DLY50 Read Port Loop till (Neg trick) Delay about debounce
first line means "load accumulator with value port MCU." most significant this port connected normally opened switch pulldown resistor. When switch pressed (closed), logic applied port pin. PCRTB instruction executed when switch opened, condition code will cleared. Conversely, PORTB instruction executed when switch closed, condition code will set.
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second line listing (BPL TOP) read "branch plus TOP." response this instruction, either branches back first line this program falls third line program, depending condition condition code bit. condition code clear, branches first line program. This corresponds interpreting value previously read from port positive value; hence, instruction name "branch plus." Tricks such that just described only read respond conditions. following lines code would accomplish same effect three lines which used N-bit trick.
00a8 00ab BRCLR PORTB, DLY50 Loop till closed Delay about debounce
first line this sequence read "branch port clear." this particular case, second sequence better than first sequence several reasons. second sequence more straightforward (less chance confusion), takes less byte machine code, executes cycle faster than three-line sequence. However, some cases operand (PORTB) needed accumulator some other reason; thus, first instruction sequence based N-bit trick becomes slightly better choice. From practical point view, differences between these approaches very small, either would work well application. 2.7.1.4 Subroutine Calls Returns jump-to-subroutine (JSR) branch-to-subroutine (BSR) instructions automate process leaving normal linear flow program execute instructions then return where normal flow left off. instructions outside normal program flow called subroutine. instruction used from running program subroutine return-fromsubroutine (RTS) instruction used return program from which subroutine called. following shows lines assembler listing which will used demonstrate executes subroutine call. Assume that
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stack pointer (SP) points address $00FF when encounters instruction location $0102.
0100 0102 0105 0201 0203 DECA #$02 SUBBY SUBBY Load immediate value subroutine Store accumulator port Decrement accumulator Loop till accumulator Return from subroutine
SUBBY
Refer Figure 2-11 during following discussion. will begin explanation with executing instruction "LDA #$02" address $0100. left side figure shows normal program flow composed LIDA #$20, SUBBY, that order) consecutive memory locations. right half figure shows subroutine instructions SUBBY DECA, SUBBY, RTS. Each number square brackets indicates cycle internal processor clock. cycle numbers will used references following explanation this figure.
START
$0100 #$02 $0101 $0102 SUBBY $0103 $0104
[27] [28] [29] [30]
[15] [16] [17] [18] [19] [20]
[10] [11] [12] [13] [14] [21] [22] [23] [24] [25] [26]
$0200
SUBBY
DECA
$0201 $0202 $0203 SUBBY
$0105 $0106
Figure 2-11. Subroutine Call Sequence
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reads opcode from location $0100 (LIDA immediate). reads immediate data from location $0101 into accumulator. reads opcode from location $0102 (JSR extended). reads high-order extended address from $0103. reads low-order extended address from $0104. builds full address subroutine ($0200). writes $00FF decrements $00FE. Another this "push low-order half return address stack." writes $00FE decrements $00FD. Another this "push high-order half return address stack." return address that saved stack $0105, which address instruction that follows instruction. reads opcode from location $0200. This first instruction called subroutine. DECA instruction takes three cycles ([9], [10], [11]). reads opcode ($26) from location $0201. reads relative offset ($FD) from $0202. During #$02 instruction [1], accumulator loaded with value during DECA instruction [9], accumulator decremented (which equal zero). Thus, [14] branch condition true, twos-complement offset ($FD added internal (which $0203 time) value $0200.
[10] [11] [12] [13] [14]
[15] [19] Repeat cycles through [13] except that when DECA instruction [15] executed this time, accumulator went from $00.
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[20] [21]
Since accumulator "equal zero," [19] branch condition true, branch will taken. reads opcode ($81) from $0203.
[22] [26] takes cycles. During last five cycles this instruction, incremented $00FE, high-order return address ($01) read from stack ($00FE), incremented again $00FF, low-order return address ($05) read from stack ($00FF), loaded with this recovered return address ($0105). [27] [28] [29] [30] reads direct opcode ($B7) from location $0105. reads low-order direct address ($02) from location $0106. direct instruction takes total four cycles. During these last cycles instruction, constructs complete address where accumulator will stored appending (assumed value high-order half address direct addressing mode) read during [28]. accumulator ($00 this time) then stored this constructed address ($0002).
2.7.2 Playing Computer Playing computer learning exercise where pretend that executing program. Programmers often mentally check programs playing computer they read through software routine. While playing computer, necessary break instructions down individual processor cycles. Instead, instructions treated single complete operation rather than several detailed steps. following paragraphs demonstrate process playing computer going through subroutine-call exercise Figure 2-11. playing-computer approach analyzing this sequence much less detailed than cycle-by-cycle analysis done earlier Figure 2-11, accomplishes same basic goal i.e., shows what happens executes sequence. After seeing this exercise,
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should attempt same thing with larger program such example Figure 2-10. begin process preparing worksheet like that shown Figure 2-12. This sheet includes mnemonic program machine code that assembles (You could alternately choose listing positioned next worksheet.) worksheet also includes register names across sheet with ample room below write values registers change course program.
STACK POINTER
ACCUMULATOR
CONDITION CODES
INDEX REGISTER
PROGRAM COUNTER
$00FC $00FD $00FE $00FF
0100 0102 0105 PORT 0200 0201
PRXAMIN LIST
SUBBY DECA SUBBY
#$02 SUBBY
LOAD IMMEDIATE VALUE SUBROUTINE STORE ACCUMULATOR DECREMENT ACCUMULATOR LOOP TILL ACCUMULATOR
Figure 2-12. Playing Computer Worksheet
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Microcontroller Operation Operation
this worksheet, there area keeping track stack. After become comfortable with stack works, would probably leave this section off, will instructive leave here now. value saved stack, will cross prior value write value right horizontal row. must also update (decrement) value crossing prior value writing value beneath under heading worksheet. value recovered from stack, would update (increment) value crossing value writing value below would then read value from location pointed wherever belongs (e.g., upper lower half PC). Figure 2-13 shows worksheet will look after working through whole sequence. Follow numbers square brackets process explained. During process, many values were written later crossed out; line been drawn from square bracket either value crossed mark show which item reference number applies Beginning sequence, should pointing $0100 [1], should pointing $00FF (due earlier assumption). reads executes #$02 instruction (load accumulator with immediate value $02); thus, write accumulator column replace value with $0102, which address next instruction. load accumulator instruction affects bits. Since value loaded $02, would cleared, would cleared [5]. This information found Appendix Since other bits affected LIDA instruction, have knowing what they should this time, question marks unknown positions [5].
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Microcontroller Operation
STACK POINTER $00FF $00FE $00FD [18] $00FE [19] $00FF
ACCUMULATOR [11] [14]
CONDITION CODES
INDEX REGISTER
PROGRAM COUNTER $0100 $0102 [10] $0200 [12] $0201 [13] $0200 [16] $0201 [17] $0203 [20] $0105
[15]
$0002 PORT [21] $00FC $00FD $00FE $00FF
0100 0102 0105 0200 0201 0203
SUBBY
DECA
#$02 SUBBY SUBBY
LOAD IMMEDIATE VALUE SUBROUTINE STORE ACCUMULATOR PORT DECREMENT ACCUMULATOR LOOP TILL ACCUMULATOR RETURN FROM SUBROUTINE
Figure 2-13. Completed Worksheet Next, reads SUBBY instruction. Temporarily remember value $0105, which address where should come back after executing called subroutine. saves low-order half return address stack; thus, write location pointed ($00FF) decrement $00FE. then saves high-order half return address stack; write $00FE again decrement (this time $00FD). finish instruction, load with $0200 [10], which address called subroutine.
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Microcontroller Operation Operation
fetches next instruction. Since $0200, executes DECA instruction, first instruction subroutine. cross accumulator column write value [11]. also change $0201 [12]. Because DECA instruction changed accumulator from (which zero negative), remain clear. Since were already cleared [5], leave them alone worksheet. executes SUBBY instruction. Since clear, branch condition met, will take branch. Cross $0201 under write $0200 [13]. again executes DECA instruction. accumulator changed from [14] (which zero negative); thus, set, remains clear [15]. advances next instruction [16]. executes SUBBY instruction, this time branch condition true now), branch will taken. simply falls next instruction (the $0203). Update $0203 [17]. instruction causes recover previously stacked Pull high-order half from stack incrementing $00FE [18] reading from location $00FE. Next, pull low-order half address from stack incrementing $00FF [19] reading from $00FF. address recovered from stack replaces value [20]. reads instruction from location $0105. Program flow returned main program sequence where left when subroutine called. (direct addressing mode) instruction writes accumulator value direct address ($0002), which port MC68HC705C8. from worksheet that current value accumulator $00; therefore, eight pins port would driven (provided they configured outputs this time). Since original worksheet have place marked recording value port would make place write there [21].
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Microcontroller Operation
larger program, worksheet would have many more crossed values time done. Playing computer worksheet like this good learning exercise, but, programmer gains experience, process would simplified. first simplifications would quit keeping track because learn trust take care this you. Another simplification worksheet stop keeping track condition codes. When branch instruction which depends condition code encountered, mentally work backwards decide whether branch should taken. Next, storage values stack would skipped, although still good idea keep track value because fairly common have programming errors resulting from incorrect values fundamental operating principle stack that over period time, same number items must removed from stack were stack. Just left parentheses must matched with right parentheses mathematical formula, JSRs BSRs must matched subsequent RTSs program. Errors which cause this rule broken will appear erroneous values while playing computer. Even experienced programmer will play computer occasionally solve some difficult problem. procedure experienced programmer would much less formal than what explained here, still amounts placing yourself role working what happens program executed.
On-Chip Peripherals
peripheral block circuitry which performs some useful function under control CPU. example peripheral universal asynchronous receiver/transmitter (UART), which acts interface between computer asynchronous serial communication link. most common example such communication link RS-232 RS-422 serial port computer. This standard universal that
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Microcontroller Operation On-Chip Peripherals
almost every personal mainframe computer made anywhere world least such port. Before developed, computer designer separate UART integrated circuit include this serial interface function computer. Often number other miscellaneous logic gates were also needed interface UART buses. Since level integration allows thousands logic gates included single integrated circuit, practical several peripherals, including this UART function, same chip along with memories. on-chip serial communications interface (SCI) MC68HC705C8 UART-type peripheral. important manufacturer select peripheral functions that will useful many potential users inclusion chip. This pressure make on-chip peripherals satisfy requirements many customers possible causes need user-selectable options modify operation on-chip peripherals. MC68HC705C8 control registers, which allow user select which parallel pins will inputs which will outputs. Although application likely need only specific mixture inputs outputs, twenty different applications likely need dozen collective mixtures. ability specify direction each time makes this ideal many different applications. Control registers controlled essentially same digital output port. could think control/status registers internal registers connected internal logic rather than pins. change voltage level output pin, writes digital value address output port register. level each output port register controls voltage level corresponding pin. case control register, state control register determines logic level internal control signal rather than pin. Section MC68HC705C8 Functional Data this applications guide, will find more complete descriptions on-chip peripherals MC68HC705C8.
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2.8.1 Serial Communications Interface (SCI) system MC68HC705C8 UART-type asynchronous serial communications interface. most common this peripheral implement RS-232 interface host computer system (such personal computer). system used communicate over relatively long distances. normal applications, simply writes data parallel data register send formatted serial character. peripheral system takes care details transforming data into proper serial format, including addition start stop bits required meet standards. transmitter even allows characters queued transmission, thus allowing more time prepare additional characters. receiver portion automatically detects start character intelligently samples incoming serial data assure correct reception, even noisy applications. activity related receiving serial data converting parallel data performed within peripheral logic with intervention CPU. After character received, simply reads data byte from receive data register. number options offered allow various data rates (baud rates), alternate character formats, automatic standby /wakeup feature. choose between software polling interrupts detection status.
2.8.2 Serial Peripheral Interface (SPI) system MC68HC705C8 separate from system used primarily communications with standard peripheral logic chips same circuit board MCU. examples chips that serial-to-parallel parallel-to-serial shift registers, peripherals, peripherals, many others. system works like distributed 16-bit shift register which half shifter (SPI), other half peripheral. When initiates transfer, this distributed shifter rotated eight
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Microcontroller Operation On-Chip Peripherals
positions that data master effectively exchanged with data peripheral slave. some cases, loop incomplete, data transferred only from peripheral from peripheral MCU. system typically consists master more slave peripherals. Other configurations such MCUs multiple master systems possible less common. system includes options select shift rate, master slave mode, clock polarity, phase allow compatibility with most synchronous serial peripheral devices from many manufacturers.
2.8.3 16-Bit Timer System MC68HC705C8 includes 16-bit timer system used measure time produce signals specific period frequency. This system based free-running 16-bit counter, 16-bit outputcompare register, 16-bit input-capture register. controls timing output signals through outputcompare mechanism. schedule output change occur specific time specific count free-running counter), 16-bit value corresponding desired time written output-compare register. When free-running counter matches value outputcompare register, planned output change occurs. detects time event measures period input signal with input-capture mechanism. select either positive negative edges detected trigger inputcapture mechanism. When selected edge occurs, current value free-running counter (which corresponds time edge occurred), captured (transferred input-capture register. later read value input-capture register determine exact time when edge occurred.
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2.8.4 Memory Peripherals Memory systems also form peripheral. uses different types memory were discussed earlier, logic required support these memories discussed. memories very straightforward require support logic other than address-select logic distinguish location from another. EPROM (erasable programmable ROM) EEPROM (electrically erasable programmable ROM) memories require support logic programming (and erasure case EEPROM). peripheral support logic MC68HC705C8 like having PROM programmer built into MCU. control register includes control bits select between programming normal modes enable highvoltage programming supply.
2.8.5 Other On-Chip Peripherals There many other peripherals available MCUs (see other members M68HC05 Family MCUs). These other peripherals include analog-to-digital (A/D) converters, liquid crystal display drivers (LCD), vacuum fluorescent display drivers (VFD).
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Applications Guide M68HC05
Section MC68HC705C8 Functional Data
Contents
Introduction
Description. 3.3.1 Hardware Features. 3.3.2 Software Features 3.3.3 General Description Pins Connections. 3.4.1 Functions 3.4.1.1 3.4.1.2 3.4.1.3 (Maskable Interrupt Request) 3.4.1.4 RESET 3.4.1.5 TCAP 3.4.1.6 TCMP 3.4.1.7 OSC1 OSC2 3.4.1.8 PA7-PA0 3.4.1.9 PB7-PB0 3.4.1.10 PC7-PC0 3.4.1.11 PD5-PD0 3.4.2 Typical Basic Connections On-Chip Memory 3.5.1 Memory Types 3.5.2 Memory Central Processor Unit 3.6.1 Registers 3.6.1.1 Accumulator 3.6.1.2 Index Register 3.6.1.3 Condition Code Register 3.6.1.4 Program Counter 3.6.1.5 Stack Pointer
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MC68HC705C8 Functional Data
3.6.2 3.6.3 3.6.4 3.6.4.1 3.6.4.2 3.6.4.3 Arithmetic/Logic Unit (ALU) Control Resets Power-On Reset Computer Operating Properly (COP) Watchdog Timer Reset Clock Monitor Reset.
Addressing Modes 3.7.1 Inherent Addressing Mode 3.7.2 Immediate Addressing Mode .103 3.7.3 Extended Addressing Mode 3.7.4 Direct Addressing Mode 3.7.5 Indexed Addressing Modes 3.7.5.1 Indexed, Offset 3.7.5.2 Indexed, 8-Bit Offset 3.7.5.3 Indexed, 16-Bit Offset 3.7.6 Relative Addressing Mode 3.7.7 Test Branch Instructions 3.7.8 Instructions Organized Type Instruction Summary Interrupts. 3.9.1 Software Interrupt (SWI). 3.9.2 External Interrupt .131 3.9.3 Timer Interrupt 3.9.4 Serial Communications Interface (SCI) Interrupt 3.9.5 Serial Peripheral Interface (SPI Interrupt .132 3.10 Microcontroller Input/Output 3.10.1 Parallel .133 3.10.2 Serial 3.11 Serial Communications Interface (SCI) 3.11.1 Transmitter 3.11.2 Receiver 3.11.3 Registers 3.11.3.1 Baud Rate Register (BAUD) 3.11.3.2 Serial Communications Control Register (SCCR1) .144
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MC68HC705C8 Functional Data Contents
3.11.3.3 3.11.3.4 3.11.3.5 3.11.4 3.11.5 3.11.6 3.11.6.1 3.11.6.2 3.11.6.3 3.11.7
Serial Communications Control Register (SCCR2) .144 Serial Communications Status Register (SCSR) .145 Serial Communications Data Register (SCDAT) Data Formats Hardware Procedures Software Procedures Initialization Procedure. Normal Transmit Operation Normal Receive Operation. .149 Application Example
3.12 Synchronous Serial Peripheral Interface (SPI) 3.12.1 Data Movement 3.12.2 Functional Description 3.12.3 Descriptions .156 3.12.3.1 Serial Data Pins (MISO, MOSI) 3.12.3.2 Serial Clock (SCK) 3.12.3.3 Slave Select (SS) 3.12.4 Registers 3.12.4.1 Serial Peripheral Control Register (SPCR) 3.12.4.2 Serial Peripheral Status Register (SPSR) 3.12.4.3 Serial Peripheral Data Register (SPDR) .161 3.13 Application Example 3.14 Programmable Timer 3.14.1 Functional Description 3.14.2 Timer Counter Alternate Counter Registers 3.14.3 Input-Capture Concept .169 3.14.4 Input-Capture Operation. 3.14.5 Output-Compare Concept 3.14.6 Output-Compare Operation 3.14.7 Timer Control Register (TCR) 3.14.8 Timer Status Register (TSR) .175 3.14.9 Timer Application Example. 3.15 STOP/WAIT Instruction Effects .177 3.15.1 Power-Consumption Modes 3.15.2 Effects On-Chip Peripherals
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MC68HC705C8 Functional Data
3.15.2.1 3.15.2.2 3.15.2.3 3.15.2.4 Timer Action During Stop Mode .180 Action During Stop Mode Action During Stop Mode Wait Mode Effects
3.16 OTPROM/EPROM Programming 3.16.1 Erasing 3.16.2 Programming 3.16.3 Program Register 3.16.4 Option Register
Introduction
MC68HC705C8 microcontroller (MCU) member M68HC05 Family low-cost, single-chip microcontrollers. HCMOS technology used MC68HC705C8 combines smaller size higher speeds with power high noise immunity CMOS. additional advantage CMOS that circuitry fully static. CMOS microcontrollers operated clock rate less than guaranteed maximum. This feature used conserve power since power consumption increases with higher clock frequencies. Static operation also advantageous during product development. software-controlled power-saving modes, WAIT STOP, available conserve additional power. These modes make MC68HC705C8 especially attractive automotive battery-driven applications.
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MC68HC705C8 Functional Data Description
Description
hardware software highlights MC68HC705C8 shown following subsections.
3.3.1 Hardware Features HCMOS technology 8-bit architecture Power-saving stop, wait, data retention modes bidirectional lines input-only lines timer pins internal operating frequency, volts; MHz, volts Internal 16-bit timer Serial communications interface (SCI) system Serial peripheral interface (SPI) system Ultraviolet (UV) light EPROM one-time programmable (OTPROM) Selectable memory configurations Computer operating properly (COP) watchdog system Clock monitor On-chip bootstrap firmware programming Software-programmable external interrupt sensitivity External pin, timer, SCI, interrupts Master reset power-on reset Single 3-to 6-volt supply (2-volt data retention mode) On-chip oscillator 40-pin dual-in-line package 44-lead PLCC (plastic leaded chip carrier) package
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MC68HC705C8 Functional Data
3.3.2 Software Features Upward software compatible with M146805 CMOS family Efficient instruction Versatile interrupt handling True manipulation Addressing modes with indexed addressing tables Memory-mapped power-saving standby modes
3.3.3 General Description Figure shows MC68HC705C8 block diagram. central processor unit (CPU) contains 8-bit arithmetic logic unit, accumulator, index register, condition code register, stack pointer, program counter, control logic. Major peripheral functions provided on-chip. On-chip memory systems include bootstrap read-only memory (ROM), programmable (EPROM OTPROM), random-access memory (RAM). On-chip devices include asynchronous serial communications interface (SCI), separate serial peripheral interface (SPI), 16-bit programmable timer system. Self-monitoring circuitry included on-chip protect against system errors. computer operating properly (COP) watchdog system protects against software failures. clock monitor system generates system reset clock lost runs slow. illegal opcode detection circuit provides non-maskable interrupt illegal opcode detected.
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MC68HC705C8 Functional Data Description
DATA DIRECTION
EPROM PROGRAMMING CONTROL
PROGRAM REGISTER
EPROM/OTPROM 7744 BYTES (144 BYTES CONFIGURABLE)
DATA DIRECTION DATA DIRECTION
OPTION REGISTER
BYTES BYTES)
BOOT BYTES
RESET
CONTROL
ARITHMETIC LOGIC UNIT (ALU) M68HC05
REGISTERS
ACCUMULATOR INDEX REGISTER
STACK POINTER PROGRAM COUNTER OSC1 OSCILLATOR OSC2 DIVIDE CONDITION CODES MOSI MISO PORT
PORT
PORT
PORT
WATCHDOG CLOCK MONITOR
BAUD RATE GENERATOR
TCMP POWER TIMER SYSTEM TCAP
Figure 3-1. MC68HC705C8 Microcontroller Block Diagram
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MC68HC705C8 Functional Data Pins Connections
following paragraphs discuss assignments, functions, basic connections. Because MC68HC705C8 CMOS device, unused input pins must terminated avoid oscillation, noise, added supply current. preferred method terminating pins that configured input output with individual pullup pulldown resistors each unused pin.
assignments shown Figure Figure 3-3.
RESET
OSC1 OSC2 TCAP TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI
Figure 3-2. 40-Pin Dual-In-Line Package Assignments
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MC68HC705C8 Functional Data Pins Connections
RESET
OSC1
OSC2
TCAP
TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO RD0/RDI
Figure 3-3. 44-Lead PLCC Package Assignments
3.4.1 Functions following subsections provide description functions. 3.4.1.1 Power supplied using these pins. power ground. operate from single 5-volt (nominal) power supply. 3.4.1.2 used when programming one-time programmable (OTPROM) EPROM. Programming voltage (14.75 Vdc) applied this when programming PROM. Normally, this connected VDD.
CAUTION:
connect (GND). will damage MCU.
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MC68HC705C8 Functional Data
3.4.1.3 (Maskable Interrupt Request) software programmable option which provides different choices interrupt triggering sensitivity. These options negative edge-sensitive triggering only, both negative edge-sensitive level-sensitive triggering. latter case, either negative edge level input will produce interrupt. completes current instruction before responds interrupt request. When goes low, small synchronization delay occurs, logic latched internally signify interrupt been requested. When completes current instruction, interrupt latch tested. interrupt latch contains logic interrupt mask bit) condition code register clear, then begins interrupt sequence. option selected include level-sensitive triggering, then input requires external resistor "wired-OR" operation. Interrupts more detail concerning interrupts. 3.4.1.4 RESET RESET active-low bidirectional control signal. input, RESET initializes known startup state. opendrain output, RESET indicates internal failure detected computer operating properly (COP) watchdog timer clock monitor circuitry. This RESET significantly different from RESET signal used other Motorola M68HC05 Family devices. Refer 3.6.4 Resets Interrupts before designing circuitry generate monitor RESET signal. 3.4.1.5 TCAP TCAP provides input input-capture feature on-chip programmable timer system. Refer input-capture register 3.14 Programmable Timer.
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MC68HC705C8 Functional Data Pins Connections
3.4.1.6 TCMP TCMP provides output output-compare feature on-chip timer system. Refer output-compare register 3.14 Programmable Timer. 3.4.1.7 OSC1 OSC2 MC68HC705C8 accept either crystal, ceramic resonator, external input control internal oscillator. internal processor clock derived dividing oscillator frequency (fosc) two. circuit shown Figure 3-4(a) recommended when using crystal. internal oscillator designed interface with AT-cut parallel resonant quartz crystal ceramic resonator MHz. crystal components should mounted close possible input pins minimize output distortion startup stabilization time. ceramic resonator used place crystal cost-sensitive applications. circuit Figure 3-4(a) recommended when using ceramic resonator crystal. manufacturer particular ceramic resonator being considered should consulted specific information. external clock applied OSC1 input with OSC2 connected, shown Figure 3-4(b). 3.4.1.8 PA7-PA0 These eight lines comprise port Each port software programmed input output. 3.4.1.9 PB7-PB0 These eight lines comprise port Each port software programmed input output.
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MC68HC705C8 Functional Data
STOP
MC68HC705C8 OSC1 XTAL OSC2
Crystal/Ceramic Resonator Oscillator Connections
STOP
MC68HC705C8 OSC1 OSC2 UNCONNECTED EXTERNAL CMOS CLOCK
External Clock Source Connections
Figure 3-4. Oscillator Connections
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MC68HC705C8 Functional Data Pins Connections
3.4.1.10 PC7-PC0 These eight lines comprise port Each port software programmed input output. 3.4.1.11 PD5-PD0 These seven lines comprise port During power-on reset, these seven pins configured inputs. When system enabled, four these lines, MISO/PD2, MOSI/PD3, SCK/PD4, SS/PD5, used system. When receiver enabled, PD0/RDI becomes receive data input SCI. When transmitter enabled, becomes transmit data output SCI.
3.4.2 Typical Basic Connections There basic connections that used starting point application minimize time required create prototype system. Figure schematic diagram simple MC68HC705C8 system. This circuit used basis MC68HC705C8 application. most cases, circuitry power supply oscillator used shown this diagram. unused inputs terminated appropriate manner.
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MC68HC705C8 Functional Data
MC68HC705C8 SYSTEM POWER (TYP)
OSC1 OSC2
PULLUP RESISTORS RECOMMENDED UNUSED INPUTS
MC34064 RESET
RESET PD0/RDI PD1/TDO
PD2/MISO PD3/MOSI PD4/SCK PD5/SS TCAP TCMP
Figure 3-5. Typical Basic Connections
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MC68HC705C8 Functional Data On-Chip Memory
On-Chip Memory
MC68HC705C8 memory includes bytes randomaccess memory (RAM), bytes read-only memory (ROM), 7600 7744 bytes programmable memory (EPROM OTPROM).
3.5.1 Memory Types means that word memory accessed without having through other words volatile form memory that memory content lost when power removed from chip. contents retained keeping least volts VDD. Power requirements this standby mode very small. very similar except, unlike RAM, possible change contents after manufactured. This type memory useful only storage information programs. special bootstrap mode allows programs downloaded through on-chip serial communications interface (SCI) into internal executed. bootloaded program used variety tasks such loading calibration values into internal EPROM performing diagnostics finished module. MC68HC705C8 on-chip called bootloader ROM. This controls loading process special bootstrap mode. Erasable programmable (EPROM) nonvolatile memory that programmed field user. Nonvolatile memories retain their contents even when power applied. Once been programmed, EPROM cannot written into, read from many times necessary. However, EPROM erased ultraviolet light reprogrammed. OTPROM same EPROM except programmed only once cannot erased.
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MC68HC705C8 Functional Data
3.5.2 Memory MC68HC705C8 contains four selectable memory configurations shown Figure 3-7. memory configurations accessed option register ($1FDF) RAM0 RAM1 bits. During reset, RAM0 RAM1 control bits forced RAM0 RAM1 states determine amount PROM, which selected follows:
RAM0
RAM1
Bytes
PROM Bytes 7744 7696 7648 7600
Central Processor Unit
MC68HC705C8 responsible executing software instructions their programmed sequence specific application. block diagram shown Figure 3-6.
CONTROL
ARITHMETIC LOGIC UNIT (ALU) M68HC05
REGISTERS
ACCUMULATOR INDEX REGISTER
STACK POINTER PROGRAM COUNTER CONDITION CODES
Figure 3-6. M68HC05 Block Diagram
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MC68HC705C8 Functional Data Central Processor Unit
$0000 $001F $0020 $002F
BYTES USER PROM BYTES RAM0=0 UNUSED BYTES BYTES RAM0=1
$004F $0050
BYTES $00BF $00C0
$00FF $0100
STACK BYTES USER PROM BYTES BYTES RAM1=1
$015F RAM1=0 $0160
USER PROM 7680 BYTES
PORT DATA REGISTER PORT DATA REGISTER PORT DATA REGISTER PORT FIXED INPUT REGISTER PORT DATA DIRECTION REGISTER PORT DATA DIRECTION REGISTER PORT DATA DIRECTION REGISTER UNUSED UNUSED UNUSED CONTROL REGISTER STATUS REGISTER DATA REGISTER BAUD RATE REGISTER CONTROL REGISTER CONTROL REGISTER STATUS REGISTER DATA REGISTER TIMER CONTROL REGISTER TIMER STATUS REGISTER INPUT-CAPTURE REGISTER (HIGH) INPUT-CAPTURE REGISTER (LOW) OUTPUT-COMPARE REGISTER (HIGH) OUTPUT-COMPARE REGISTER (LOW) TIMER COUNT REGISTER (HIGH) TIMER COUNT REGISTER (LOW) ALT. COUNT REGISTER (HIGH) ALT. COUNT REGISTER (LOW) EPROM PROGRAM REGISTER RESET REGISTER CONTROL REGISTER UNUSED
$1EFF $1F00 BOOT BYTES $1FDE $1FDF $1FE0 BOOT VECTORS BYTES $1FEF $1FF3 $1FF4 $1FFF UNUSED BYTES USER PROM VECTORS BYTES OPTION REGISTER VECTOR (HIGH) VECTOR (LOW) VECTOR (HIGH) VECTOR (LOW) TIMER VECTOR (HIGH) TIMER VECTOR (LOW) VECTOR (HIGH) VECTOR (LOW) VECTOR (HIGH) VECTOR (LOW) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE) $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF
*Refer 3.16.4 Option Register explanation software-selectable memory configurations.
Figure 3-7. MC68HC705C8 Memory
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MC68HC705C8 Functional Data
3.6.1 Registers contains five registers shown Figure 3-8. Registers memories inside microprocessor (not part memory map).
ACCUMULATOR INDEX REGISTER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER
CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM
Figure 3-8. Programming Model 3.6.1.1 Accumulator accumulator 8-bit general-purpose register used hold operands, results arithmetic calculations, data manipulations. also directly accessible nonarithmetic operations. accumulator used during execution program when contents some memory location loaded into accumulator. Also, store instruction causes contents accumulator stored some prescribed memory location.
ACCUMULATOR
Figure 3-9. Accumulator
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MC68HC705C8 Functional Data Central Processor Unit
3.6.1.2 Index Register index register used indexed modes addressing used auxiliary accumulator. This 8-bit register loaded either directly from memory, have contents stored memory, contents compared memory. indexed instructions, register provides 8-bit value that added instruction-provided value create effective address. instruction-provided value bytes long.
INDEX REGISTER
Figure 3-10. Index Register 3.6.1.3 Condition Code Register condition code register contains five status indicators that reflect results arithmetic other operations CPU. five flags half-carry (H), negative (N), zero (Z), overflow (V), carry borrow (C).
CONDITION CODE REGISTER
CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM
Figure 3-11. Condition Code Register (CCR) Half-Carry half-carry flag used binary-coded decimal (BCD) arithmetic operations affected addition instructions. when carry occurs between bits
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MC68HC705C8 Functional Data
Interrupt Mask interrupt mask disables maskable interrupt sources when set. Clearing this enables interrupts. When interrupt occurs, automatically after registers stacked before interrupt vector fetched. external interrupt occurs while set, interrupt latched processed after cleared; therefore, interrupts from lost because being set.
After interrupt been serviced, return from interrupt (RTI) instruction causes registers restored their previous values. Normally, would zero after executed. After reset, only cleared software instruction. Negative when result last arithmetic, logical, data manipulation negative (bit result logic one). other uses. assigning often-tested flag register memory location, test this simply loading accumulator with contents that location. Zero when result last arithmetic, logical, data manipulation zero. Carry/Borrow used indicate whether there carry from addition borrow result subtraction. Shift rotate instructions operate with through carry facilitate multiple word shift operations. This also affected during test branch instructions. following illustration example condition code bits affected arithmetic operations. useful after this operation because accumulator valid value before operation.
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MC68HC705C8 Functional Data Central Processor Unit
ASSUME INITIAL VALUES ACCUMULATOR CONDITION CODES:
ACCUMULATOR BEFORE ($FF)
CONDITION CODES
EXECUTE FOLLOWING INSTRUCTION: ---- ACCUMULATOR
ACCUMULATOR AFTER ($01)
CONDITION CODES
CONDITION CODES ACCUMULATOR REFLECT RESULTS INSTRUCTION:
because there carry from accumulator. change. Clear because result negative (bit accumulator Clear because result zero. because there carry accumulator.
3.6.1.4 Program Counter program counter 13-bit register that contains address next instruction instruction operand fetched processor.
PROGRAM COUNTER
Figure 3-12. Program Counter (PC) Normally, program counter advances memory location time instructions instruction operands fetched. Jump, branch, interrupt operations cause program counter loaded with memory address other than that next sequential location.
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MC68HC705C8 Functional Data
3.6.1.5 Stack Pointer stack pointer 13-bit register that contains address next free location stack. During reset reset stack pointer (RSP) instruction, stack pointer location $00FF.The stack pointer then decremented data pushed onto stack incremented data pulled from stack.
STACK POINTER
Figure 3-13. Stack Pointer (SP) When accessing memory, seven MSBs permanently 0000011. These seven bits appended bits produce address within range $00FF $00C0. Subroutines interrupts (decimal) locations. locations exceeded, stack pointer wraps around loses previously stored information. subroutine call occupies locations stack; interrupt uses five locations.
3.6.2 Arithmetic/Logic Unit (ALU) arithmetic logic unit (ALU) used perform arithmetic logical operations defined instruction set. various binary arithmetic operations circuits decode instruction instruction register desired function. Most binary arithmetic based addition algorithm, subtraction carried negative addition. Multiplication performed discrete instruction chain addition shift operations within under control control logic. multiply instruction (MUL) requires internal processor cycles complete this chain operat

M68HC05 Microcontrollers M68HC05AG/D Rev. 3/2002 WWW.MO

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