Kbit (32K 5.0V Asynchronous SRAM SUPPLY VOLTAGE: 5.5V bits SRAM w

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Kbit (32K 5.0V Asynchronous SRAM SUPPLY VOLTAGE: 5.5V bits SRAM w

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M68AF031A
Kbit (32K 5.0V Asynchronous SRAM
SUPPLY VOLTAGE: 5.5V bits SRAM with OUTPUT ENABLE EQUAL CYCLE ACCESS TIME: 70ns STANDBY CURRENT DATA RETENTION: TRI-STATE COMMON AUTOMATIC POWER DOWN PACKAGES SO28, PDIP28, TSOP28 Standard Reverse Pinout. TSOP28 Standard Available Lead-Free Version
Figure Packages
SO28 (MS)
PDIP28
TSOP28 13.4mm
TSOP28 (NS) 13.4 (Reverse)
November 2004
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M68AF031A
TABLE CONTENTS
FEATURES SUMMARY Figure Packages SUMMARY DESCRIPTION Figure Table Figure Figure Figure Figure Figure Logic Diagram Signal Names Connections. Connections TSOP Connections (Normal) TSOP Connections (Reverse) Block Diagram
MAXIMUM RATING. Table Absolute Maximum Ratings PARAMETERS. Table Figure Figure Table Table Operating Measurement Conditions Measurement Waveform Measurement Load Circuit. Capacitance. Characteristics (M68AF031A-55 M68AF031A-70)
OPERATION Table Operating Modes Read Mode Figure 10.Address Controlled, Read Mode Waveforms Figure 11.Chip Enable Output Enable Controlled, Read Mode Waveforms. Figure 12.Chip Enable Controlled, Standby Mode Waveforms Table Read Standby Mode Characteristics Write Mode Figure 13.Write Enable Controlled, Write Waveforms Figure 14.Chip Enable Controlled, Write Waveforms Table Write Mode Characteristics Figure 15.Low Data Retention Waveforms Table Data Retention Characteristics. PACKAGE MECHANICAL Figure 16.SO28 lead Plastic Small Outline, mils body width, Package Outline Table SO28 lead Plastic Small Outline, mils body width, Package Mechanical Data Figure 17.PDIP28 Plastic DIP, mils width, Package Outline Table PDIP28 Plastic DIP, n600 mils width, Package Mechanical Data Figure 18.TSOP28 lead Normal Pinout Plastic Small Outline, Package Outline Table TSOP28 lead Normal Pinout Plastic Small Outline, Package Mechanical Data
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M68AF031A
Figure 19.TSOP28 lead Reverse Pinout Plastic Small Outline, Package Outline Table TSOP28 lead Reverse Pinout Plastic Small Outline, Package Mechanical Data. PART NUMBERING Table Ordering Information Scheme REVISION HISTORY Table Document Revision History
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M68AF031A
SUMMARY DESCRIPTION
M68AF031A Kbit (262,144 bit) CMOS SRAM, organized 32,768 bytes. device features fully static operation requiring external clocks timing strobes, with equal address access cycle times. requires single 5.5V supply. This device automatic powerdown feature, reducing power consumption over when deselected. M68AF031A available SO28 (28-lead Small Outline), PDIP28 (28-pin Plastic Dual-InLine) TSOP28 (28-lead Thin Small Outline, Standard Reverse Pinout) packages. addition standard version, TSOP28 Standard package also available Lead-free version (standard Tape Reel packing), compliance with JEDEC J-STD-020B, ECOPACK 7191395 Specification, RoHS (Restriction Hazardous Substances) directive. also compliant with Lead-free soldering processes.
Figure Logic Diagram
Table Signal Names
A0-A14 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Supply Voltage Ground Connected Internally
DQ0-DQ7
A0-A14 M68AF031A
DQ0-DQ7
AI05920C
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M68AF031A
Figure Connections Figure TSOP Connections (Normal)
M68AF031A
AI05921C
M68AF031A (Normal)
AI07200C
Figure Connections
Figure TSOP Connections (Reverse)
M68AF031A
M68AF031A (Reverse)
AI07201C
AI05922C
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M68AF031A
Figure Block Diagram
DECODER MEMORY ARRAY
CIRCUITS COLUMN DECODER
AI05919
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M68AF031A
MAXIMUM RATING
Stressing device above rating listed Absolute Maximum Ratings table cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification imTable Absolute Maximum Ratings
Symbol TLEAD TSTG Output Current Power Dissipation Ambient Operating Temperature Lead Temperature during Soldering Storage Temperature Supply Voltage Input Output Voltage Parameter Value
plied. Exposure Absolute Maximum Rating conditions periods greater than periods affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents.
Unit
-0.5 -0.5 +0.5
Note: output time, exceed second duration. maximum operating 6.0V only. Compliant with JEDEC J-STD-020B (for small body, Sn-Pb assembly), ECOPACK® 7191395 specification, European directive Restrictions Hazardous Substances (RoHS) 2002/95/EU.
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M68AF031A
PARAMETERS
This section summarizes operating measurement conditions, well characteristics device. parameters following Characteristic tables derived from tests performed under Measurement Conditions listed relevant tables. Designers should check that operating conditions their projects match measurement conditions when using quoted parameters.
Table Operating Measurement Conditions
Parameter Supply Voltage Range Ambient Operating Temperature Range Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Output Timing Ref. Voltages Input Rise Fall Times Input Pulse Voltages Output Transition Timing Ref. Voltages 85°C 100pF 3.0k 3.1k VCC/2 1ns/V 0.3VCC; 0.7VCC M68AF031A 5.5V 70°C
Figure Measurement Waveform
Figure Measurement Load Circuit
Timing Reference Voltage VCC/2 DEVICE UNDER TEST Output Timing Reference Voltage 0.7VCC 0.3VCC
AI05831
includes probe capacitance
AI05932
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M68AF031A
Table Capacitance
Symbol COUT Parameter(1,2) Input Capacitance pins (except Output Capacitance Test Condition VOUT Unit
Note: Sampled only, 100% tested. 25°C, MHz, 5.0V.
Table Characteristics (M68AF031A-55 M68AF031A-70)
Symbol Parameter Test Condition 5.5V, 1/tAVAV, IOUT 5.5V, 1MHz, IOUT 5.5V, -0.2V VOUT Range Range -0.3 -1.0mA 2.1mA Unit
ICC1 (1,2) Operating Supply Current ICC2
Note:
Operating Supply Current
Standby Supply Current CMOS Input Leakage Current Output Leakage Current Input High Voltage Input Voltage Output High Voltage Output Voltage
Average current, cycling tAVAV minimum. VIL, VIH. 0.2V, 0.2V -0.2V. Output disabled.
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M68AF031A
OPERATION
M68AF031A Chip Enable power down feature which invokes automatic standby mode whenever Chip Enable de-asserted High). Output Enable signal provides high speed tri-state control, allowing fast read/write cyTable Operating Modes
Operation Deselected Read Write Output Disabled
Note: VIL.
cles achieved with common data bus. Operational modes determined device control inputs summarized Operating Modes table (see Table Operating Modes).
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Read Mode M68AF031A Read mode whenever Write Enable High with Output Enable Low, Chip Enable asserted. This provides access data 262,144 locations static memory array, specified address inputs. Valid data will available eight output pins within tAVQV after last stable
address, providing Low. Chip Enable Output Enable access times met, data access will measured from limiting parameter (tELQV tGLQV) rather than address. Data indeterminate tELQX tGLQX data lines will always valid tAVQV.
Figure Address Controlled, Read Mode Waveforms
tAVAV A0-A14 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI05939
Note: Low, Low, High.
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M68AF031A
Figure Chip Enable Output Enable Controlled, Read Mode Waveforms.
tAVAV A0-A14 tAVQV tELQV tELQX tGLQV tGLQX DQ0-DQ7 VALID
AI05940
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable High.
Figure Chip Enable Controlled, Standby Mode Waveforms
AI05956
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M68AF031A
Table Read Standby Mode Characteristics
M68AF031A Symbol Parameter Min. tAVAV tAVQV tAXQX tEHQZ (2,3) tELQV tELQX tGHQZ (2,3) tGLQV tGLQX Read Cycle Time Address Valid Output Valid Data hold from address change Chip Enable High Output Hi-Z Chip Enable Output Valid Chip Enable Output Lo-Z Output Enable High Output Hi-Z Output Enable Output Valid Output Enable Output Transition Chip Enable High Power Down Chip Enable Power Max. Min. Max. Unit
Note: Test conditions assume transition timing reference level 0.3VCC 0.7VCC. given temperature voltage condition, tGHQZ less than tGLQX tEHQZ less than tELQX given device. These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels. Tested initially after design process changes that affect these parameters.
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M68AF031A
Write Mode M68AF031A Write mode whenever Low. Either Chip Enable input Write Enable input must deasserted during Address transitions subsequent write cycles. When Low, write cycle begins (E)'s falling edge. Therefore, address setup time referenced Write Enable Chip Enable tAVWL tAVEL respectively, determined latter occurring edge.
Write cycle terminated earlier rising edge Output enabled Low, Low), then will return outputs high impedance within tWLQZ falling edge. Care must taken avoid contention this type operation. Data input must valid tDVWH before rising edge Write Enable, tDVEH before rising edge whichever occurs first, remain valid tWHDX tEHDX respectively.
Figure Write Enable Controlled, Write Waveforms
tAVAV A0-A14 VALID tAVWH tELWH tWLWH tAVWL tWLQZ tWHDX DQ0-DQ7 DATA DATA INPUT tDVWH
AI05941
tWHAX
tWHQX
DATA
Note: During this period DQ0-DQ7 output state input signals should applied.
Figure Chip Enable Controlled, Write Waveforms
tAVAV A0-A14 VALID tAVEH tAVEL tWLEH tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI05942
tELEH
tEHAX
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M68AF031A
Table Write Mode Characteristics
M68AF031A Symbol Parameter Min. tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tELWH tWHAX tWHDX tWHQX tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid Chip Enable High Address valid Chip Enable Address Valid Write Enable High Address Valid Write Enable Input Valid Chip Enable High Input Valid Write Enable High Chip Enable High Address Transition Chip enable High Input Transition Chip Enable Chip Enable High Chip Enable Write Enable High Write Enable High Address Transition Write Enable High Input Transition Write Enable High Output Transition Write Enable Chip Enable High Write Enable Output Hi-Z Write Enable Write Enable High Max. Min. Max. Unit
Note: given temperature voltage condition, tWLQZ less than tWHQX given device. These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels.
Figure Data Retention Waveforms
DATA RETENTION MODE 5.5V 4.5V
2.0V tCDR 0.2V
AI05925
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M68AF031A
Table Data Retention Characteristics
Symbol ICCDR Parameter Supply Current (Data Retention) Test Condition 2.0V, -0.2V, tAVAV -0.2V, Unit
Chip Deselected Data Retention tCDR (1,2) Time Operation Recovery Time Supply Voltage (Data Retention)
Note: other Inputs -0.2V 0.2V. Tested initially after design process changes that affect these parameters. tAVAV Read cycle time. input exceed +0.2V.
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M68AF031A
PACKAGE MECHANICAL
Figure SO28 lead Plastic Small Outline, mils body width, Package Outline
SO-E
Note: Drawing scale.
Table SO28 lead Plastic Small Outline, mils body width, Package Mechanical Data
millimeters Symbol 1.27 7.39 11.68 0.79 2.38 0.05 2.28 0.35 0.20 18.03 2.79 0.35 2.43 0.50 0.30 18.41 0.10 7.62 12.19 1.27 0.050 0.291 0.460 0.031 0.094 0.002 0.090 0.014 0.008 0.710 0.110 0.014 0.096 0.020 0.012 0.725 0.004 0.300 0.480 0.050 inches
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M68AF031A
Figure PDIP28 Plastic DIP, mils width, Package Outline
PDIP
Note: Drawing scale.
Table PDIP28 Plastic DIP, n600 mils width, Package Mechanical Data
millimeters Symbol 2.54 14.99 33.02 15.24 1.52 0.38 3.56 0.38 0.20 36.83 13.59 15.24 3.18 1.78 5.08 4.06 0.51 0.30 37.34 13.84 17.78 3.43 2.08 0.100 0.590 1.300 0.600 0.060 0.015 0.140 0.015 0.008 1.450 0.535 0.600 0.125 0.070 0.200 0.160 0.020 0.012 1.470 0.545 0.700 0.135 0.082 inches
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M68AF031A
Figure TSOP28 lead Normal Pinout Plastic Small Outline, Package Outline
TSOP-C
Note: Drawing scale.
Table TSOP28 lead Normal Pinout Plastic Small Outline, Package Mechanical Data
millimeters Symbol 13.400 11.800 8.000 0.550 0.300 0.220 0.100 0.210 0.100 0.700 0.5276 0.4646 0.3150 0.0217 0.0118 0.050 0.910 1.200 0.150 1.050 0.0087 0.0039 0.0083 0.0039 0.0276 0.0020 0.0358 0.0472 0.0059 0.0413 inches
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M68AF031A
Figure TSOP28 lead Reverse Pinout Plastic Small Outline, Package Outline
TSOP-H
Note: Drawing scale.
Table TSOP28 lead Reverse Pinout Plastic Small Outline, Package Mechanical Data
millimeters Symbol 13.400 11.800 8.000 0.550 0.300 0.220 0.100 0.210 0.100 0.700 0.5276 0.4646 0.3150 0.0217 0.0118 0.050 0.910 1.200 0.150 1.050 0.0087 0.0039 0.0083 0.0039 0.0276 0.0020 0.0358 0.0472 0.0059 0.0413 inches
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M68AF031A
PART NUMBERING
Table Ordering Information Scheme
Example: Device Type Mode Asynchronous Operating Voltage 5.5V Array Organization Kbit (32K Option Chip Enable Option L-Die M-Die Speed Class 55ns 70ns Package SO28 PDIP28 TSOP28 8x13.4mm (Standard Pinout) TSOP28 8x13.4mm (Reverse Pinout) Operative Temperature 70°C Shipping Tape Reel Packing Lead-free RoHS Package, Standard Packing Lead-free RoHS Package, Tape Reel Packing M68AF031
list available options (Speed, Package, etc.) further information aspect this device, please contact STMicroelectronics Sales Office nearest you.
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M68AF031A
REVISION HISTORY
Table Document Revision History
Date January 2002 07-Feb-2002 08-Feb-2002 06-Mar-2002 19-Apr-2002 Version First Issue clarified TSOP28 Package removed Measurement Load Circuit changed (Figure Operating Measurement Conditions clarified (Table Document status changed Data Sheet Absolute Maximum current value added (Table Operating Measurement Conditions clarified (Table Absolute Maximum Ratings Table clarified (Table Operating Measurement Conditions Table clarified (Table Characteristics Table clarified (Table Write Mode Characteristics Table clarified (Table Data Retention Waveforms clarified (Figure Data Retention Characteristics Table clarified Table Characteristics Table clarified (Table Data Retention Characteristics Table clarified (Table TSOP28 8x13.4mm Standard Reverse pinout added (Figure Table Revision numbering modified: minor revision will indicated incrementing digit after dot, major revision, incrementing digit before (revision version equals 8.0). part number added. Datasheet number simplified. 55ns speed-class added Package outline package mechanical data added TSOP28 Reverse package. TSOP28 Standard Lead-free version added FEATURES SUMMARY, SUMMARY DESCRIPTION. TLEAD parameter added Table Absolute Maximum Ratings. Standard Lead-free option added Table 14., Ordering Information Scheme. TSOP28 Lead-free Tape Reel version added FEATURES SUMMARY, SUMMARY DESCRIPTION. Lead-Free Tape Reel option added Table 14., Ordering Information Scheme. Revision Details
26-Apr-2002
20-May-2002 29-May-2002
02-Oct-2002
09-Oct-2002 23-Apr-2003 27-May-2004 05-Nov-2004
10.0
15-Nov-2004
11.0
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M68AF031A
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners 2004 STMicroelectronics rights reserved STMicroelectronics group companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States America www.st.com
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Kbit (32K 5.0V Asynchronous SRAM SUPPLY VOLTAGE: 5.5V bits SRAM w

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