Semiconductor MSM7662 Semiconductor NTSC/PAL Digital Video Decode

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Semiconductor MSM7662 Semiconductor NTSC/PAL Digital Video Decode

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E2F0020-18-X2
Semiconductor MSM7662
Semiconductor NTSC/PAL Digital Video Decoder
This version: Oct. 1998 MSM7662
GENERAL DESCRIPTION
MSM7662 device that decodes NTSC analog video signals into YCbCr digital data based ITU-RBT.601. device built-in channels converters accept composite video video signals input video signals. Composite video signals converted YCbCr digital data 2-dimensional separation circuit with adaptive filter. Analog video signals sampled clock pixel frequency twice pixel frequency. decimation filter built-in sampling twice pixel frequency. Input signals synchronized internally high-speed locking color burst possible. Because FIFO buffer built into output format circuit, jitter-free output obtained even non-standard signals.
FEATURES feature found MSM7661)
NTSC/PAL composite video signal S-video signal composite, S-video analog inputs (switchable) Built-in clamp circuits video amps Built-in 8-bit converters channels; sampling frequency: MHz) selectable output interfaces ITU-RBT.656 (conditional), 8-bit (YCbCr), 8-bit 8-bit (CbCr) YCbCr YCbCr (limit) 24-bit 2-dimensional separation using adaptive comb filter (this filter bypassed S-video signal input) NTSC format: lines lines, format: lines virtual lines) Selectable input signal synchronization synchronization modes: FIFO-1, FIFO-2, FM-1, FM-2 (FIFO-1 normally selected) (FIFO-1 FIFO-2 internal FIFO, FM-1 FM-2 external field memory) Compatible pixel frequencies 13.5 (ITU-RBT.601), 12.27 (NTSC Square Pixel) 14.31818 (NTSC 4fsc), 14.45 (PAL Square Pixel) Built-in AGC/ACC circuits, compatible with wide range input levels Input level range: +3.5 Switchable between AGC/MGC (fixed gain) ACC/MCC (fixed gain) Decimation filter built into input stage, allows easy configuration filter prior converter Automatic NTSC/PAL recognition (only ITU-RBT.601) Sleep mode Multiplex signal recognition (closed caption) During vertical blanking interval, data output 8-bit data. I2C-bus interface single power supply (I/O tolerance) Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7662TB) 1/47
Input analog signal
BLOCK DIAGRAM
Semiconductor
CLKX2O INS[2:0] GAINS[2:0] CLKXO
CLKX2 CLKSEL
PLLSEL
VSYNC_L HVALID
VVALID
STATUS1
STATUS3
HSYNC_L
ODD/EVEN
STATUS2
Synchronization Block VRT2 VIN6 VIN5 ADIN2 AMPOUT2 CLPOUT2 VRB2 AGC&
Decimation Filter
M[7:0]
Prologue Block
Luminance Block (AGC LPF) Epilogue Block ITU-656 bits (YCbCr) Y[7:0] (G[7:0])
Dim. separate)
Decimation Filter
VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 VIN4 VIN3 VIN2 VIN1 VRT1
Line Memory Kbyte)
Chrominance Block (ACC LPF) bits bits (CbCr)
AGC&
Output Formatter I2C-bus Control Logic Test Control Logic
C[7:0] (R[7:0])
Matrix
bits bits bits
B[7:0]
MSM7662
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MODE[3:0]
RESET_L
SLEEP
SCAN
TEST[2:0]
Semiconductor
GAINS[0] GAINS[1] GAINS[2] DAGND INS[0] INS[1] INS[2] DGND DVDD
DAVDD VRT2 VIN6 VIN5 ADDD AGND ADIN2 AMPOUT2 CLPOUT2 VRB2 AGND AGND VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 AGND AVDD VIN4 VIN3 VIN2 VIN1 VRT1 DAVDD
MSM7662
CONFIGURATION (TOP VIEW)
STATUS1
STATUS2
STATUS3
CLKX2O
CLKXO
HSYNC_L VSYNC_L VVALID HVALID ODD/EVEN C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] DGND DVDD Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] DVDD DGND
CLKX2 B[4]
DAGND
MODE[0]
MODE[1]
MODE[2]
MODE[3]
SCAN
TEST[2]
TEST[1]
TEST[0]
SLEEP
RESET_L
DVDD
DGND
PLLSEL
CLKSEL
B[7]
B[6]
B[5]
B[3]
B[2]
DGND
DVDD
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
B[1]
100-Pin Plastic TQFP
B[0]
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Semiconductor
MSM7662
DESCRIPTIONS
Symbol DAVDD VRT2 VIN6 VIN5 AVDD AGND ADIN2 AMPOUT2 CLPOUT2 VRB2 AGND AGND VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 AGND AVDD VIN4 VIN3 VIN2 VIN1 VRT1 DAVDD DAGND Type Description Digital power supply converter converter reference voltage (high side) chroma signal Chroma signal input (leave open connect AGND when used) Chroma signal input (leave open connect AGND when used) Analog power supply Analog ground converter input chroma signal Chroma signal output Chroma signal clamp voltage output converter reference voltage (low side) chroma signal Analog ground Analog ground converter reference voltage (low side) composite/luminance signal Composite/luminance signal clamp voltage output Composite/luminance signal output converter input composite/luminance signal Luminance signal clamp voltate input Analog ground Analog power supply Composite/luminance signal input (leave open connect AGND when used) Composite/luminance signal input (leave open connect AGND when used) Composite/luminance signal input (leave open connect AGND when used) Composite/luminance signal input (leave open connect AGND when used) converter reference voltage (high side) composite/luminance signal Digital power supply converter Digital ground converter Mode selection pins (pulled-down internal resistors) MODE[3:2] Output mode selection ITU-RBT.656 (with SAV, EAV, blank processing) ITU-RBT.656 SAV, EAV, blank processing) ITU-RBT.601 MODE[3:0] MODE[1] MODE[0] NTSC ITU-RBT.601 Square Pixel
ITU-R.601 signal input while registers automatic NSTC/PAL recognition, NTSC/PAL will automatically recognized regardless MODE1 setting.
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Semiconductor
MSM7662
DESCRIPTIONS (continued)
Symbol SCAN TEST[2] TEST[1] TEST[0] SLEEP RESET_L DVDD DGND PLLSEL CLKSEL B[7:0] DGND DVDD Y[7:0] DVDD DGND C[7:0] ODD/EVEN HVALID VVALID VSYNC_L HSYNC_L CLKXO CLKX2O DGND DVDD CLKX2 Type Description Test input. Normally fixed (pulled down internal resistor). Test input. Normally fixed (pulled down internal resistor). Test input. Normally fixed (pulled down internal resistor). Test input. Normally fixed (pulled down internal resistor). normal operation, sleep operation Reset input (active "L") Digital power supply Digital ground I2C-bus clock input I2C-bus data Internal/external sync switching (pulled down internal resistor). Internal sync mode, External sync mode; external Clock select input (pulled down internal resistor). "L": double-speed MHz, "H": normal clock 13.5 data output during mode B[7]: MSB, B[0]: Digital ground Digital power supply ITU-RBT.656 data output during ITU-RBT.656 output mode ITU-RBT.601 luminance data output during ITU-RBT.601 output mode data output during mode, Y[7]: MSB, Y[0]: Digital power supply Digital ground Chroma data output during ITU-RBT.601 output mode data output during mode, C[7]: MSB, C[0]: Field display output field odd, output Horizontal valid pixel timing output Vertical valid line timing output sync output sync output Pixel clock output System clock output Digital ground Digital power supply System clock input Default internal FIFO overflow detection (TV, mode switching guide) STATUS[3] non-detection, detection CSYNC output (selected register) When PLLSEL external sync mode selected, HSYNC output
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Semiconductor
MSM7662
DESCRIPTIONS (continued)
Symbol Type NTSC, HLOCK sync detection display output (selected register) non-detection, detection STATUS[1] M[7] M[6] M[5] M[4] M[3] M[2] interval multiplex signal detection output non-detection, detection Field memory control signal; output Field memory control signal; output Field memory control signal; RSTR output Field memory control signal; RSTW output Test output pin, normally output Slave address select "L": 1000001X "H": 1000011X internal pull-up pull-down resistor) setting either external internal register order select M[1] analog section gain value video signal input pin. "L": external setting "H": internal register setting internal pull-up pull-down resistor) M[0] DGND DVDD GAINS[2:0] INS[2:0] DAGND Test pin, normally fixed internal pull-up pull-down resistor) Digital ground Digital power supply Inputs gain switch setting during external setting mode (pulled down internal resistors) Inputs signal input switch setting during external setting (pulled down internal resistors) Digital ground converter Description Default NTSC-PAL recognition STATUS[2]
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Semiconductor
MSM7662
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Power Consumption Storage Temperature Symbol TSTG Condition 25°C Rating -0.3 +4.5 -0.3 +5.5 +150 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Power Supply Voltage Digital Level Input Voltage Digital Level Input Voltage Analog Video Signal Input Operating Temperature Symbol VIH1 VIH2 (*1) VAIN Condition 25°C 25°C SYNC white peak level Min. Typ. Max. Unit VP-P
CLKX2,
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Semiconductor
MSM7662
ELECTRICAL CHARACTERISTICS
Characteristics
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter Level Output Voltage Level Output Voltage Symbol Condition (*1) (*2) IOL= (*1) IOL= (*2) Input Leakage Current Output Leakage Current Output Voltage Output Current SDAVL SDAIO Rpull_down (*3) Min. -250 Typ. Max. Unit
HSYNC_L, VSYNC_L, SYSSEL, C[7:0], B[7:0], ODD, VVALID, HVALID, CLKXO, Y[7:0], CLKX2O MODE[3:0], TEST1, PLLSEL, CLKSEL, M[3:0], ATEST[3:1], INS[3:1]
Characteristics (Analog Unit)
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter AMPOUT Output Voltage CLPOUT Output Voltage Output Voltage Output Voltage ADIN Input Current Symbol VOAMP VOCLP VIADIN VIVIN IIVIN Condition Capacitive coupling Min. 2.05 0.15 Typ. Max. Unit VP-P
Characteristics
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter Power Supply Current (Operating) Symbol Condition CLKX2 Power Supply Current (Operating) Power Supply Current (Sleep) CLKX2 Min. Typ. Max. Unit
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Semiconductor Characteristics (Single Speed Mode)
MSM7662
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter Symbol Condition ITU-RS601 CLKX2 Cycle Time tCLKX1 NTSC 4fsc NTSC Square Pixel Square Pixel CLKX1 Duty tD_D1 CLKSEL Min. Typ. Max. 74.07 69.84 81.5 67.8 Unit
Output Data Delay Time Output Data Delay Time Output Clock Delay Time (CLKX2-CLKXO) Output Clock Delay Time (CLKX2-CLKX2O) Clock Cycle Time Clock Duty Level Cycle Output load:
tOD11 tOD12 tCXD11 tCXD12 tC_SC1 tD_SC1 tL_SC1
CLKSEL CLKSEL Rpull_up Rpull_up
Characteristics (Double Speed Mode)
70°C, (DVDD, ADVDD, AVDD) ±0.3 Parameter Symbol Condition ITU-RS601 CLKX2 Cycle Time tCLKX2 NTSC 4fsc NTSC Square Pixel Square Pixel CLKX2 Duty tD_D2 Min. Typ. Max. 37.05 34.9 40.75 33.9 Unit
Output Data Delay Time Output Data Delay Time Output Clock Delay Time (CLKX2-CLKXO) Output Clock Delay Time (CLKX2-CLKX2O) Clock Cycle Time Clock Duty Level Cycle Output load:
tOD21 tOD22 tCXD21 tCXD22 tC_SCL tD_SCL tL_SCL
CLKSEL CLKSEL CLKSEL CLKSEL Rpull_up Rpull_up
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Semiconductor
MSM7662
INPUT OUTPUT TIMING
Clock Output Timing
CLKSEL:H tCLKX1 CLKSEL:L tCLKX2
CLKX2 tCXD12 CLKX2O tCXD11 CLKXO tOD11 Y[7:0], C[7:0] HVALID, VVALID, ODD/EVEN, STATUS[3:1], M[7:4], B[7:0] HSYNC_L, VSYNC_L tOD12 tOD22 tOD21 tCXD21 tCXD22
I2C-bus Interface Input/Output Timing basic input/output timing I2C-bus indicated below.
Start condition
tC_SCL
Stop condition
Data line stable: data valid
Change data allowed
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Semiconductor
MSM7662
FUNCTIONAL DESCRIPTION
Analog Unit Analog input select: Compatible with composite video signals S-video signals. Input selection switched register control I2C-bus external pins. (See below chart combinations.) Clamp function: analog clamp digital pulse clamp used. Analog clamp (HSY Analog clamp clamp (digital clamp) clamp (digital clamp) Only clamp pedestal clamp. amp: function operates depending upon input level. Manual gain setting also possible. This function operates stages, analog unit digital unit. Digital decoded data output conformance with ITU-RBT.601. converter: internal 8-bit converters sample twice pixel frequency. (Sampling pixel frequency possible changing register setting.) List Analog Input Conditions
Input Signal Composite Input* Composite Input Composite Input Composite Input Composite Input S-video Input S-video Input inputs @Control INS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] Luminance Luminance (Sleep) VIN1 Composite Composite Composite Composite Composite Chroma Chroma VIN2 Input VIN3 VIN4 VIN5 VIN6 Selection
Blank spaces: non-selectable register default setting after reset These settings valid during external mode setting. internal register mode, register contents will changed. Manual Gain Control (analog gain)
Gain Setting Pins GAINS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] Gain Value Typ. Value (multiplication factor) 1.35 1.75
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Semiconductor Decoder Unit Prologue Block
MSM7662
prologue block inputs data performs separation. Data input either pixel frequency (ITU-R: 13.5 MHz) twice pixel frequency (ITU-R: MHz). input twice pixel frequency, data processed after passing through decimator circuit convert pixel frequency. decimator circuit bypassed changing register setting, regardless whether data input normal pixel frequency twice pixel frequency. composite signal (CVBS) input, default setting performs separation using 2dimensional adaptive comb filter. following operating modes selected I2C-bus. Default settings indicated asterisk (*). default state selected reset. Video input mode selection Composite video input S-video input Video input mode selection NTSC/PAL auto-select* (only ITU-R.601) Dependent upon operating mode selected When ITU-R.601 selected, video input mode automatically depending upon number lines field. Operating mode selection NTSC ITU-R.601 13.5 MHz* NTSC Square Pixel 12.27 NTSC 4fsc 14.31818 ITU-R.601 13.5 Square Pixel 14.75 Decimator circuit pass/bypass selection Pass through decimator circuit* Bypass decimator circuit separation mode selection adaptive comb filter* non-adaptive comb filter comb filter (use trap filter) adaptive comb filter makes correlation between consecutive lines (only lines case signal). there correlation, separation performed comb filter according format correlation. non-adaptive comb filter performs separation removing luminance component based average preceding following lines (when there correlation between lines). When comb filter used, separation performed trap filter.
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Semiconductor S-video signal input, these separation circuits bypassed.
MSM7662
functions this block only operate when lines valid image information. During blanking interval, CVBS signals processed. Luminance Block luminance block removes synchronous signals from signals containing luminance components after separation. signals compensated then output luminance signals. modes gain control functions selected luminance signal output level: (Auto Gain Control) Pedestal Clamp. mode, luminance level amplification determined comparing SYNC depth with reference value. default 40IRE changed register setting. input sync chip clamp. Pedestal Clamp mode, signal output level clamped pedestal level input. Signal amplification black level changed from clamped position register settings. This block select follwing operating modes. Selection prefilter sharp filter usage use* These filters used enhance edges luminance component signals. Selection aperture bandpass filter coefficient Middle range* High range Coring range selection Off* ±4LBS ±5LBS ±7LBS Aperture weighting coefficient selection 0.25 0.75 Both coring aperture compensation processes perform contour compensation. Selection pixel position compensating circuit usage Use* loop filter time constant selection Slow coefficient value 1/1024n Medium 1/64n* Fast Fixed Fixed: manual gain setting possible
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Semiconductor
MSM7662
Parameter fine adjustment sync depth Parameter fine adjustment sync removal level black level adjusted. default setting outputs pedestal position black level (=16). Pedestal clamp selection pedestal clamp* pedestal clamp this time, does operate, operates) Chrominance Block This block processes chroma signals. following operating modes selected. Selection color bandpass filter usage use* loop filter time constant selection Slow coefficient value 1/1024m Medium 1/64m* Fast Fixed Fixed: manual gain setting possible reference level fine adjustment Parameter burst level fine adjustment Threshold level which chroma amplitude becomes valid selected based upon color burst ratio. 0.25* 0.125 Off: color killer function turned off. decoloration occurs while decoding still picture, setting threshold level "off" will reduce decoloration. Color killer mode selection Auto color killer mode* Forced color killer Parameter fine adjustment color subcarrier phase this block, chroma signals pass through bandpass filter unnecessary band. maintain constant chroma level, these signals then pass through compensating circuit demodulated. (The filter bypassed.) demodulated result does reach constant level, color killer signals generated gain. This functions auto color killer control circuit. demodulated results pass through low-pass filter output chrominance signals.
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Semiconductor Synchronization Block
MSM7662
This block processes sync signals. Synchronous signals generated chip output internal use. Various signals output from this block following operating modes selected. Adjustment SYNC threshold level (internal sync) control 2-1) Fine adjustment signal (start side) 2-2) Fine adjustment signal (stop side) signal enable selection High Level* Active Level signal provides sync-tip-clamp processing converter. Fine adjustment HSYNC_L signal HVALID control 5-1) Fine adjustment HVALID signal (start side) 5-2) Fine adjustment HVALID signal (stop side) VVALID control 6-1) Fine adjustment VVALID signal (start side) 6-2) Fine adjustment VVALID signal (stop side) Data signals transferred rising edge HVALID signal. FIFO Field Memory mode selection FIFO-1 mode*: Sets outputs standard value number pixels from internal FIFO. This mode also compatible degree) with non-standard signals. FIFO-2 mode: Sets outputs constant pixel number corresponding input interval number pixels from internal FIFO. FM-1 mode: This mode outputs decoded results according SYNC signal. Usage external field memory required manage number pixels absorb jitter. Memory control signals generated externally. FM-2 mode: This mode compatible with considerably distorted non-standard signals. Jitter absorbed using external field memory standard value pixel number. Field memory control signals output simultaneously from M[7:4]. Field memory control signals FM-1 mode uses external field memory instead internal FIFO, field memory control signals supplied from pins M[7:4].
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Semiconductor Epilogue Block
MSM7662
Epilogue Block outputs signal from Chrominance block signal from Luminance block format based signal obtained from control register setting. This block select following modes. Output mode selection 1-1) ITU-RBT.656 (SAV, EAV, blank processing) 1-2) 8-bit (YCbCr) output pixel clock) synchronization with HSYNC_L, VSYNC_L 1-3) 16-bit (8-bit Y/8-bit CbCr) (pixel clock) synchronization with HSYNC_L, VSYNC_L 1-4) 24-bit bits each) synchronization with HSYNC_L, VSYNC_L Enable Blue Back display when synchronization fails Selection YCbCr signal output format YCbCr YCbCr 4:1:1 chrominance signal component) outputs data output format described later. Selection 8-bit chroma signal output format Offset binary* complement Output enable selection High-impedance Output enable* Multiplex signal (VBI data) detection level adjustment levels detect multiplexed signals sent during vertical blanking period configured variable. binary values after input signals A-to converted employed levels detect multiplexed signals, levels eight steps with respect SYNC level. (See page page Various mode detection NTSC/PAL detection Multiplex signal detection HSYNC synchronization detection Iunternal FIFO overflow detection Output signal phase control phases each adjusted range pixels. Control Block This serial interface block based standard Phillips Corporation. This block only functions Slave-Receiver (write mode). Test Control Block This block used test chip. Normally this block used.
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Semiconductor Input Signal Level
MSM7662
figure below shows ideal range input signal, considered 8-bit straight binary value.
reserved
Iuminance
chrominance
NTSC:60 (PAL:63) sync
input black level input sync-tip level NTSC/PAL: CVBS[7:0] input range
above input conditions ideal. Because analog signals normally input different levels, exact settings described above difficult achieve. While maintaining ratio White Peak (100%)/SYNC 100IRE/40IRE (NTSC), input signal within converter's voltage range, digital output will output with Black Level White Peak (100%) 235.
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Semiconductor Output format
MSM7662
ITU-RBT.656 output, 8-bit (YCbCr) output, 16-bit (8-bit Y/8-bit CbCr) output have following formats. YCbCr 4:2:2 format 4:1:1 format shown below. output format changed register settings.
Output (MSB) (LSB) (MSB) (LSB) point point Pixel Byte Sequence Output (MSB) (LSB) (MSB) (LSB) point point YCbCr 4:1:1 format Pixel Byte Sequence
YCbCr 4:2:2 format
Relation between video mode pixel number (default settings when standard signal input)
Video Mode NTSC Pixel Type ITUR.601 Square pixel 4fsc ITUR.601 Square pixel Pixel Rate (MHz) 13.5 12.27 14.32818 13.5 14.75 Total Pixels Active Pixels FrontPorch Hsyc BackPorch HBLK Total
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Semiconductor
MSM7662
TIMING DESCRIPTION
Vertical Synchronizing Signal vertical synchronizing signal timing follows.
CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID
Vertical Synchronizing Signal
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Semiconductor
MSM7662
CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID
Vertical Synchronizing Signal
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Semiconductor Converter Support Signal
MSM7662
waveform signal, shown below, provides clamp timing converter when clamp (digital clamp) selected. start edges clamp pulse have variable range from sync chip pedestal position.
CVBS BURST
COLOR BURST
Converter Support Signal Output Timing ITU-R.656 output
clock periods normal (1/27 MHz) start active video timing reference code active video timing reference code Digital line {1716T (NTSC, 525), 1728T (PAL, 625)} Multiplexed video data Digital active line Video data block (1440T)
ITU-R BT.656 Output (Data line which video data presents) During blanking interval, data output with value. Note: Digital line 1716T (NTSC, 525) 1728T (PAL, 625) maintained next line. Digital active line 1440T line immediately after VVALID falls 10th 11th line after VSYNC_L rises will fluctuate pixel compensation. Especially when non-standard signal input, line immediately after VVALID falls will fluctuate largely instability input signal. phenomena such increase number lines standard signal decrease number lines nonstandard signal, possible guarantee correct functionality. 21/47
Digital line blanking 276T (NTSC, 525) 288T (PAL, 625)
Semiconductor Contents Both consist words. Their configuration shown below.
Word First Second Third Fourth (MSB) (LSB)
MSM7662
during field during field elsewhere during field blanking Protection
word relationship between Protection bits word shown below.
Function (MSB) Fixed
Usually, during blanking, however when data detected desired output, MRC[3] SAV, V-status Mode Register (MRC) "1".
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Semiconductor
MSM7662
CLKX2 HVALID Y[7:0]
8-bit (YCbCr: clock) Output
CLKX2 CLKO HVALID Y[7:0] C(7:0) Y(n-2) Y(n-1)
Cb(n-2) Cr(n-2)
16-bit 8-bit, CbCr: 8-bit) Output
CLKX2 CLKO HVALID R[7:0] G[7:0] B[7:0] R(n-2) G(n-2) B(n-2) R(n-1) G(n-1) B(n-1)
24-bit 8-bit, 8-bit, 8-bit) Output 23/47
Semiconductor
MSM7662
Timing when using external field memory Field memory timing FM-2 mode, using control signals from decoder Field memory: MSM518222, units used Four memory control signals supplied from decoder, M[4]: RSTW, M[5]: RSTR, M[6]: WE:, M[7]: NTSC Signal (13.5 MHz)
hsync_l vsync_l hvalid vvalid odd-even (7:0) (7:0) RSTW HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR (7:0) (7:0)
NTSC: Field
hsync_l vsync_l hvalid vvalid odd-even (7:0) (7:0) RSTW HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR (7:0) (7:0)
NTSC: EVEN Field 24/47
Semiconductor Signal (13.5 MHz)
MSM7662
hsync_l vsync_l hvalid vvalid odd-even (7:0) (7:0) RSTW HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR (7:0) (7:0)
PAL: Field
hsync_l vsync_l hvalid vvalid odd-even (7:0) (7:0) RSTW HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR (7:0) (7:0)
PAL: EVEN Field
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Semiconductor Horizontal Synchronization Signal horizontal synchronization signal timing shown below.
MSM7662
Y[7:0]
HVALID HSYNC_L pixels
Horizontal Timing Data Detection (when Composite signal input): STATUS1 Timing data detection results output from STATUS1 pin.
Detection level OMR[5:3] video
STATUS1 HVALID
HSYNC_L
Y[7:0]
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Semiconductor Data Detection (when S-Video signal input): STATUS1 Timing data detection results output from STATUS1 pin.
Detection level OMR[5:3] video
MSM7662
STATUS1 HVALID
HSYNC_L
Y[7:0]
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Semiconductor I2C-bus Interface Input Output Timing Basic input output timing I2C-bus interface shown below.
MSM7662
Start Condition
tC_SCL
Stop Condition
Data Line Stable: Data Valid Change Data Allowed
I2C-bus Basic Input/Output Timing
FORMAT
I2C-bus interface input format shown below.
Slave Address Symbol Slave Address Subaddress Data Start condition Slave address 1000001X, write signal ["0"] read signal ["1"] Acknowledge. Generated slave Subaddress byte Data write address designated subaddress. Stop condition Subaddress Data Data
Description
mentioned above, write operation executed from subaddress subaddress continuously. When write operation executed subaddresses discontinuously, Acknowledge Stop condition formats input repeatedly after Data following matters occurs, decoder will return (Acknowledge). slave address does match. non-existent subaddress specified. write attribute register does match (read ["1"]/write ["0"] control bit). input timing shown below.
Start Condition
Slave Address
Address
Data Stop Condition
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Semiconductor
MSM7662
OPERATING MODE SETTING
There types video mode settings. External mode: direct setting from dedicated pins Register setting mode: specification internal register settings These modes switched mode register MRA[0]. reset state (default) external mode. following registers external mode. MRA[3:1] Input signal mode *000: NTSC ITU-RBT.601 13.5 001: NTSC Square Pixel 12.27 010: NTSC 4fsc 14.31818 100: ITU-RBT.601 13.5 101: Square Pixel 14.75 ITU-R BT.656 (SAV, EAV, blank processing) *01: CbCr) HSYNC_L VSYNC_L used synchronization ITU-R BT.601 CbCr)
MRA[7:6]
Output mode
Note:
NTSC 4fsc cannot externally.
Setting Example NTSC, (ITU-RBT.601), Composite input, 8-bit (YCbCr) Output
name MODE[3] MODE[2] MODE[1] MODE[0] CLKSEL PLLSEL INS[2:0] GAINS[2:0] TEST[2:0] SCAN M[2] M[1] M[0] SLEEP high 1000001, high 1000011 Normally level normal operation sleep operation Normally level Condition 16-bit CbCr) NTSC Square Pixel pixel frequency ITU-RBT.601 Notes ITU-RBT.656 8-bit (YCbCr)
twice pixel frequency
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Semiconductor
MSM7662
INTERNAL REGISTERS
Register List
Register Function Mode Register (MRA) Mode Register (MRB) Mode Register (MRC) Horizontal Sync Trimmer (HSYT) Sync Threshold level adjust (STHR) Horizontal Sync Delay (HSDL) Horizontal Valid Trimmer (HVALT) Vertical Valid Trimmer (VVALT) Luminance Control (LUMC)
AGC/Pedestal Loop filter Control (AGCLF)
Write Sub/Read address Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Read
Data byte MRA7 MRB7 MRC7 HSYT7 STHR7 HSDL7 MRA6 MRB6 MRC6 HSYT6 STHR6 HSDL6 MRA5 MRB5 MRC5 HSYT5 STHR5 HSDL5 MRA4 MRB4 MRC4 HSYT4 STHR4 HSDL4 MRA3 MRB3 MRC3 HSYT3 STHR3 HSDL3 MRA2 MRB2 MRC2 HSYT2 STHR2 HSDL2 MRA1 MRB1 MRC1 HSYT1 STHR1 HSDL1 MRA0 MRB0 MRC0 HSYT0 STHR0 HSDL0
HVALID7 HVALID6 HVALID5 HVALID4 HVALID3 HVALID2 HVALID1 HVALID0 VVALID7 VVALID6 VVALID5 VVALID4 VVALID3 VVALID2 VVALID1 VVALID0 LUMC7 LUMC6 LUMC5 LUMC4 LUMC3 LUMC2 LUMC1 LUMC0 AGCLF7 AGCLF6 AGCLF5 AGCLF4 AGCLF3 AGCLF2 AGCLF1 AGCLF0 SSEPL7 SSEPL6 SSEPL5 SSEPL4 SSEPL3 SSEPL2 SSEPL1 SSEPL0 CHRC7 HUE7 OPCY7 OPCC7 OMR7 ADC17 ADC27 ADC37 ZLD7 CHRC6 HUE6 OPCY6 OPCC6 OMR6 ADC16 ADC26 ADC36 ZLD6 CHRC5 HUE5 OPCY5 OPCC5 OMR5 ADC15 ADC25 ADC35 ZLD5 CHRC4 HUE4 OPCY4 OPCC4 OMR4 ADC14 ADC24 ADC34 ZLD4 CHRC3 HUE3 OPCY3 OPCC3 OMR3 ADC13 ADC23 ADC33 ZLD3 CHRC2 HUE2 OPCY2 OPCC2 OMR2 ADC12 ADC22 ADC32 ZLD2 CHRC1 HUE1 OPCY1 OPCC1 OMR1 ADC11 ADC21 ADC31 ZLD1 CHRC0 HUE0 OPCY0 OPCC0 OMR0 ADC10 ADC20 ADC30 ZLD0 ACCLF7 ACCLF6 ACCLF5 ACCLF4 ACCLF3 ACCLF2 ACCLF1 ACCLF0
Sync separation level (SSEPL) Chrominance Control (CHRC) Loop filter Control (ACCLF) Control (HUE)
Output phase Control Data (OPCY) Output phase Control Data (OPCC)
Optional Mode Register (OMR)
register (ADC1) register (ADC2) register (ADC3) level detect register (ZLD) Stataus register (STATUS)
STATUS7 STATUS6 STATUS5 STATUS4 STATUS3 STATUS2 STATUS1 STATUS0
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Semiconductor
MSM7662
Register Parameters
Registers controlled from I2C-bus listed below. asterisk indicates that register setting value default value. Mode Register (MRA) MRA[7:6] Write only <address: $00> ITU-R BT.656 (SAV, EAV, blank processing) *01: bits (SAV, EAV, without blank processing) bits bits Offset binary Complement Composite video input S-video input *000: NTSC ITU-R BT.601 13.5 001: NTSC Square Pixel 12.27 010: NTSC 4fsc 14.31818 100: ITU-R BT.601 13.5 101: Square Pixel 14.75 External mode Register mode <address: $01> *00: FIFO-1 (use internal memory) FIFO-2 (use internal memory) FM-1 (use external memory, external control) FM-2 (use external memory, control signals supplied from M[7:4]) Auto color killer (Chrominance signal level color burst level below specified value.) Forced color killer (Chrominance signal level forced "0".) (Video signal demodulated output regardless synchronization detection.) AUTO (Blue Back output when synchronization detected.) *00: Analog Clamp (HSY Analog, hybrid clamp clamp *00: Adaptive comb filter (Correlation lines monitored operating mode selected.) Non-adaptive comb filter (Operating mode always fixed.) trap filter. (Comb filter used.) Undefined
Video output mode
MRA[5] MRA[4] MRA[3:1]
Chroma format Video input model Video Input mode2
MRA[0]
Disable MODE[3:0]
Mode Register (MRB) MRB[7:6]
Write only
Synchronization mode
MRB[5]
Color killer mode
MRB[4]
Blue Back
MRB[3:2]
Clamp mode
MRB[1:0]
separation mode
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Semiconductor Note: Adaptive comb filter Non-adaptive comb filter 2/3-line comb filter NTSC Comb filter/trap filter 3-line comb filter NTSC 2-line cosine comb filter <address: $02>
MSM7662
Mode Register (MRC) MRC[7]
Write only
Auto MRC[6] Pixel Alignment pixel position compensating circuit. pixel position compensating circuit. MRC[5] Pixel Sampling Rate (4:2:2) (4:1:1) MRC[4] Data-pass control DECIMATOR sampling DECIMATOR Note: This register valid when clock MHz) input. MRC[3] SAV, V-status During blanking, During blanking, while data detected, MRC[2] output level MRC[1:0] Undefined Horizontal Sync Trimmer (HSYT) HSYT[7:4] HSYT[3:0] Write only <address: $03> (*$0): (-32 pixels) (*$0): (-32 pixels) <address: $04> (*$1E):
NTSC/PAL Auto select
start trimmer pixels) stop trimmer pixels) Write only
Sync. Threshold level adjust (STHR) STHR[7:0] Sync. depth
Horizontal Sync Delay (HSDL) HSDL[7:0]
Write only
<address: $05>
HSYNC_L delay trimmer pixel) (*$00): -128 +127 (-128 +127 pixels) Note: internal sync separation (PLLSEL: Low) mode, HSYNC_L sync signal output position adjusted. external sync separation (PLLSEL: High) mode, phase shift H-Sync input video signal input adjusted. Horizontal Valid Trimmer (HVALT) Write only <address: $06>
HVALT[7:4] HVALID start trimmer pixels) (*$0): (-16 pixels) HVALT[3:0] HVALID stop trimmer pixels) (*$0): (-16 pixels)
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Semiconductor Vertical Valid Trimmer (VVALT) Write only <address: $07> (*$0): (*$0): <address: $08>
MSM7662
VVALT[7:4] VVALID start trimmer line) VVALT[3:0] VVALID stop trimmer line) Luminance Control (LUMC) LUMC[7] Write only
Note: Control range while limiter 16.235 LUMC[6] Pre-filter prefilter prefilter LUMC[5:4] Aperture bandpass select *00: range0 (middle) range1 range2 range3 (high) LUMC[3:2] Coring range select *00: coring +/-4LSB +/-5LSB +/-7LSB LUMC[1:0] Aperture filter weighting factor *00: 0.00 0.25 0.75 1.50 AGC/Pedestral Loop filter control (AGCLF) Write only
Output level limiter
<address: $09>
AGCLF[7:6] loop filter time constant slow *01: medium fast mode AGCLF[5:0] reference level (*$00): Sync separation level (SSEPL) Write only SSEPL[7] SSEPL[6:0] Pedestal Clamp on/off Sync. separation level <address: $0A> pedestal clamp pedestal clamp (AGC stops operating) (*$00): <address: $0B>
Chrominance Control (CHRC) Write only CHRC[7:4] CHRC[3] Note: Control range while limiter 16.224 Undefined C-Output level limiter
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Semiconductor CHRC[2] CHRC[1:0] Chroma bandpass filter Color kill threshold factor 0.500 color burst level *01: 0.250 color burst level 0.125 color burst level Color killer
MSM7662
Loop filter control (ACCLF) Write only
<address: $0C>
ACCLF[7] Undefined ACCLF[6:5] loop filter time constant slow *01: medium fast mode ACCLF[4:0] reference level (*$00):
control (HUE) HUE[7:0] control
Write only
<address: $0D> (*$00): -180 +178.6 degrees
Output phase control data (OPCY) Write only OPCY[7:2] OPCY[1:0]
<address: $0E>
Undefined Output phase control data *00: normal forward clock backward clock backward clock
Output phase control data (OPCC) Write only OPCC[7:2] OPCC[1:0]
<address: $0F>
Undefined Output phase control data *00: normal forward clock backward clock backward clock
Optional Mode Register (OMR) Write only OMR[7] output timing select <address: $10> clamp position adjust circuit clamp position adjust circuit 34/47
Semiconductor OMR[6]
MSM7662
OMR[5:3]
OMR[2]
OMR[1] OMR[0]
VSYNC output timing select VSYNC_L synchronized HSYNC_L then output VSYNC_L output when VSYNC input signal detected. Multiplex signal detection level (VBID etc.) 000: 001: *010: 011: 100: 101: 110: 111: Hi-Z Output SLEE MODE Active Hi-Z Status2 output mode NTSC/PAL identification HLOCK sync detection Status3 output mode TV/VCR identification CSYNC Write only <address: $11> *00: Undifined *000: ADI-VIN1 (composite) 001: ADI-VIN2 (composite) 010: ADI-VIN3 (composite) 011: ADI-VIN4 (composite) 100: ADI-VIN5 (composite) 101: ADI-VIN1 (Y), AD2-VIN5 110: ADI-VIN2 (Y), AD2-VIN6 111: Prohibited setting (ADC enters sleep state) <address: $12>
register (ADC1) ADC1[7] ADC1[6] ADC1[5:4]
Video select Comparator select Clamp current select
ADC1[2:0]
input select
register (ADC2) ADC2[7]
Write only
gain control mode select manual auto 000: 1.00 *001: 1.35 010: 1.75 011: 2.30 100: 3.00 35/47
ADC2[6:4]
gain manual select
Semiconductor 101: 3.80 110: 5.00 111: 2.05 initialize condition gain select initialize initialize gain control stage select change change *10: change loop Write only <address: $13>
MSM7662
ADC2[3]
ADC2[1:0]
register (ADC3) ADC3[7] ADC3[6:4]
ADC3[2:0]
Undefined gain control margin level select 000: 001: *010: 011: 100: gain control line select 000: line 001: lines *010: lines 011: lines 100: lines Write only <address: $14>
level detect register (ZLD) ZLD[7:3] ZLD[2:0]
Undefined level detect width pixel) 000: Undefined 001: pixels *010: pixels 011: pixels 100: pixels 101: pixels 110: pixels 111: pixels Read only <address: $20>
Status register (STATUS) STATUS[7:5] STATUS[4] STATUS[3] STATUS[2] STATUS[1] STATUS[0]
Undefined interval multiplex signal detection Non-detection, Detection HLOCK sync detection Non-detection, Detection NTSC/PAL identification NTSC, TV1/TV2 identification Mode Register (bit TV1, FTFO overflow detection Non-detection, Detection 36/47
Semiconductor Relationship between Register Setting Value Adjusted Value Horizontal Sync Trimmer Position adjustment sync chip clamp timing signal HSYT [7:4] :Adjusting starting position
MSM7662
Register Setting Value (Ox)
Adjusted Value (Pixel)
HSYT [3:0]
:Adjusting position
Register Setting Value (Ox)
Adjusted Value (Pixel)
Horizontal Sync Delay Adjustment starting position horizontal sync signal HSDL [7:0]
MSB[7 -128 -112 -127 -111 -126 -110 -125 -109 -124 -108 -123 -107 -122 -106 -121 -105 -120 -104 -119 -103 -118 -102 -117 -101 -116 -100 -115 -114 -113 +112 +113 +114 +115
+100 +116 +101 +117 +102 +118 +103 +119 +104 +120 +105 +121 +106 +122 +107 +123 +108 +124 +109 +125 +110 +126 +111 +127
37/47
Semiconductor Horizontal Valid Trimmer Position adjustment horizontal valid pixel timing signal HVALT [7:4]
Register Setting Value (Ox)
MSM7662
:Adjusting starting position
Adjusted Value (Pixel)
HVALT [3:0]
Register Setting Value (Ox)
:Adjusting position
Adjusted Value (Pixel)
Vertical Valid Trimmer Position adjustment vertical valid line timing signal VVALT [7:4]
Register Setting Value (Ox)
:Adjusting starting position
Adjusted Value (Line)
VVALT [3:0]
Register Setting Value (Ox)
:Adjusting position
Adjusted Value (Line)
Loop filter control AGCLF [5:0]
Register Setting Value (Ox)
:Adjusting sync level
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Semiconductor Sync separation level SSEPL [6:0]
Register Setting Value (Ox)
MSM7662
:Adjusting blanking level
Loop filter control ACCLF [4:0]
Register Setting Value (Ox)
:Adjusting color burst level
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Semiconductor control Adjustment color subcarrier phase [7:0]
Register Setting Value (Ox)
MSM7662
-90.0 -88.6 -87.2 -85.8 -84.4 -83.0 -81.6 -80.2 -78.8 -77.3 -75.9 -74.5 -73.1 -71.7 -70.3 -68.9
-67.5 -66.1 -64.7 -63.3 -61.9 -60.5 -59.1 -57.7 -56.3 -54.8 -53.4 -52.0 -50.6 -49.2 -47.8 -46.4
-45.0 -43.6 -42.2 -40.8 -39.4 -38.0 -36.6 -35.2 -33.8 -32.3 -30.9 -29.5 -28.1 -26.7 -25.3 -23.9
-22.5 -21.1 -19.7 -18.3 -16.9 -15.5 -14.1 -12.7 -11.3 -9.8 -8.4 -7.0 -5.6 -4.2 -2.8 -1.4
+0.0 +1.4 +2.8 +4.2 +5.6 +7.0 +8.4 +9.8 +11.3 +12.7 +14.1 +15.5 +16.9 +18.3 +19.7 +21.1
+22.5 +23.9 +25.3 +26.7 +28.1 +29.5 +30.9 +32.3 +33.8 +35.2 +36.6 +38.0 +39.4 +40.8 +42.2 +43.6
+45.0 +46.4 +47.8 +49.2 +50.6 +52.0 +53.4 +54.8 +56.3 +57.7 +59.1 +60.5 +61.9 +63.3 +64.7 +66.1
+67.5 +68.9 +70.3 +71.7 +73.1 +74.5 +75.9 +77.3 +78.8 +80.2 +81.6 +83.0 +84.4 +85.8 +87.2 +88.6
+90.0 +91.4 +92.8 +94.2 +95.6 +97.0 +98.4 +99.8
-180.0 -157.5 -135.0 -112.5 -178.6 -156.1 -133.6 -111.1 -177.2 -154.7 -132.2 -109.7 -175.8 -153.3 -130.8 -108.3 -174.4 -151.9 -129.4 -106.9 -173.0 -150.5 -128.0 -105.5 -171.6 -149.1 -126.6 -104.1 -170.2 -147.7 -125.2 -102.7 -168.8 -146.3 -123.8 -101.3 -167.3 -144.8 -122.3 -165.9 -143.4 -120.9 -164.5 -142.0 -119.5 -163.1 -140.6 -118.1 -161.7. -139.2 -116.7 -160.3 -137.8 -115.3 -158.9 -136.4 -113.9 -99.8 -98.4 -97.0 -95.6 -94.2 -92.8 -91.4
+112.5 +135.0 +157.5 +113.9 +136.4 +158.9 +115.3 +137.8 +160.3 +116.7 +139.2 +161.7 +118.1 +140.6 +163.1 +119.5 +142.0 +164.5 +120.9 +143.4 +165.9 +122.3 +144.8 +167.3
+101.3 +123.8 +146.3 +168.8 +102.7 +125.2 +147.7 +170.2 +104.1 +126.6 +149.1 +171.6 +105.5 +128.0 +150.5 +173.0 +106.9 +129.4 +151.9 +174.4 +108.3 +130.8 +153.3 +175.8 +109.7 +132.2 +154.7 +177.2 +111.1 +133.6 +156.1 +178.6
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Semiconductor
MSM7662
Filter Characteristics
Band Pass Filter (NTSC ITU-R601)
Level [dB]
-100 Frequency [MHz]
Band Pass Filter (PAL ITU-R601)
Level [dB]
-100 Frequency [MHz]
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Semiconductor
MSM7662
Trap Filter (NTSC ITU-R601)
Level [dB]
-100 Frequency [MHz]
Trap Filter (PAL ITU-R601)
Level [dB]
-100 Frequency [MHz]
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Semiconductor
MSM7662
Filter
Level [dB]
-100 Frequency [MHz]
Sharp Filter
Level [dB]
-100 Frequency [MHz]
43/47
Semiconductor
MSM7662
Decimation Filter
Level [dB]
-100 Frequency [MHz]
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Semiconductor
MSM7662
BASIC APPLICATION CIRCUIT EXAMPLES
Application Circuit FIFO-1 FIFO-2 Modes
Video (Composite input) Controller 1000 1000 1000
RESET_L AVDD VIN(1:4) VRT1 AMPOUT ADIN1 CLPOUT1 VRCL1 VRB1 MSM7662
DAVDD
DVDD Y(7:0) C(7:0) B(7:0) Video
Video input)
VIN(5:6) VRT2 AMPOUT2 ADIN2 CLPOUT2 VRB2 AGND DAGND DGND MODE[3:0]
HVALID VVALID HSYNC_L VSYNC_L CLKX2O CLKXO CLKX2
Connect M7662 decoder video device according output interface (ITUR656, 8-bit [YCbCr], 16-bit [YCbCr], RGB). Video input five composite inputs S-Video inputs. Connect unused video input pins AGND. composite signal input, input side (video amp, converter, etc.) will operation state. input limited composite signal, connect (5:6), VRT2, VRB2, AMPOUT2, ADIN2, CLPOUT2 pins AGND. Externally attached components such capacitors removed. MODE[3:0] pins prescribed setting. Supply power analog, A/D, digital circuits circuit board should separated power source wherever possible. Power lines analog circuits must wide impedance.
45/47
Semiconductor Application Circuit FM-1 FM-2 Modes
MSM7662
Video (Composite input) Controller
1000 1000 1000 Memory control signal
RESET_L AVDD VIN(1:4) VRT1 AMPOUT ADIN1 CLPOUT1 VRCL1 VRB1
DAVDD
DVDD
M[7:4] Y(7:0) C(7:0) B(7:0)
Field memory Field memory Video
Video input)
MSM7662
VIN(5:6) VRT2 AMPOUT2 ADIN2 CLPOUT2 VRB2 AGND DAGND DGND MODE[3:0]
CLKXO HVALID VVALID HSYNC_L VSYNC_L CLKX2O CLKX2
Select either 16-bit [YCbCr] output output interface. Number field memories utilized 16-bit [YCbCr]: field memories. RGB: field memories. Video input five composite inputs S-Video inputs. Connect unused video input pins AGND. composite signal input, input side (video amp, converter, etc.) will operation state. input limited composite signal, connect (5:6), VRT2, VRB2, AMPOUT2, ADIN2, CLPOUT2 pins AGND. Externally attached components such capacitors removed. MODE[3:0] pins prescribed setting. MF-1 mode setting, externally generate supply control signals field memory. MF-2 mode setting, memory control signals from M[7:4] supplied field memory. MF-2 mode setting, output timing HSYNC_L, VSYNC_L, ODD, VVALID, HVALID becomes memory read timing. Data output from memory aligned with variout sync signal timings. (See page page Supply power analog, A/D, digital circuits circuit board should separated power source wherever possible. Power lines analog circuits must wide impedance. 46/47
Semiconductor
MSM7662
PACKAGE DIMENSIONS
(Unit
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more 0.55 TYP.
Notes Mounting Surface Mount Type Package SOP, QFP, TSOP, SOJ, (PLCC), surface mount type packages, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
47/47
E2Y0002-28-41
NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents cotained herein reprinted reproduced without prior permission. MS-DOS registered trademark Microsoft Corporation.
Copyright 1998 Electric Industry Co., Ltd.
Printed Japan

Semiconductor MSM7662 Semiconductor NTSC/PAL Digital Video Decode

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