4Bank 512K 32bits Synchronous DRAM Revision History Inicial Versi

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4Bank 512K 32bits Synchronous DRAM Revision History Inicial Versi

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64Mb Synchronous DRAM based 512K 4Bank Document Title
4Bank 512K 32bits Synchronous DRAM
Revision History Inicial Version Release Corrected OREDERING INFORMATION Corrected type error BALL CONFIGURATION Draft Date Jan. 2005 Jan. 2005 Feb. 2005 Remark Preliminary Preliminary Preliminary
This document general product description subject change without notice. Hynix does assume responsibility circuits described. patent licenses implied. Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
DESCRIPTION
Hynix HY5V62D(L/S)F(P) series 67,108,864bit CMOS Synchronous DRAM, ideally suited memory applications which require wide data high bandwidth. HY5V62D(L/S)F(P) organized 4banks 524,228 HY5V62D(L/S)F(P) series offering fully synchronous operation referenced positive edge clock. inputs outputs synchronized with rising edge clock input. data paths internally pipelined achieve very high bandwidth. input output voltage levels compatible with LVTTL. Programmable options include length pipeline (Read latency number consecutive read write cycles initiated single control command (Burst length 1,2,4,8 full page), burst count sequence(sequential interleave). burst read write cycles progress terminated burst terminate command interrupted replaced burst read write command cycle. (This pipelined design restricted '2N' rule)
FEATURES
Voltage VDD, VDDQ 3.3V supply voltage device pins compatible with LVTTL interface 90Ball FBGA with 0.8mm pitch inputs outputs referenced positive edge system clock Data mask function Internal four banks operation Burst Read Single Write operation Programmable Latency Clocks Auto refresh self refresh 4096 Refresh cycles 64ms Programmable Burst Length Burst Type full page Sequential Burst Interleave Burst
ORDERING INFORMATION
Part Number HY5V62DF(P)1-55 HY5V62DF(P)1-6 HY5V62DF(P) HY5V62DLF(P) HY5V62DLF(P) HY5V62DLF(P)1-7 HY5V62DSF(P) HY5V62DSF(P)
1-55
Clock Frequency 183MHz 166MHz 143MHz 183MHz 166MHz 143MHz 183MHz 166MHz 143MHz
Power
Organization
Interface
Package
Normal
Power
4Banks 512Kbits
LVTTL
Ball FBGA
Super Power
HY5V62DSF(P)1-7
Note: 90Ball FBGA Lead Free Package. Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
BALL CONFIGURATION
DQ26
DQ24
DQ23
DQ21
DQ28
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
VDDQ
DQ31
DQ16
VSSQ
VSSQ
DQM3
DQM2
View
/RAS
DQM1
/CAS
DQM0
VDDQ
VSSQ
VSSQ
DQ10
VDDQ
VSSQ
DQ12
DQ14
VDDQ
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ13
DQ15
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
BALL DESCRIPTIONS
SYMBOL BA0, RAS, CAS, DQM0 DQM3 DQ31 VDDQ VSSQ TYPE INPUT INPUT INPUT INPUT INPUT INPUT SUPPLY SUPPLY DESCRIPTION Clock: system clock input. other inputs registered SDRAM rising edge Clock Enable: Controls internal clock signal when deactivated, SDRAM will states among (deep) power down, suspend self refresh Chip Select: Enables disables inputs except CLK, Bank Address: Selects bank activated during activity Selects bank read/written during activity Address: RA10, Column Address: Auto-precharge flag: Command Inputs: RAS, define operation Refer function truth table details Data Mask: Controls output buffers read mode masks input data write mode Data Input Output: Multiplexed data input output Power supply Power supply connection These pads should left unconnected
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
FUNCTIONAL BLOCK DIAGRAM
512Kbit 4banks Power Synchronous DRAM
Self refresh logic timer
Internal Counter
State Machine Active
512Kx32 BANK
Decoder
512Kx32 BANK 512Kx32 BANK 512Kx32 BANK
Buffer Logic Sense Gate
X-Decoder X-Decoder X-Decoder X-Decoder
Refresh
Memory Cell Array
Column Active
DQM0~3
Column Decoder
DQ31
Y-Decoder
Bank Select
Column Counter
Address Buffers
Address Register
Burst Counter
Mode Register
Latency
Data Control
Pipe Line Control
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
Code Latency Burst Length
Code
Write Mode Burst Read Burst Write Burst Read Single Write Burst Type Sequential Interleave
Burst Type
Latency
Latency Reserved Reserved Reserved Reserved Reserved
Burst Length
Burst Length Reserved Reserved Reserved Full Page A3=1 Reserved Reserved Reserved Reserved
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
ABSOLUTE MAXIMUM RATING
Parameter Ambient Temperature Storage Temperature Voltage relative Voltage relative Voltage VDDQ relative Short Circuit Output Current Power Dissipation Soldering Temperature Time Symbol TSTG VIN, VOUT VDDQ TSOLDER Rating -1.0 -1.0 -1.0
Unit
OPERATING CONDITION (TA= 70oC
Parameter Power Supply Voltage Input High Voltage Input Voltage Symbol VDD, VDDQ -0.3 VDDQ Unit Note
Note: voltages referenced VIH(max) acceptable 5.6V pulse width with duration. VIL(min) acceptable -2.0V pulse width with duration
OPERATING TEST CONDITION (TA= VDD=3.3±0.3V, VSS=0V)
Parameter Input High Level Voltage Input Timing Measurement Reference Level Voltage Input Rise Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance Access Time Measurement Note
Vtt=1.4V
Symbol Vtrip Voutref
Value
Unit
Note
Vtt=1.4V
RT=500
RT=50
Output
Output
30pF
30pF
Output Load Circuit
Output Load Circuit
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
CAPACITANCE (TA= f=1MHz, VDD=3.3V)
Parameter Input capacitance A10, BA0, BA1, CKE, RAS, CAS, DQM0 DQM3 DQ31 Symbol CI/O Unit
Data input output capacitance
CHARACTERRISTICS (TA= 70oC)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Symbol Unit Note -2mA +2mA
Note: 3.6V, other balls tested under DOUT disabled, VOUT=0
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
CHARACTERISTICS (TA= 70oC)
Speed Parameter Symbol Test Condition Operating Current IDD1 Burst length=1, bank active tRC(min), IOL=0mA VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. tCK(min), IOL=0mA banks active tRC(min), banks active Normal Self Refresh Current IDD6 0.2V Power Super Power CL=3 Unit Note
Precharge Standby Cur- IDD2P rent IDD2PS Power Down Mode
Precharge Standby Cur- IDD2N rent Power Down Mode IDD2NS Active Standby Current Power Down Mode IDD3P IDD3PS
Active Standby Current Power Down Mode
IDD3N
IDD3NS Burst Mode Operating Current Auto Refresh Current IDD4 IDD5
Note: IDD1 IDD4 depend output loading cycle rates. Specified values measured with output open Min. (Refresh cycle time) shown CHARACTERISTICS HY5V62DF(P) Series HY5V62DLF(P) Series HY5V62DSF(P) Series
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Symbol tCK3 tCK2 tCHW tCLW tAC3 tAC2 tCKS tCKH tOLZ tOHZ3 tOHZ2 2.25 2.25 1000 1000 1.75 1.75 1.75 1.75 1000 Unit Note
System Clock Cycle Time Clock High Pulse Width Clock Pulse Width Access Time From Clock Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time Setup Time Hold Time Command Setup Time Command Hold Time
Data Output Low-Z Time Data Output High-Z Time Note:
Assume (input rise fall time) 1ns. 1ns, then [(tR+tF)/2-1]ns should added parameter. Access time measured with input signals 1V/ns edge rate, from 0.8V 2.0V. 1ns, then (tR/2-0.5)ns should added parameter.
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Cycle Time Cycle Time Delay Active Time Precharge Time Bank Active Delay Delay Write Command Data-In Delay Data-in Precharge Command Data-In Active Command Data-Out Hi-Z Data-In Mask Command Precharge Data Output High-Z Power Down Exit Time Self Refresh Exit Time Refresh Time Operation Auto Refresh Symbol 16.5 38.7 16.5 100K 100K tDPL 100K Unit Note
tRRC tRCD tRAS tRRD tCCD tWTL tDPL
tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF
Note: command given after self refresh exit.
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
COMMAND TRUTH TABLE
Command Mode Register Operation Bank Active Read Read with charge Write Write with charge AutopreH AutopreH CKEn-1 CKEn ball High (Other balls code) Mode ADDR A10/AP code Note
Precharge Banks Precharge selected Bank Burst Stop Auto Refresh Burst-Read-SingleWRITE Entry Self Refresh1 Exit
Entry Precharge power down Exit
Clock Suspend
Entry Exit
Rev. Feb. 2005
111Preliminary Synchronous DRAM Memory 64Mbit (2Mx32bit) HY5V62D(L/S)F(P) Series
PACKAGE INFORMATION
Ball FBGA, 13mm 1.2mm, 0.8mm pitch
Unit [mm]
8.00± 0.10
0.8(Typ)
Index Mark
6.40
0.8(Typ)
0.450 0.05
Bottom View
6.50 0.05 6.50 0.05
13.0 0.10
11.20
3.20 0.05
4.00
0.05
0.340 0.05
Side View
Rev. Feb. 2005

4Bank 512K 32bits Synchronous DRAM Revision History Inicial Versi

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