KS7301B CMOS designed Digital Camcorder System. This Processor Compati

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KS7301B CMOS designed Digital Camcorder System. This Processor Compati

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KS7301B
KS7301B CMOS designed Digital Camcorder System. This Processor Compatible NTSC/PAL Hiband/Normal Camcorder System.
DIGITAL CAMERA PROCESSOR
160-QFP-2424
FEATURES
Luminance Chroma Signal Procession Built Timing Generator Built Sync. Generator Built Memory Detection Part (16bit* word*2 page) Built delay line *910) Built Encoder PAL/NTSC Built Interface Block Built Super Impose function Built Title Block Compatible with NORMAL/Hi Band System Built Micro controller Interface Block
ORDERING INFORMATION
Device KS7301B Package 160-QFP-2424 Operating Temperature -20°C +75°C
BLOCK DIAGRAM
SDATA DISRSTN LSSE
TST0
TST1
<7:0> <7:0> HEODN VEODN <7:0> <7:0>
(Detection Module)
(Color Processing Module)
MA(Matrix Module)
(Encoding Module)
SPDAC SPDAY SYNC LALT
XSG1 XSG2
<19:0>
(Timing Generation Module)
(BUS Interface Module)
(SuperImpose Module)
<7:0> VCOL<2:0>
RESETN DCPN SAM8NECN
VBLK VDATA
SOEN SWEN SCSROMN
SCSRAMN
AD<7.0> PALNTN DCPCSN ASTB WAITN
XSUB CLP1 CLP2 CLP3 CLP4 PBLK
KS7301B
DIGITAL CAMERA PROCESSOR
CONFIGURATION
SPDAY SSA<19> SSA<18> SSA<17> SSA<16> SSA<15> SSA<14> SSA<13> SSA<12> SSA<11> SSA<10> SSA<9> SSA<8> SSA<7> SSA<6> SSA<5> SSA<4> SSA<3> SSA<2> SSA<1> SSA<0> SSD<7> SSD<6> SSD<5> SSD<4> SSD<3> SSD<2>
Y<4> Y<3> Y<2> Y<1> Y<0> SPDAC LALT SYNC
DISRSTN
Y<5> Y<6> Y<7> C<0> C<1> C<2> C<3> C<4> C<5> C<6> VDDIN C<7> SDATA VSSIN LSSE HEODN VEODN DIS<0> DIS<1> DIS<2> DIS<3> DIS<4> DIS<5> DIS<6> DIS<7> VDDIN DOS<0> DOS<1> DOS<2> DOS<3> DOS<4> DOS<5> DOS<6> DOS<7>
KS7301B
SSD<1> SSD<2> SCSRAMN SCSROMN SWEN SOEN VDATA VCOL<2> VCOL<1> VCOL<0> VSSIN VBLK SAM8NECN AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> WAITN DCPCSN VSSIN RESETN PALNTN DCPN
TST0 TST1 VDDIN
XSG1 XSG2 XSUB
CLP1 CLP2 CLP3 CLP4 PBLK
KS7301B
DESCRIPTIONS
Symbol DISRSTN CLP1 CLP2 CLP3 CLP4 PBLK XSG1 XSG2 XSUB TST0 TST1 VDDIN
DIGITAL CAMERA PROCESSOR
Description Secondary Pipe Line clock PCK/2 Main Pipe Line Clock Line Signal Reset Signal Active connection connection Power supply connection connection connection connection connection connection Converter Sampling Clock Clamp Pulse Clamp Pulse Clamp Pulse Clamp Pulse Video Blanking Pulse Data Sampe Hold Pulse Ground Pre-Charge Sample Hold Pulse Horizontal Driving Pulse Horizontal Driving Pulse Pre-Charge Gate Pulse Read Pulse Read Pulse Discharge Pulse Vertical Driving Pulse Vertical Driving Pulse Vertical Driving Pulse Vertical Driving Pulse Power Supply Ground Main X-tal Input Main X-tal Output Test Test Output Power Supply (INTERNAL) Power Supply
Remark
KS7301B
DIGITAL CAMERA PROCESSOR
DESCRIPTIONS (Continued)
Symbol DCPN PALNTN RESETN VSSIN DCPCSN WAITN DSN(RDN) ASN(AS) AD<0> AD<1> AD<2> AD<3> AD<4> AD<5> AD<6> AD<7> SAM8NECH VBLK VSSIN VCOL<0> VCOL<1> VCOL<2> VDATA SOEN SWEN SCSROMN SCSRAMN SSD<0> SSD<1> Description Test 4Fsc Input (17.73447MHz) 4Fsc Output Ground Ground PAL/NTSC Mode Select 760H/510H Mode Selection Reset Input Power Supply Phase Comparator Output Ground (INTRENAL) Chip Select (Low Active) Wait Micom Interface (Low Active) Remark
Micro controller Address Data
Ground Part Pulse (VCR Mode Title Mix) Part Pulse (VCR Mode Title Mix) Microcontroller Type Select (SAM8:High, NEC:Low) Title Blank Signal Mode Title Ground (INTERNAL) Title Color Signal Mode Title
Title Data Enable Signal Mode Title Enable Superimpose Active Enable Superimpose Active Chip Select Superimpose Active Chip Select Superimpose Active Memory Interface Data Superimpose
KS7301B
DIGITAL CAMERA PROCESSOR
DESCRIPTIONS (Continued)
Symbol SSD<2> SSD<3> SSD<4> SSD<5> SSD<6> SSD<7> SSA<0> SSA<1> SSA<2> SSA<3> SSA<4> SSA<5> SSA<6> SSA<7> SSA<8> SSA<9> SSA<10> SSA<11> SSA<12> SSA<13> SSA<14> SSA<15> SSA<16> SSA<17> SSA<18> SSA<19> SPDAY SYNC LALT SPDAC Y<0> Y<1> Y<2> Y<3> Y<4> Description Power supply Memory Interface Data Superimpose Remark
Memory Interface Address Output Superimpose
Ground Memory Interface Address Output Superimpose
Memory Interface Address Output Superimpose
Converter Sampling Clock Signal (PCK) Chroma Subcarrier (NTSC 3.7595MHz, 4.4336MHz) Burst Flag Pulse Video Composite SYNC signal Line Atternate Pulse Converter Sampling Clock Signal (4Fsc) Video Signal Output
Ground
KS7301B
DIGITAL CAMERA PROCESSOR
DESCRIPTIONS (Continued)
Symbol Y<5> Y<6> Y<7> C<0> C<1> C<2> C<3> C<4> C<5> C<6> VDDIN C<7> SDATA VSSSIN LSSE HEODN VEODN DIS<0> DIS<1> DIS<2> DIS<3> DIS<4> DIS<5> DIS<6> DIS<7> VDDIN DOS<0> DOS<1> DOS<2> DOS<3> DOS<4> DOS<5> DOS<6> DOS<7> Video Signal Output Description Remark
Video Signal Output
Power supply (INTERNAL) Video Signal Output Interface Serial Data Interface Load Signal signal signal Ground (INTERNAL) Power supply Shutter Speed Enable Video Field Signal Chroma Pixel Control (Default High) Chroma 2R-G, G-2B Line Control (Default High) Video Input Signal
Power supply (INTERNAL) Video Input Signal Ground Video Input Signal
KS7301B
DIGITAL CAMERA PROCESSOR
REMARK Main Pipe Line Clock 510H: NTSC 1820/3fh, 6/3fh 760H: NTSC 910fh, 908fh Main X-tal Input NTSC:28.63636MHz, PAL:28,375Mhz Test TST1, TST0, DCPN) 0,0,0 TEST 0,0,1 TEST 0,1,0 TEST 0,1,1 TEST 1,0,0 TEST 1,0,1 TEST HIGH 1,1,0 NORMAL 1,1,1 RESERVED Phase Comparator Output Include Charge Pump Part Mode Data Strobe Signal Input Active Mode Read Enable Active Address Strobe Micom Interface Active, High Active Mode Read Write Enable Read High, Write Mode Write Enable Active
KS7301B
ABSOLUTE MAXIMUMTINGS
Characteristics Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature
DIGITAL CAMERA PROCESSOR
(Ta=25°C) Symbol VOUT Value -0.5~6.5 -0.5~VDD+0.5 -0.5~VDD+0.5 -20~+75 -65~+150 Unit
ELECTRICAL CHARACTERISTICS
(VCC=5V, 25°C, unless otherwise specified Characteristics Supply Voltage Input Leakage Current Output Leakage Current Operating Current High-Level Input Voltage Low-Level Input Voltage Output High Voltage Output Voltage *Output High Voltage *Output Voltage **Output High Voltage **Output Voltage XPG, SHP, Pulse :H1, Pulse Symbol VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 Test Condition VDD=5V IOH=-2mA IOL=4mA IOH=-4mA IOL=8mA IOH=-8mA IOL=8mA 0.8VDD VDD-0.5 VDD-0.5 VDD-0.5 0.2VDD 0.45 0.45 0.45 Unit Remark
IO=2mA IO=4mA IO=8mA
KS7301B
DIGITAL CAMERA PROCESSOR
Micro controller Interface SAVB PIN68A HIGH
Characteristics Address setup time Address hold time ASTB pulse width ASTB, WAITN distance delay from Data width Data hold time Data delay from Data, WAITN distance ASN, distance Symbol Tast Taht Tasw Tawd Tdsdy Twrw Trdrv Tdwd Tadd Unit nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec Remark Write Read Read
Micro controller Interface SAM8 (PIN68 HIGH)
DCPCSN
Tast
ASN(AS)
ADDR
Tasw Taht Tdsdv Tawd
DATA
DSN(RDN) (WRN) AITN
Twrw
DCPCSN
Tast
ADDR
Tasw Taht Tadd Trddv
DATA
ASN(AS) DSN(RDN) (WRN) AITN
Tawd
Tdwd
READ MODE
KS7301B
DIGITAL CAMERA PROCESSOR
Micro controller Interface SAVB (PIN68 LOW)
Characteristics Address setup time Address hold time ASTB pulse width ASTB, WAITN distance Data delay from width Data hold time Data delay from Data, WAITN distance ASN, distance Symbol Tast Taht Tasw Tawd Tdsdy Twrw Trdrv Tdwd Tadd Unit nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec Remark Write Read Read
Micro controller Interface (PIN68 LOW)
DCPCSN
Tast
<7:0>
ADDR
Tasw Taht Tdsdv
DATA
ASTB (AS)
Tawd Twrw
(RWN) (DSN) WAITN WRITE MODE DCPCSN
Tast
<7:0>
ADDR
Tasw Taht Trddv
DATA
ASTB (AS)
Tawd
Tdwd
(DSN) (RWN) WAITN
READ MODE
KS7301B
DIGITAL CAMERA PROCESSOR
Vertical Timing SYNC signal
NTSC
FIELD STNC
FIELD
VBLK
FIELD STNC VBLK
FIELD
KS7301B
DIGITAL CAMERA PROCESSOR
FIELD
FIELD
7.5H STNC
VBLK
BF(3-4) BF(1-2)
FIELD
FIELD
7.5H STNC VBLK BF(34-1) BF(2-3)
KS7301B
DIGITAL CAMERA PROCESSOR
NTSC/NORMAL
NTSC/HI8
PAL/NORMAL
PAL/HI8
KS7301B
SHP, SHD,
DIGITAL CAMERA PROCESSOR
NTSC/NORMAL OSC1 PCLK1
NTSC OSC1 PCLK1
KS7301B
DIGITAL CAMERA PROCESSOR
XSUB 10000 Shutter Speed Mode
NTSC 1/60 XSG1 XSUB
NORMAL
KS7301B
Horizontal Timing XSG1,XSG2
DIGITAL CAMERA PROCESSOR
EVEN
XSG1 XSG2 unit
Normal 39.5 43.5
HI18 42.2 47.2
KS7301B
Horizontal Timing CCD(NTSC/NORMAL)
CBLK
CLP1
CLP2
CLP3
CLP4
DIGITAL CAMERA PROCESSOR
XSUB
KS7301B
Horizontal Timing CCD(PAL/NORMAL)
CBLK
CLP1
CLP2
CLP3
CLP4
DIGITAL CAMERA PROCESSOR
XSUB
KS7301B
Horizontal Timing CCD(NTSC/HI8)
CBLK
CLP1
CLP2
CLP3
CLP4
DIGITAL CAMERA PROCESSOR
XSUB
KS7301B
Horizontal Timing CCD(PAL/HI8)
CBLK
CLP1
CLP2
CLP3
CLP4
DIGITAL CAMERA PROCESSOR
XSUB
KS7301B
Vertical Timing CCD(NTSC/NORMAL)
CBLK
XSG1
XSG2
CLP1
CLP2
DIGITAL CAMERA PROCESSOR
CLP3,4
KS7301B
Vertical Timing CCD(PAL/NORMAL)
CBLK
XSG1
XSG2
CLP1
CLP2
DIGITAL CAMERA PROCESSOR
CLP3,4
KS7301B
Vertical Timing CCD(NTSC/HI8)
CBLK
XSG1
XSG2
CLP1
CLP2
DIGITAL CAMERA PROCESSOR
CLP3,4
KS7301B
Vertical Timing CCD(PAL/HI8)
CBLK
XSG1
XSG2
CLP1
CLP2
DIGITAL CAMERA PROCESSOR
CLP3,4
KS7301B
REGISTER MAPPING
REGISTER NAME ADDRESS NO.(HEX) BITS MODE
DIGITAL CAMERA PROCESSOR
DESCRIPTION Status Register
High Superimpose Busy Superimpose Stanby High :Hi8 Mode :Normal Mode High :PAL Mode :NTSC Mode
DADR
Detection Address Pointing Register Just with assignment Start point, increasing step Address automatically. read first small picture, Address value 00(HEX) (LSB using) Detection Data Register
DMDH DMDL
DMDL
DMDH DCMD
Read cycle achieve which DMDH DMDL Register AE/AF/AWB detection Data Command Register
High Peak-hold Data Detection Integration Data Detection High High Clock Delay Even Clock Delay High Page Micom Read Page Micom Read High Detection Read Detection Write High Data Detection Data Detection High Mode Mode High Mode Mode
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME DDIS COV1 COV2 CC0A CC0B CAKP CNSL
ADDRESS NO.(HEX)
BITS MODE
DESCRIPTION Mode Control Register Knee Delta Coeff. Register Default Range 255( Knee Coeff. Register Half value Knee Point Range 255( Aperture Gain Register Range 255( Color Coeff.1 Register Default 0.12 Range 6dB( Color Coeff.2 Register Default Range 6dB( Knee Point Value Range 255( Aperture Noise Slice Level Range 255( Bdge Chroma Suppress
Gain Suppress Limit Level
CAPS
CRC0 CBC0 CGC0 CUTH CLTH;
Deciding amount Max, Suppress fixing suppress Limit Level Cr(=2R-G) Gain Range Cb(=G-2B) Gain Range Gain Range Superimpose Mode Input Data High Threshold Range Superimpose Mode Input Data Threshold Range
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME MRPW MGPW MBPW MRWB MBWB MDSCR MDSCR MDSCR MRHC
ADDRESS NO.(HEX)
BITS MODE
DESCRIPTION Pre-white Balance Coeff. Range 18dB Green Pre-white Balance Coeff. Range 18dB Blue Pre-white Balance Coeff. Range 18dB White Balance Coeff. Range 18dB Blue White Balance Coeff. Range 18dB Black Balance Coeff. (2'C Data) Range -127(HEX +127 (HEX
MBHC
MRYG MBYG MA1C MB1C MA2C MB2C
Control Value (MRHC*[B-Y]) Range -(B-Y) +(B-Y) Sign Absolute Value Control Value (MBHC*[R-Y]) Range -(R-Y) +(R-Y) Sign Absolute Value Gain Range 0~18dB (FF) Gain Range 18dB (FF) Color difference signal Matrix Coeff Range Recommand Value: MA1C (HEX MB1C (HEX MA2C 0.11 (HEX MB2C 0.89 (HEX
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME EHSBY
ADDRESS NO.(HEX)
BITS MODE
DESCRIPTION axis direction Burst Level (2'C Data) Range -128(HEX (HEX Sign Value axis direction Burst Level Data) Range -128(HEX (HEX Sign Value Chroma Fade Control Value Range White Clip Level Range Luminance Fade Control Value Range 18dB Set-up Level Range Blanking Level Range Command Register
EHSRY
ECFAD EWCLP EYFAD ESET EBLK ECMD1
Negative Effect Normal Operation Output Disable Normal Operation Normal Operation step16 Freeze step Freeze step Freeze Clock Inverting Normal Operation Digital Interface Mode Normal Operation Digital Interface Mode Normal Operation Output Enable Output Disable
ECMD2
Delay Adjust
Title delay daj. Range
delay adj. Range PCLK
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME TCMD1
ADDRESS NO.(HEX)
BITS MODE
DESCRIPTION Shutter Speed Control
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1111 1100 1101 1110 1111 1/60 (PAL 1/50 sec) 1/85 1/125 1/185 1/250 1/375 1/500 1/750 1/1000 1/1500 1/2000 1/2500 1/4000 1/6000 1/10000 Flicker Mode
1/30 1/15 Normal Shutter Speed enable
ECMD2
Flickerless Control
High NTSC 1/120 sec, 1/100 Flickerless Mode
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME SCMD
ADDRESS NO.(HEX)
BITS MODE
DESCRIPTION Superimpose Command Register
REMARK
Superimpose Instruction Format
Instruction Code
TYPE CT1=0, CT2=0) Environmental Instruction
STOP MEDi SWAP
Conditions MEDi SWAP
TYPE (CT1=0, CT0=0) Configure Environment (R/W, SCOLL)
READ WRITE
Occur Superimpose Busy Flag while sci, operation Mode. And, impossible excute other superimpose intermediate this status. (About seconds)
KS7301B
REGISTER NAME ADDRESS NO.(HEX)
DIGITAL CAMERA PROCESSOR
BITS MODE
DESCRIPTION
REMARK
TYPE2 Environmental Instruction
Normal Wiper Inverse Wiper Normal FILL Mode
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 :F10 1011 1100 1101 1110 1111
Occur Superimpose Busy Flag while wiper operation Mode. impossible excute other superimpose intermediate this status (About seconds) TYPE Configure Environment
TST1
KS7301B
REGISTER NAME SCOL ADDRESS NO.(HEX) BITS MODE
DIGITAL CAMERA PROCESSOR
DESCRIPTION Super impose Color Status Register REMARK
Medi Medi Toggle Toggle
Swap Swap Mode Mode Blank Blue Magenta Green Cyan Yellow White
Color
status READ/WRITE, other bits READ only
SDAT
Data Register (Buffer using test mode) Setting mode stage
Normal Page Page Page Page
Page Page
KS7301B
REGISTER NAME SADR00 SADR01 SADR02 SADR10 SADR11 SADR12 SADR20 SADR21 SADR22 SADR30 SADR31 SADR32 SADR40 SADR41 SADR42 ADDRESS NO.(HEX)
DIGITAL CAMERA PROCESSOR
BITS MODE
DESCRIPTION image address register (20Bit)
REMARK
image address register (20Bit)
image address register (20Bit)
image address register (20Bit)
image address register (20Bit)
SADR02
SADR01
SADR00
SADR02 uses only 4Bit. SSYN Horizontal counter test register (Used test) Vertical counter test register (Used test) Title horizontal position adjusting value (After reset, SVRT allowed.)
Title vertical position adjusting value (After reset, allowed.)
KS7301B
PACKAGE DIMENSION
DIGITAL CAMERA PROCESSOR
Unit

KS7301B CMOS designed Digital Camcorder System. This Processor Compati

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