PALCE29MA16H-25 24-Pin CMOS Programmable Array Logic DISTINC

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PALCE29MA16H-25 24-Pin CMOS Programmable Array Logic DISTINC

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COM'L: H-25
PALCE29MA16H-25
24-Pin CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
High-performance semicustom logic Register/Latch Preload permits full logic
replacement; Electrically Erasable (EE) technology allows reprogrammability bidirectional user-programmable logic macrocells Combinatorial/Registered/ Latched operation Output Enable controlled product terms Varied product term distribution increased design flexibility Programmable clock selection with common clock/latch enable (LE) individual product term clock/LE with LOW/HIGH clock/ polarity
verification
High speed (tPD fMAX fMAX
internal MHz)
Full-function testing factory
high programming functional yields high reliability 24-pin SKINNYDIP 28-pin plastic leaded chip carrier packages Extensive third-party software programmer support through FusionPLD partners
GENERAL DESCRIPTION
PALCE29MA16 high-speed, CMOS Programmable Array Logic (PAL) device designed general logic replacement CMOS digital systems. offers high speed, power consumption, high programming yield, fast programming, excellent reliability. devices combine flexibility custom logic with off-the-shelf availability standard products, providing major advantages over other
BLOCK DIAGRAM
CLK/LE I/OF I/OF
I/O7
I/O6
I/OF5
I/OF4
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Programmable Array 58x178
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
I/OE
I/OF0
I/OF
I/O0
I/O3
I/OF
I/OF3
08811G-1
Publication# 08811 Rev. Issue Date: June 1993 Amendment
2-349
GENERAL DESCRIPTION (continued)
semicustom solutions such gate arrays standard cells, including reduced development time upfront development cost. PALCE29MA16 uses familiar sum-of-products (AND-OR) structure, allowing users customize logic functions programming device specific applications. provides array inputs outputs. incorporates AMD's unique input/output logic macrocell which provides flexible input/output structure polarity, flexible feedback selection, multiple Output Enable choices, programmable clocking scheme. macrocells individually programmed combinatorial, registered, latched with active-HIGH active-LOW polarity. flexibility logic macrocells permits system designer tailor device particular application requirements. Increased logic power been built into PALCE29MA16 providing varied number logic
product terms output. outputs, outputs have product terms each, outputs have product terms each, other outputs have product terms each. This varied product-term distribution allows complex functions implemented single device. Each output dynamically controlled common Output Enable Output Enable product term. Each output also permanently enabled disabled. System operation been enhanced addition common asynchronous-Preset Reset product terms power-up Reset feature. PALCE29MA16 also incorporates Preload Observability functions which permit full logic verification design. PALCE29MA16 offered space-saving 300-mil SKINNYDIP package well plastic leaded chip carrier package.
CONNECTION DIAGRAMS View SKINNYDIP
PLCC
CLK/LE
I/OF0
I/OF0 I/OF1 I/O0 I/O1 I/O2 I/O3 I/OF2 I/OF3 I/OE
I/OF7 I/OF6 I/O7 I/O6 I/O5 I/O4 I/OF5 I/OF4
08811G-2
I/OF1 I/O0 I/O1 I/O2 I/O3 I/OF2
I/OF6 I/O7 I/O6 I/O5 I/O4 I/OF5
I/OF3 I/OE I/OF4
I/OF7
08811G-3
Note: marked orientation.
DESIGNATIONS
CLK/LE I/OF 2-350 Clock Latch Enable Ground Input Input/Output Input/Output with Dual Feedback Supply Voltage Connection PALCE29MA16H-25
CLK/LE
ORDERING INFORMATION Commercial Products
programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination these elements:
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Advanced Asynchronous Macrocell NUMBER FLIP-FLOPS POWER Half Power (100 SPEED OPTIONAL PROCESSING Blank Standard Processing PROGRAMMING REVISION First Revision (Requires current programming Algorithm)
TEMPERATURE RANGE Commercial (0°C +75°C)
PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028)
Valid Combinations PALCE29MA16H-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
PALCE29MA16H-25 (Com'l)
2-351
FUNCTIONAL DESCRIPTION Inputs
PALCE29MA16 inputs drive each product term inputs with both TRUE complement versions available array) shown block diagram Figure these inputs, dedicated inputs, from eight logic macrocells with feedbacks, from other logic macrocells with single feedback I/OE input. Initially AND-array gates disconnected from inputs. This condition represents logical TRUE array. selectively programming cells, array connected either TRUE input complement input. When both TRUE complement inputs connected, logical FALSE results output gate.
device ranging from wide, with average logic product terms output. increased number product terms output allows more complex functions implemented single device. This flexibility aids implementing functions such counters, exclusive-OR functions, complex state machines, where different states require different numbers product terms. Individual asynchronous-Preset Reset product terms connected Registered Latched I/Os. When asynchronous-Preset product term asserted (HIGH) register latch will immediately loaded with HIGH, independent clock. When asynchronous-Reset product term asserted (HIGH) register latch will immediately loaded with LOW, independent clock. actual output state will depend macrocell polarity selection. latches must latched mode (not transparent mode) Reset, Preset, Preload, power-up Reset modes meaningful.
Product Terms
degree programmability complexity device determined number connections that form programmable-AND gates. Each programmable-AND gate called product term. PALCE29MA16 product terms; these product terms provide logic capability others architectural product terms. Among control product terms, Observability, Preload. Output Enable each macrocell programmed controlled common Output Enable individual product term. also permanently disabled. addition, independent product terms each macrocell control Preset, Reset CLK/LE. Each product term PALCE29MA16 consists 58-input gate. outputs these gates connected fixed-OR plane. Product terms allocated gates varied distribution across
Input/Output Logic Macrocells
logic macrocell allows user flexibility defining architecture each input output individual basis. also provides capability using associated either input output. PALCE29MA16 macrocells, each pin. Each macrocell programmed combinatorial, registered latched operation (see Figure Combinatorial output desired when device used replace combinatorial glue logic. Registers Latches used synchronous logic applications. Registers Latches with product term controlled clocks also used asychronous application.
Preset CLK/LE Reset
Common I/OE (Pin) Individual Individual Asynchronous Preset Common CLK/LE (PIN) Individual CLK/LE Individual Asynchronous Reset Array
08811G-4
Figure PALCE29MA16 Macrocell (Single Feedback) 2-352 PALCE29MA16H-25
output polarity each macrocell each three modes operation user-selectable, allowing complete flexibility macrocell configuration. Eight macrocells (I/OF0-I/OF7) have independent feedback paths array (see Figure 2b). first dedicated feedback array combinatorial input. second path consists direct register/latch feedback array. used dedicated input using first feedback path, register/latch feedback path still available array. This path provides capability using register/latch buried state register/latch. other eight macrocells have single feedback path array. This feedback user-selectable either register/latch feedback (see Figure 2a). Each macrocell provide true input/output capability. user select each macrocell register/latch driven either signal generated AND-OR array corresponding pin. When selected input, feedback path provides register/latch input array. When used input, each macrocell also user-programmable registered, latched, combinatorial input. PALCE29MA16 dedicated CLK/LE individual CLK/LE product term macrocell. macrocells have programmable switch choose between CLK/LE CLK/LE product term clock latch enable signal. These signals clock signals macrocells configured registers latch enable signals macrocells configured latches. polarity these CLK/LE signals also individually programmable. Thus different registers latches driven different clocks clock phases. Output-Enable mode each macrocells selected user. configured output (permanently enabled) input (permanently disabled). also configured
Common I/OE (Pin) Individual Individual Asynchronous Preset Common CLK/LE (PIN) Individual CLK/LE Individual Asynchronous Reset Array Array
08811G-5
dynamic controlled Output Enable product term.
Logic Macrocell Configuration
AMD's unique macrocell offers major benefits through versatile, programmable input/output cell structure, multiple clock choices, flexible Output Enable feedback selection. Eight macrocells with single feedback contain cells, while other eight macrocells contain cells programming input/ output functions (see Table cell controls whether macrocell will combinatorial registered/latched. controls output polarity (active-HIGH active-LOW). determines whether storage element register latch. allows macrocell input register/latch output register/latch. selects direction data path through register/latch. connected usual AND-OR array output, register/latch output connected pin. connected pin, register/latch becomes input register/latch array using feedback data path. Programmable cells allow user select four CLK/LE signals each macrocell. used control Output Enable controlled, product-term controlled, permanently enabled permanently disabled. controls feedback multiplexer macrocells with single feedback path only. Using programmable cells S0-S8 various input output configurations selected. Some possible configuration options shown Figure erased state (charged, disconnected), architectural cell said have value "1"; programmed state (discharged, connected GND), architectural cell said have value "0."
I/OFX
Preset CLK/LE Reset
Figure PALCE29MA16 Macrocell (Dual Feedback) PALCE29MA16H-25 2-353
Table PALCE29MA16 Logic Macrocell Architecture Selections
Cell Output Cell Input Cell Storage Element Register Latch
Output Type Combinatorial Register/Latch
Output Polarity Active Active HIGH
Feedback* Register/Latch
*Applies macrocells with single feedback only.
Table PALCE29MA16 Logic Macrocell Clock Polarity Output Enable Selections
Clock Edge/Latch Enable Level CLK/LE positive-going edge, active-LOW CLK/LE negative-going edge, active-HIGH CLK/LE positive-going edge, active-LOW CLK/LE negative-going edge, active-HIGH
Output Buffer Control Pin-Controlled Three-State Enable PT-Controlled Three-State Enable Permanently Enabled (Output only) Permanently Disabled (Input only)
Notes: Erased State (Charged disconnected). Programmed State (Discharged connected). *Active-LOW means that data stored when HIGH, latch transparent when LOW. Active-HIGH means opposite.
2-354
PALCE29MA16H-25
SOME POSSIBLE CONFIGURATIONS INPUT/OUTPUT LOGIC MACROCELL
(For other useful configurations, please refer macrocell diagrams Figure macrocell architecture cells independently programmable).
08811G-6
Output Registered/Active
08811G-7
Output Combinatorial/Active
08811G-8
08811G-9
Output Registered/Active High
Output Combinatorial/Active High
Figure Dual Feedback Macrocells
08811G-10
08811G-11
Output Registered/Active Low, Feedback
Output Combinatorial/Active Low, Feedback
08811G-12
08811G-13
Output Latched/Active High, Feedback
Output Combinatorial/Active High, Feedback
Figure Single Feedback Macrocells PALCE29MA16H-25 2-355
SOME POSSIBLE CONFIGURATIONS INPUT/OUTPUT LOGIC MACROCELL
08811G-14
Output Registered/Active Low, Register Feedback
08811G-15
Output Combinatorial/Active Low, Latched Feedback
08811G-16
Output Latched/Active Low, Latched Feedback
08811G-17
Output Combinatorial/Active Low, Latched Feedback
Figure Single Feedback Macrocells (Continued)
(FOR SINGLE FEEDBACK ONLY) REGISTER LATCH
08811G-18
PROGRAMMABLE-AND ARRAY
Programmable-AND Array
Figure Macrocells
2-356
PALCE29MA16H-25
Power-Up Reset
flip-flops power logic predictable system initialization. outputs PALCE29MA16 depend whether they selected registered combinatorial. registered selected, output will programmed active HIGH programmed active HIGH. combinatorial selected, output will function logic.
each logic macrocells. This unique feature allows easy debugging tracing buried state machines. addition, capability supervoltage observability also provided.
Security Cell
security cell provided each device prevent unauthorized copying user's proprietary logic design. Once programmed, security cell disables programming, verification, preload, observability modes. only erase protection cell erasing entire array architecture cells, which case proprietary design copied. (This cell should programmed only after rest device been completely programmed verified.)
Preload
simplify testing, PALCE29MA16 designed with preload circuitry that provides easy method testing logical functionality. Both product-term-controlled supervoltage-enabled preload modes available. TTL-level preload product term useful during debugging, where supervoltages available. Preload allows arbitrary state value loaded into registers/latches device. typical functional-test sequence would verify possible state transitions device being tested. This requires ability state registers into arbitrary "present state" value device's inputs into arbitrary "present input" value. Once this done, state machine clocked into state, "next state," which checked validate transition from "present state." this transition checked. Since preload provide capability directly desired arbitrary state, test sequences greatly shortened. Also, possible states tested, thus greatly reducing test time development costs guaranteeing proper in-system operation.
Programming Erasing
PALCE29MA16 programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erasure operation required.
Quality Testability
PALCE29MA16 offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, this verifies complete programmability functionality device yield highest programming yield post-programming functional yield industry.
Technology
high-speed PALCE29MA16 fabricated with AMD's advanced electrically-erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input-clamp diodes, output slew-rate control, grounded substrate clean switching.
Observability
output register/latch observability product term, when asserted, suppresses combinatorial output data from appearing allows observation contents register/latch output
PALCE29MA16H-25
2-357
LOGIC DIAGRAM SKINNY (PLCC) Pinouts
CLK/LE
I/OF0
Input/ Output Macro
(27)
OBSERVE PRODUCT TERM
Input/ Output Macro
(26) I/OF
I/OF1
Input/ Output Macro
Input/ Output Macro
(25) I/OF
Input/ Output Macro
Input/ Output Macro
(24)
Input/ Output Macro
(23) I/O6
Input/ Output Macro
Continued Next Page
08811G-19
2-358
PALCE29MA16H-25
LOGIC DIAGRAM SKINNY (PLCC) Pinouts
Continued from Previous Page
Input/ Output Macro
(21)
Input/ Output Macro
(10)
Input/ Output Macro
Input/ Output Macro
(20)
(11) I/OF2
Input/ Output Macro
Input/ Output Macro
(19) I/OF5
(12) I/OF
Input/ Output Macro
PRELOAD PRODUCT TERM
Input/ Output Macro
(18) I/OF4
(13) I/OE
(17) (16)
08811G-19 (concluded)
PALCE29MA16H-25
2-359
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol Parameter Description Output HIGH Voltage Output Voltage Test Conditions IOZH IOZL Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note (Note (Note VOUT (Note VOUT (Note VOUT (Note Outputs Open (IOUT -130 0.33 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-360
PALCE29MA16H-25 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS Registered Operation
Parameter Symbol Parameter Description Input Combinatorial Output Unit
Combinatorial Output
Output Register Clock tSOR tCOR tHOR Input Output Register Setup Output Register Clock Output Data Hold Time Output Register
Output Register Product Term Clock tSORP tCORP tHORP Input Output Register Setup Output Register Clock Output Data Hold Time Output Register
Input Register Clock tSIR tCIR tHIR Input Register Setup Register Feedback Clock Combinatorial Output Data Hold time Input Register
Clock Frequency tCIS tCISPP fMAX fMAXI fMAXP fMAXIPP tCWH tCWL tCWHP tCWLP Register Feedback (Pin Driven Clock) Output Register/Latch (Pin Driven) Setup Register Feedback Driven Clock) Output Register/Latch Driven) Setup Maximum Frequency (Pin Driven) 1/(tSOR tCOR) Maximum Internal Frequency (Pin Driven) 1/tCIS Maximum Frequency Driven) 1/(tSORP tCORP) Maximum Internal Frequency Driven) 1/tCISPP Clock Width HIGH Clock Width Clock Width HIGH Clock Width 33.3
PALCE29MA16H-25 (Com'l)
2-361
tSIR Input Register
AND-OR Array
Output Register
08811G-20
Input/Output Register Specs (Pin Reference)
Input
Input Register
CISPP
AND-OR Array
CISPP
Output Register CORP
tSORP
08811G-21
Input/Output Register Specs Reference)
2-362
PALCE29MA16H-25
SWITCHING WAVEFORMS
Combinatorial Input Combinatorial Output
Combinatorial Output Combinatorial Output
08811G-22
Combinatorial Input Clock
tSOR tHOR tCOR
Registered Output
Output Register (Pin Clock) Output Register (Pin Clock)
08811G-23
Combinatorial Input Combinatorial Input Clock Registered Output
SORP CORP
HORP
Output Register Clock) Output Register Clock)
08811G-24
Registered Input
Clock
Combinatorial Output
Input Register Input Register
08811G-25
PALCE29MA16H-25
2-363
SWITCHING WAVEFORMS
Clock
tCWH
Clock Width Clock Width
08811G-26
CISPP
Combinatorial Input Clock
CWLP
CWHP
08811G-27
Clock Width Clock Width
2-364
PALCE29MA16H-25
SWITCHING CHARACTERISTICS Latched Operation
Parameter Symbol tPTD Parameter Description Input Combinatorial Output Input Output Transparent Latch Unit
Combinatorial Output
Output Latch tSOL tGOL tHOL tSTL Input Output Register Setup Latch Enable Transparent Mode Output Data Hold Time Output Latch Input Output Latch Setup Transparent Input Latch Input Output Latch Setup Latch Enable Transparent Mode Output Data Hold Time Output Latch Input Output Latch Setup Transparent Input Latch
Output Latch Product Term tSOLP tGOLP tHOLP tSTLP
Input Latch tSIL tGIL tHIL Latch Enable tGIS tGISPP tGWH tGWL tGWHP tGWLP Latch Feedback (Pin Driven) Output Register/Latch (Pin Driven) Setup Latch Feedback Driven) Output Register/Latch Driven) Setup Enable Width HIGH Enable Width Enable Width HIGH Enable Width Input Latch Setup Latch Feedback, Latch Enable Transparent Mode Combinatorial Output Data Hold Time Input Latch
PALCE29MA16H-25 (Com'l)
2-365
tPTD Input Latch
AND-OR Array
Output Latch
08811G-28
Input/Output Latch Specs (Pin Reference)
INPUT
tGISPP STLP tPTD
AND-OR Array
tGISPP GOLP Output Latch
Input Latch
SOLP
08811G-29
Input/Output Latch Specs Reference)
2-366
PALCE29MA16H-25
SWITCHING WAVEFORMS
Latched Input
tPTD Latched Transparent
Combinatorial Input Combinatorial Output
tPTD Transparent
Input Latch
tGIS
Latched Output Latch
08811G-31
Latched Output
Input Output Latch Relationship
08811G-30
Latch (Transparent Mode)
Latched Input
Latched Input
STLP
Combinatorial Input
Combinatorial Input
SOLP Transparent
HOLP Transparent GOLP
Combinatorial Input Latched Output
Latched Output
Note
08811G-32
08811G-33
Output Latch (Pin
Latched Input
Output Latch
Transparent
LATCHED
TRANSPARENT
08811G-35
Combinatorial Output
Width
08811G-34
Input Latch (Pin
Combinatorial Input
Latched
Transparent tGWHP
GWLP
Note:
Width
08811G-36
combinatorial input changes while latched mode goes into transparent mode after tPTD elasped, corresponding latched output will change tGOL after goes into transparent mode. combinatorial input changes while latched mode goes into transparent mode before tPTD elapsed, corresponding latched output will change later following tPTD after combinatorial input changes tGOL after goes into latched mode.
PALCE29MA16H-25
2-367
SWITCHING CHARACTERISTICS Reset/Preset, Enable
Parameter Symbol tAPO tARO tARI tARPO tARPI Parameter Description Input Output Register/Latch Reset/Preset Asynchronous Reset/Preset Pulse Width Asynchronous Reset/Preset Output Register/Latch Recovery Asynchronous Reset/Preset Input Register/Latch Recovery Asynchronous Reset/Preset Output Register/Latch Recovery Clock/LE Asynchronous Reset/Preset Input Register/Latch Recovery Clock/LE I/OE Output Enable I/OE Output Disable (Note Input Output Enable Input Output Disable (Note Unit
Output Enable Operation tPZX tPXZ
Note: Output disable times include test load time constants.
SWITCHING WAVEFORMS
Combinatorial Asynchronous Reset/Preset Registered/ Latched Output Clock
Combinatorial/ Registered/ Latched Output
08811G-37
08811G-39
Output Register/Latch Reset/Preset
Output Disable/Enable
Combinatorial Asynchronous Reset/Preset
Combinatorial Input
Clock
08811G-38
Combinatorial/ Registered/ Latched Output
08811G-40
Input Register/Latch Reset/Preset
Input Output Disable/Enable
2-368
PALCE29MA16H-25 (Com'l)
SWITCHING WAVEFORMS
WAVEFORM
INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply
OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output
08811G-41
Specification tPD, tCO, tGOL tEA, tPZX
Switch Closed open closed
Measured Output Value
tER, tPXZ
open closed
-0.5 +0.5
PALCE29MA16H-25
2-369
PRELOAD
PALCE29MA16 capability product-term Preload. When global-preload product term true, PALCE29MA16 will enter preload mode. This feature aids functional testing allowing direct setting register states. procedure Preload follows:
selected input pins user selected
Pulse clock (pin Remove inputs pins. Remove Preload condition. Verify VOL/VOH output pins pro-
grammed pattern. Because Preload command product term, input array used Preload (including pins registers). Preload itself will change values pins registers. This will have unpredictable results. Therefore, only dedicated input pins should used Preload command.
preload condition.
Apply desired register value pins.
This sets register. value seen pin, after Preload, will depend whether macrocell active high active low.
Parameter Symbol tI/O
Parameter Description Delay Time Pulse Width Valid Output
Rec.
Unit
Inputs Preload Mode
Pins Data Preloaded
VOH/VIH VOL/VIL
08811G-42
Preload Waveform
2-370
PALCE29MA16H-25
OBSERVABILITY
PALCE29MA16 capability product-term Observability. When global-Observe product term true, PALCE29MA16 will enter Observe mode. This feature aids functional testing allowing direct observation register states. When PALCE29MA16 Observe mode, output buffer enabled value will corresponding register. This overrides inputs. procedure Observe
Remove inputs pins. Parameter Symbol tI/O
inputs the, user selected, Observe
configuration. register values will sent corresponding pins. Remove Observe configuration from selected pins. Because Observe command product term, input array used Observe (including pins registers). pins used, observe mode could cause value change, which would cause device oscillate Observe mode. Therefore, only dedicated input pins should used Observe command.
Parameter Description Delay Time Valid Output
Rec.
Unit
Input Pins
Observe Mode
Pins
08811G-43
Observability Waveform
PALCE29MA16H-25
2-371
POWER-UP RESET
registered devices Family have been designed with capability reset during system power-up. Following power-up, registers will reset LOW. output state will depend polarity output buffer. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below.
Parameter Symbol Parameter Description Power-Up Reset Time Input Feedback Setup Time Clock Width Rise Time
asynchronous operation power-up reset, wide range ways rise steady state, conditions required ensure valid power-up reset. These conditions are:
rise must monotonic. Following reset, clock input must driven
from HIGH until applicable input feedback setup times met.
Unit
Switching Characteristics
Power
Registered Active Output
Clock
08811G-44
Power-Up Reset Waveform
2-372
PALCE29MA16H-25
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm SKINNYDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
PALCE29MA16H-25
2-373

PALCE29MA16H-25 24-Pin CMOS Programmable Array Logic DISTINC

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