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DSP56311UMAD/D Rev. 11/2002 DSP56311 User's Manual
Freescale Semiconductor, Inc.
Introduction
Introduction Modified Signal Definitions Operating Mode Register (OMR) Layout Definition.6 Control Register (BCR).7 Peripheral Signal Designators Receive Register (SRX) Description Updated OMR, BCR, Timer Programming Sheets
This document provides updated information revision DSP56311 User's Manual (DSP56311UM/D). updates include following: Modified signal definitions some ground, external control, HI08, ESSI, SCI, timer signals Operating Mode Register (OMR) layout definitions Added Control Register (BCR) layout definitions Updated Peripheral Signal Designators Updated Receive Register (SRX) Description Updated Programming sheets OMR, BCR, Timer Registers (TLR, TCPR, TCR)
Modified Signal Definitions
Change Description
Change number Ground (GND) signals from
Area Change
Table 2-1,
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Modified Signal Definitions
Area Change
Figure 2-1, Replace with following:
Change Description
DSP56311
VCCP VCCQL VCCQH VCCA VCCD VCCC VCCH VCCS Power Inputs: Core Logic Address Data Control HI08 ESSI/SCI/Timer Grounds: General Interrupt/Mode Control
During Rese MODA MODB MODC MODD RESET
After Reset IRQA IRQB IRQC IRQD RESET Multiplexed HAD[0-7] HAS/HAS HA10 Double HRD/HRD HWR/HWR Double HTRQ/HTRQ HRRQ/HRRQ Port GPIO PC[0-2] Port GPIO PD[0-2] Port GPIO Timer GPIO TIO0 TIO1 TIO2 Port GPIO PB[0-7] PB10 PB13 PB11 PB12 PB14 PB15
Host Interface (HI08) Port1
Non-Multiplexed H[0-7] HCS/HCS Single HDS/HDS Single HREQ/HREQ HACK/HACK
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GNDP GNDP1 EXTAL XTAL PCAP CLKOUT4 After Reset
Clock
Enhanced Synchronous Serial Interface Port (ESSI0)2 Port External Address External Data External Control Enhanced Synchronous Serial Interface Port (ESSI1)2 Serial Communications Interface (SCI) Port2
During Reset PINIT
SC0[0-2] SCK0 SRD0 STD0 SC1[0-2] SCK1 SRD1 STD1 SCLK TIO0 TIO1 TIO2 TRST
A[0-17] D[0-23] AA[0-3]/ RAS[0-3]4 CAS4 BCLK4 BCLK4
Timers3
JTAG/OnCE Port
Notes:
HI08 port supports non-multiplexed multiplexed bus, single double Data Strobe (DS), single double Host Request (HR) configurations. Since each these modes configured independently, combination these modes possible. These HI08 signals also configured alternately GPIO signals (PB[0-15]). Signals with dual designations (for example, HAS/HAS) have configurable polarity. ESSI0, ESSI1, signals multiplexed: ESSI0 with Port GPIO signals (PC[0-5]), ESSI1 with Port GPIO signals (PD[0-5]), with Port GPIO signals (PE[0-2]). TIO[0-2] configured GPIO signals. These signals supported above MHz.
Figure 2-1. Signals Identified Functional Group
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Modified Signal Definitions
Area Change
Table 2-3, Replace with following:
Change Description
Table 2-3. Grounds
Ground Name
GNDP
Description
Ground- ground dedicated use. connection should provided with extremely low-impedance path ground. VCCP should bypassed GNDP 0.47 capacitor located close possible chip package. Ground ground dedicated use. connection should provided with extremely low-impedance path ground. Ground-Connected internal device ground plane. user must provide adequate external decoupling capacitors connections
Freescale Semiconductor, Inc.
GNDP1
Area Change
Section 2.3, Table 2-5,
Change Description
Delete note following Table Replace with following:
Table 2-5. Phase-Locked Loop Signals
Signal Name
PCAP
Type
Input
State During Reset
Input
Signal Description
Capacitor-An input connecting off-chip capacitor filter. Connect capacitor terminal PCAP other terminal VCCP. used, PCAP tied VCC, GND, left floating.
CLKOUT
Output
Chip-driven
Clock Output-Provides output clock synchronized internal core clock phase. enabled both multiplication division factors equal one, then CLKOUT also synchronized EXTAL. disabled, CLKOUT frequency half frequency EXTAL. Note: operating frequencies above MHz, this signal produces low-amplitude waveform that usable externally other devices. Above MHz, asynchronous arbitration option that enabled Asynchronous Arbitration Enable (ABE) Operating Mode Register. When set, enters Asynchronous Arbitration mode, which eliminates set-up hold time requirements with respect CLKOUT.
PINIT
Input
Input
Initial-During assertion RESET, value PINIT written into enable (PEN) control (PCTL) register, determining whether enabled disabled. Nonmaskable Interrupt-After RESET deassertion during normal instruction processing, this Schmitt-trigger input negative-edge-triggered request internally synchronized CLKOUT.
Input
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Modified Signal Definitions
Area Change
Table 2-8,
Change Description
Change title third column State During Reset, Stop, Wait. Change first table following:
AA[0-3]
Output
Tri-stated
Address Attribute-When defined these signals used chip selects additional address lines. default defines priority scheme under which only signal asserted time. Setting priority disable (APD) (Bit OMR, priority mechanism disabled lines used together four external lines that decoded externally into chip select signals. Address Strobe-When defined RAS, these signals used DRAM interface. These signals tri-statable outputs with programmable polarity. Note: DRAM access supported above MHz.
RAS[0-3]
Output
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Area Change
Table 2-8,
Change Description
Change Signal Description following: Transfer Acknowledge-If DSP56321 master there external activity, DSP56321 master, input ignored. input data transfer acknowledge (DTACK) function that extend external cycle indefinitely. number wait states .infinity) added wait states inserted control register (BCR) keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. current cycle completes clock period after deasserted. number wait states determined input BCR, whichever longer. sets minimum number wait states external cycles. order functionality, must programmed least wait state. zero wait state access cannot extended deassertion. operating frequencies MHz, operate synchronously (with respect CLKOUT) asynchronously depending setting Operating Mode Register (OMR). synchronous mode selected, user responsible ensuring that transitions occur synchronous CLKOUT ensure correct operation. Synchronous operation supported above OMR[TAS] must synchronize signal with internal clock. Change signal State During Reset, Stop, Wait Reset: Output (deasserted) State during Stop/Wait depends BCR[BRH] setting: Output, deasserted Maintains last state (that asserted, remains asserted) Change signal State during Reset, Stop, Wait Ignored input
Change signal following:
Column Address Strobe-When master, active-low output used DRAM strobe column address. Otherwise, Mastership Enable (BME) DRAM control register cleared, signal tri-stated. Note: DRAM access supported above MHz.
Output
Tri-stated
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Modified Signal Definitions
Area Change
Table 2-8,
Change Description
following rows table:
BCLK
Output
Tri-stated
Clock When master, BCLK active when Operating Mode Register set. When BCLK active synchronized CLKOUT internal PLL, BCLK precedes CLKOUT one-fourth clock cycle. Note: operating frequencies above MHz, this signal produces low-amplitude waveform that usable externally other devices.
BCLK
Output
Tri-stated
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Clock When master, BCLK inverse BCLK signal. Otherwise, signal tri-stated. Note: operating frequencies above MHz, this signal produces low-amplitude waveform that usable externally other devices.
Area Change
Table 2-10, 2-11 2-14
Change Description
Change title third column State During Reset1,2. notes that state: Note: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines have weak keepers that maintain last output state even drivers tri-stated. Wait processing state does affect signal state. Change State During Reset signals Ignored input. Change Signal Description PB14 Port B14-When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. Change title third column State During Reset1,2 Change State During Reset Stop signals Ignored input. notes that state: Note: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines have weak keepers that maintain last output state even drivers tri-stated. Wait processing state does affect signal state.
Table 2-11, 2-15 2-16 Table 2-12, 2-17 2-18 Table 2-13, 2-19 Table 2-14, 2-20
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Operating Mode Register (OMR) Layout Definition
Operating Mode Register (OMR) Layout Definition
Area Change
Figure 4-3, 4-11
Change Description
Replace with following figure:
Stack Control/Status (SCS)
Extended Operating Mode (EOM)
Chip Operating Mode (COM)
MSW[1-0] CDP[1-0]
Reset:
After reset, these bits reflect corresponding value mode input (that MODD, MODC, MODB, MODA, respectively). Reserved bit. Read zero; write zero future compatibility
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Figure 4-3. Operating Mode Register (OMR)
Area Change
Table 4-6, 4-11 4-14
Change Description
change contents following:
Address Trace Enable This valid operating frequency less. When conditions valid set, Address Trace Enable (ATE) enables Address Trace mode. Address Trace mode debugging tool that reflects internal memory accesses external address bus.
Area Change
Table 4-6, 4-11 4-14
Change Description
change contents following:
Synchronize Select Selects synchronization method input Port pin-TA (Transfer Acknowledge). operating frequencies MHz, operate synchronously (with respect CLKOUT) asynchronously depending setting Operating Mode Register (OMR). synchronous mode selected, user responsible ensuring that transitions occur synchronous CLKOUT ensure correct operation. Synchronous operation supported above MHz; when using OMR[TAS] must synchronize signal with internal clock.
Area Change
Table 4-6, 4-11 4-14
Change Description
change contents following:
Memory Switch Mode Allows some internal data memory both) become part chip internal Program RAM. Notes: ensure proper operation, place instructions after instruction that changes bit. ensure proper operation, while Instruction Cache enabled SR).
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Control Register (BCR)
Control Register (BCR)
Area Change
Chapter introduction, After Section 4.6, 4-21
Change Description
bullet after control register that lists control register. section, follows:
4.6a Control Register
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Control Register (BCR), depicted Figure 4-5a, read/write register that controls external activity Interface Unit (BIU) operation. bits except BBS, read/write bits. bits defined Table 4-8a.
BDFW4
BDFW3
BDFW2
BDFW1
BDFW0
BA3W2
BA3W1
BA3W0
BA2W2
BA2W1
BA2W0
BA1W4
BA1W3
BA1W2
BA1W1
BA1W0
BA0W4
BA0W3
BA0W2
BA0W1
BA0W0
Reserved bit. Read zero; write zero future compatibility
Figure 4-5a. Control Register (BCR)
Table 4-8a. Control Register (BCR) Definitions
Number
Name
Reset Value
Description
Request Hold Asserts signal, even external access needed. When set, signal always asserted. cleared, asserted only external access attempted pending. This reserved. State This read-only when master cleared otherwise. Default Area Wait State Control Defines number wait states (one through inserted into each external access area that defined registers. access type this area SRAM only. These bits should programmed zero since SRAM memory access requires least wait state. When four through seven wait states selected, additional wait state inserted access. When selecting eight more wait states, additional wait states inserted access. These trailing wait states increase data hold time memory release time increase memory access time.
20-16
BDFW[4-0]
11111 wait states)
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Control Register (BCR)
Table 4-8a. Control Register (BCR) Definitions (Continued)
Number
15-13
Name
BA3W[2-0]
Reset Value
wait states)
Description
Area Wait State Control Defines number wait states (1-7) inserted each external SRAM access Area Area area defined AAR3. program value these bits zero since SRAM memory access requires least wait state. When four through seven wait states selected, additional wait state inserted access. This trailing wait state increases data hold time memory release time does increase memory access time.
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12-10
BA2W[2-0]
wait states)
Area Wait State Control Defines number wait states (1-7) inserted into each external SRAM access Area Area area defined AAR2. program value these bits zero, since SRAM memory access requires least wait state. When four through seven wait states selected, additional wait state inserted access. This trailing wait state increases data hold time memory release time does increase memory access time.
BA1W[4-0]
11111 wait states)
Area Wait State Control Defines number wait states (1-31) inserted into each external SRAM access Area Area area defined AAR1. program value these bits zero, since SRAM memory access requires least wait state. When four through seven wait states selected, additional wait state inserted access. When selecting eight more wait states, additional wait states inserted access. These trailing wait states increase data hold time memory release time increase memory access time.
BA0W[4-0]
11111 wait states)
Area Wait State Control Defines number wait states (1-31) inserted each external SRAM access Area Area area defined AAR0. program value these bits zero, since SRAM memory access requires least wait state. When selecting four through seven wait states, additional wait state inserted access. When selecting eight more wait states, additional wait states inserted access. These trailing wait states increase data hold time memory release time increase memory access time.
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Peripheral Signal Designators
Peripheral Signal Designators
Area Change
Figure 5-2,
Change Description
Change H0-H7 H[0-7]. Change HAD0-HAD7 HAD[0-7]. Change HA0. Change HAS/HAS HAS/HAS. Change HA1. Change HA8. Change HA2. Change HA9. Change HCS/HCS HCS/HCS. Change HA10 HA10. Change HRW. Change HRD/HRD HRD/HRD Change HDS/HDS HDS/HDS Change HREQ/HREQ HREQ/HREQ Change HTRQ/HTRQ HTRQ/HTRQ Change HACK/HACK HACK/HACK Change HRRQ/HRRQ HRRQ/HRRQ
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Figure 5-5,
Change RXD, TXD, SCLK, PE0, PE1, RXD, TXD, SCLK, PE0, PE1, PE2, respectively.
Receive Register (SRX) Description
Area Change
Section 9.6.4.1, 9-24
Change Description
Change beginning fourth paragraph from Synchronous mode" Asynchronous mode".
Updated OMR, BCR, Timer Programming Sheets
Replace Figure B-2, Figure B-4, Figure B-24 DSP56311 User's Manual with following figures.
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Updated OMR, BCR, Timer Programming Sheets
Central Processor
Asynchronous Arbitration Enable, Synchronization disabled Synchronization enabled Address Attribute Priority Disable, Priority mechanism enabled Priority mechanism disabled Address Trace Enable, Address Trace mode disabled Address Trace mode enabled *valid less only Stack Extension Select, Mapped memory Mapped memory Stack Extension Underflow Flag, stack underflow Stack underflow Stack Extension Overflow Flag, stack overflow Stack overflow Stack Extension Wrap Flag, stack extension wrap Stack extension wrap (sticky bit) Stack Extension Enable, Stack extension disabled Stack extension enabled Memory Switch Configuration, Bits MSW[1 Program Memory Memory: $4000 $BFFF Memory: $4000 $BFFF Memory: $6000 $BFFF Memory: $6000 $BFFF Memory: $8000 $BFFF Memory: $8000 $BFFF Memory: $A000 $BFFF Memory: $A000 $BFFF Chip Operating Mode, Bits Refer operating modes table Chapter External Disable, Enables external Disables external
Stop Delay Mode, Delay 128K clock cycles Delay clock cycless Memory Switch Mode, Memory switching disabled Memory switching enabled Core-DMA Priority, Bits CPD[1:0] Description Compare SR[CP] active channel priority higher priority than core same priority core lower priority than core Cache Burst Mode Enable, Burst Mode disabled Burst Mode enabled Synchronize Select, synchronized Synchronized Release Timing, Fast Release mode Slow Release mode
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MSW1 MSW0 CPD1 CPD0
Operating Mode Register Reset $00030X; latched from levels Mode pins
Reserved, Program
Figure B-2. Operating Mode Register (OMR)
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Updated OMR, BCR, Timer Programming Sheets
Central Processor
NOTE: bits read/write control bits. State, master master Default Area Wait Control, Bits
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Area Wait Control, Bits Area Wait Control, Bits Area Wait Control, Bits Area Wait Control, Bits These read/write control bits define number wait states inserted into each external SRAM access designated area. value these bits should programmed zero. Number wait states: BDFW[20 BA3W[15 BA2W[12 BA1W[9 BA0W[4 Request Hold, asserted only attempted pending access always asserted
BDFWBDFW BDFWBDFWBDFWBA3W BA3W BA3WBA2W BA2W BA2W BA1W BA2WBA1W BA1WBA1W BA0W BA0W BA0WBA0W BA0W
Control Register (BCR) Reset $1FFFFF
Reserved, Program
Figure 4-2. Control Register (BCR)
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Updated OMR, BCR, Timer Programming Sheets
Timers
Timer Reload Value
Timer Load Register Reset $xxxxxx, value indeterminate
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TLR0-X:$FFFF8E Write Only TLR1-X:$FFFF8A Write Only TLR2-X:$FFFF86 Write Only
Value Compared Counter Value
Timer Compare Register Reset $xxxxxx, value indeterminate after reset
TCPR0-X:$FFFF8D Read/Write TCPR1-X:$FFFF89 Read/Write TCPR2-X:$FFFF85 Read/Write
Timer Count Value
Timer Count Register Reset $000000
TCR0-X:$FFFF8C Read Only TCR1-X:$FFFF88 Read Only TCR2-X:$FFFF84 Read Only
Figure B-24. Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
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Updated OMR, BCR, Timer Programming Sheets
Freescale Semiconductor, Inc.
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Updated OMR, BCR, Timer Programming Sheets
Freescale Semiconductor, Inc.
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Updated OMR, BCR, Timer Programming Sheets
Freescale Semiconductor, Inc.
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DSP56311UMAD/D
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