SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT SPEED CAN-TRANSCEIVER
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L4969
SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT SPEED CAN-TRANSCEIVER
OPERATING SUPPLY VOLTAGE 28V, TRANSIENT QUIESCENT CURRENT CONSUMPTION, LESS THAN 40µA SLEEP MODE VERY DROP VOLTAGE REGULATORS 200mA 5V/200mA SEPARATE VOLTAGE REGULATOR CAN-TRANSCEIVER SUPPLY WITH POWER SLEEP MODE EFFICIENT SUPERVISION RESET LOGIC SERIAL INTERFACE UNPOWERED INSUFFICIENTLY SUPPLIED NODE DOES DISTURB LINES VOLTAGE SENSE COMPARATOR SUPPORTS TRANSMISSION WITH GROUNDSHIFT: SINGLE WIRE: 1.5V, DIFFERENTIAL:
SO20
PowerSO20
ORDERING NUMBERS: L4969MD (SO20) L4969 (PowerSO20)
DESCRIPTION L4969 integrated circuit containing independent Voltage Regulators standard fault tolerant speed line interface multipower BCD3S process. integrates main local functions automotive body electronic applications connected bus.
Figure Block Diagram
VREG
VREG
Watchdog adjustable RC-Oscillator
NRESET
Identifier Filter VREG
WAKE CANH CANL Fault tolerant speed CAN-transceiver SCLK SOUT Control Status Memory NINT
October 2003
This preliminary information product development undergoing evaluation. Details subject change without notice.
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Figure Connection
CANH CANL
WAKE NINT NRES
SCLK NRES NINT WAKE
SOUT
PSO20
SCLK SOUT
SO20
CANL CANH
Table Functions
(PSO20) (SO20) 5,6, Name CANH CANL SOUT SCLK NRES NINT WAKE Power Ground Microcontroller Supply Voltage Peripheral Supply Voltage Internal Supply Power Supply CANH Line Driver Output CANL Termination Source CANL Line Driver Output CANH Termination Source Act. Receive Dominant Data Output Act. Transmit Dominant Data Input Serial Data Output Serial Data Input Serial Clock Act. Reset Output Act. Interrupt Request Dual Edge Triggerable Wakeup Input Function
Table Thermal Data
Symbol Rthj-amb Rthj-case Parameter Thermal resistance junction-ambient Thermal resistance junction-case Powerso20 401) SO20L Unit °C/W °C/W
Note: Typical value soldered board with copper ground plane thick).
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Table Absolute Maximum Ratings
Symbol VVSDC VVSTR IVOUT1.3 TSTG VOUT1 VOUT2 VOUT3 Vinli VinliW Vcanh Vcanl Parameter operating supply voltage Transient operating supply voltage 400ms) Output currents Storage temperature Operating junction temperature Externally forced output voltage OUT1 Externally forced output voltage OUT2 Externally forced output voltage OUT3 Input voltage Logic inputs: SIN, SCLK, NRES Input voltage WAKE Voltage CANH line Voltage CANL line Value -0.3 -0.3 Internally limited +150 +150 -0.3 VS+0.3, +6.3 -0.3 VS+0.3 -0.3 VS+0.3, +6.3 -0.3 -0.3 VS+0.3
Unit
Notes: pins protected against ESD. verification performed according 883C, human body model with 1.5kW, 100pF discharge voltage 2000V, corresponding maximum discharge energy 0.2mJ. Voltage forced means voltage limited specified values while current limited. Pulses CAN-Pins with other Pins grounded.
Table Electrical Characteristics 14V, -40°C 150°C unless otherwise specified.
Symbol Supply Current ISSL ISSLWK ISSB Regulators (CANH Standby off, off, (CAN only) only (CAN Standby) Timer (Sleep Timer (Sleep RXonly Timer (Standby Timer (Standby Default (Standby Regulators (CAN active, high) Additional Oscillator- Chargepumpcurrent IOUT1 -100mA IOUT2 -10mA load. Timer Timer >-100mA SO20 Package >-150mA PSO20 Package VDP1 Dropout voltage VS=4.8V IOUT1 -10mA IOUT1 -100mA SO20 Package IOUT1 -150mA PSO20 Package Parameter Test Conditions Min. Typ. Max. Unit
ISCP
Voltage Regulator output voltage
0.025 0.25
0.06
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Table Electrical Characteristics (continued) 14V, -40°C 150°C unless otherwise specified.
Symbol VOL01 Parameter Load regulation Test Conditions =-1mA to-100mA SO20 Package =-1mA -150mA PSO20 Package ILIM1 Current limit 0.8V 4.5V, VS=6V, SO20 Package 0.8V 4.5V VS=14V, PSO20 Package VOLI1 TOVT1 TOTKL1 Vres Line regulation Overtemp flag Thermal shutdown -1mA RTC0 Voltage Regulator Output voltage >-100mA SO20 Package >-150mA PSO20 Package Dropout voltage 4.8V IOUT 100mA SO20 Package IOUT 150mA PSO20 Package VOLO Load regulation =-1mA -100mA SO20 Package =-1mA -150mA PSO20 Package ILIM Current limit 0.8V 4.5V, VS=6V, SO20 Package 0.8V 4.5V PSO20 Package VOLI TOVT TOTKL Vtrc tOSC tWDC tRDnom tWDstart Line regulation Overtemp flag Thermal shutdown tracking offset OnChip RC-Timebase Watchdog timebase (2.5ms) Reset pulse duration (1ms) Reset pulse pause (320ms) (startup watchdog) IOUT -5mA 28V, RC-Adjustment Min. -180 -180 Typ. -400 -400 Max. -800 -800 Unit
4.15
reset threshold voltage RTC0
0.25
-180 -180 0.95
-400 -400 2498 1024
-800 -800 1.35
tOSC tOSC tWDC
Reset Watchdog
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Table Electrical Characteristics (continued) 14V, -40°C 150°C unless otherwise specified.
Symbol tWDswS Parameter Watchdog window start (Software window Watchdog) Test Conditions (2.5ms) (5ms) (10ms) (20ms) tWDswE Watchdog window (Software window watchdog) (5ms) (10ms) (20ms) (40ms) tWD1C System Watchdog (80ms) (160ms) (320ms) (640ms) (800ms) tWD2C System Watchdog (1s) (2s) (4s) (8s) (45min) VRESL RPURES Reset output voltage Internal Reset Pull-Up Resistance Propagation delay (rec state) Propagation delay (dom state) output slew rate Cload 3.3nF Cload 3.3nF, RTERM =100 CLoad 3.3nF IRES 500u, 2.5V IRES 500u, 1.5V Min. Typ. 1600 3200 1081344 0.85 Max. Unit tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC tWDC
Line Interface tdrd tddr
V/µs
RRTH, RRTL external Termination resistance (application limit) VCCFS VHRXD VLRXD Vd_r Force Standby mode (fail safe) High level output voltage level output voltage Differential receiver threshold VCANH VCANL Differential receiver threshold VCANH VCANL failures turn CAN-IF
2.20 -3.85
-2.50
Vr_d
failures
-3.50
-2.20
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Table Electrical Characteristics (continued) 14V, -40°C 150°C unless otherwise specified.
Symbol VCANHr VCANHd VCANLr VCANLd ICANH ICANL ILCANH ILCANL VWakeH VWakeL Vcanhs Vcanls VOVH VOVL RTRTH Parameter CANH recessive output voltage CANH dominant output voltage CANL recessive output voltage CANL dominant output voltage CANH dominant output current CANL dominant output current CANH Sleep mode leakage current CANL Sleep mode leakage current CANH wakeup voltage CANL wakeup voltage CANH single ended receiver threshold CANL single ended receiver threshold CANH overvoltage detection threshold CANL overvoltage detection threshold internal termination resistance Normal mode, failures. internal termination current Normal mode, Failure EIII internal termination resistance Normal mode, failures. internal termination current Normal mode. (failure EIV, EVI, EVII) internal termination resistance failures. level input voltage High level input voltage level input voltage High level input voltage Test Conditions RRTH ICANH 40mA RRTL ICANL -40mA VCANH VCANL Sleep mode. 130°C VCANH Sleep mode. 130°C VCANL Sleep/ standby mode Sleep/ standby mode Normal mode. CANL Normal mode. CANH< Normal mode. CANL Normal mode. CANH VRTH -160 -100 1.82 1.4V 0.2V 2.15 Min. Typ. Max. 0.35 Unit
ITRTHF
VRTH
RTRTL
VRTL
ITRTLF
VRTL
RTRTLS
Standby/sleep mode. VRTL
13.0
Digital VSINL VSINH VSCLKL VSCLKH
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Table Electrical Characteristics (continued) 14V, -40°C 150°C unless otherwise specified.
Symbol VTXL VTXH VWakeL VWakeH VSoutH VSoutL VRXDH VRXDL IohRXD IolRXD IohSOUT IolSOUT IohINT IolINT IohReset IolReset IohWake IolWake tStart Parameter level input voltage High level input voltage level input voltage High level input voltage High level output voltage level output voltage High level output voltage level output voltage High level output current level output current High level output current level output current High level output current level output current High level output current level output current High level output current level output current SCLK setup time (frame start) SCLK setup time (write) SCLK hold time (write) SCLK SOUT delay time (read) SCLK maximum cycle time (timeout) Interframe SCLK frequency range Sense comparator detection threshold CANH groundshift detection threshold edges CANL detect permanent CANH edges detect recovery CANH Operating mode (EI_V) 0.25 -1.5 -0.6 SOUT SOUT RESET RESET VWake VWake Test Conditions Min. -2.5 -1.5 -4.5 -1.8 -14.0 24,0 -15.0 24,0 -15,0 -3.4 Typ. Max. -0.9 +1.5 -2.0 Unit
Serial Data Interface
tSetup tHold tCKmax tGAP fSCLK VSmin GSCANH
Diagnostic Functions
Error Detection NEdgeH Edges
NEdgeHR
Operating mode (EI_V)
Edges
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Table Electrical Characteristics (continued) 14V, -40°C 150°C unless otherwise specified.
Symbol NEdgeL Parameter edges CANH detect permanent CANL edges detect recovery CANL CANH short circuit detection time CANH short circuit recovery time CANL short circuit detection time CANL short circuit recovery time CANL short circuit detection time CANL short circuit recovery time CANL CANH short circuit detection time CANL CANH short circuit recovery time CANH short circuit detection time CANH short circuit recovery time permanent dominant detection time (Fail safe) permanent dominant recovery time (Fail safe) Minimum dominant time wake-up CANH CANL Minimum pulse time wakeup WAKE Test Conditions Operating mode (EII_IX) Min. Typ. Max. Unit Edges
NEdgeLR
Operating mode (EII_IX)
Edges
tEIII
Operating mode (EIII) Sleep/ standby mode (EIII) Operating mode (EIII) Sleep/ standby mode (EIII) Operating mode (EIV) Sleep/ standby mode (EIV) Operating mode (EIV) Sleep/ standby mode (EIV) Operating mode (EVI) Operating mode (EVI) Operating mode (EVII) Operating mode (EVII) Operating mode (EVIII) Sleep/ standby mode (EVIII) Operating mode (EVIII) Sleep/ standby mode (EVIII) Operating mode (EX) Operating mode (EX)
tEIIIR
tEIV
tEIVR
tEVI tEVIR tEVII tEVIIR tEVIII
tEVIIIR
tFailTX tFailTXR Wakeup twuCAN twuWK
sleep/standby sleep/standby
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FUNCTIONAL DESCRIPTION
General Features L4969 monolithic integrated circuit which provides main functions automotive body network. features independent regulated voltage supplies interrupt reset logic with internal clock generator, Serial Interface speed CAN-bus transceiver which supplied separate third voltage regulator (V3). device guarantees clearly defined behavior case failure, avoid permanent errors. device operates four basic modes, with additional programming Standbymodes CTCR:
Mode Sleep Sleep Timer/WDC (250KHz) (250KHz) (1MHz) (1MHz) (1MHz) CAN-IF Standby Standby Standby Standby Standby RX-Only Normal Ityp 170u 210u 440u LP1, (CTCR) Remarks Timer based wakeup Timer active Watchdog Timer Watchdog timer active Watchdog timer activ, default Active during Busactivity filter automatic fall back Sleep when idle Currents from Regulators
Standby #1(*1) Standby #2(*1) Standby RXOnly Normal
(*1) Note, that order enter either Standby Standby Startup-Watchdog acknowledged (see Chapter 1.2), Standby Window Watchdog disabled described Chapter 2.5, allow decativation internal oscillator.
1.1.1 Output Voltage regulator uses DMOS transistor output stage. With this structure very dropout voltage obtained. dropout operation standby regulator maintained down input supply voltage. output voltage regulated transient input supply voltage 40V. With this feature functional interruption overvoltage pulses generated. output regulator switched sleep mode. 1.1.2 Output Voltage regulator uses same output structure output regulator except being short circuit proof rated output current 200mA. output switched through dedicated enable control register. addition tracking option enabled allow follow with constant offset. This feature allows consistent conversion inside (supplied when converted signals referenced maximum voltage that applied 0.3V 40V. 1.1.3 Output Voltage third voltage regulator device generates supply voltage internal logic CAN-transceiver. operating mode capable supplying 200mA order guarantee required short circuit current CAN_H driver. sleep operating modes switched through dedicated enable bit. 1.1.4 Internal Supply Voltage power sleep mode regulator supplies internal logic sleep mode.
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Power-Up, Initialization Sleep mode transitions following state-diagram illustrates possible mode transitions inside device. prerequisite, SPI-connection with correct CRC-algorythms required. During debug phase NRES line forced high externally (connect deactivate startup failure mechanis keeping will alive.
After POR, externally forced reset through NRES, STARTUP STATE entered forced sleep mode left upon wakeup through either edge WAKE. Applying permanent wakeup (i.e. both CAN-lines dominant) prevents from being turned (can used during System debugging)
NRES WAKEUP STARTUP active WDC-ACK
WAKEUP
Forcing NRES high externally, fail will incremented (Emulation)
t=320ms t=1ms
STARTUP FAILURE RESET (fail
fail
FORCED SLEEP Reset
missing within 320ms will initiate STARTUP FAILURE phase (RESET low).
WDC-FAIL
Dependig value from last WDC-ACK, another written within specified time frame (SWDC[1:0]). failure will activate STARTUP STATE
WDC-ACK WDEN
WDC-ACK received within seven retrials voltage regulator will turned entering FORCED SLEEP state.
Writing WDCregister (WDC-ACK) NORMAL STATE entered.
Window supervision temporarily deactivated time programmed during last WDC-ACK (WDT[3:0]). Upon rewriting (WDC-ACK) expiry timer, NORMAL STATE reentered.
NORMAL MODE WDC-ACK WINDOW t=tWIN2 WDC-OK ACTIVE
WINDOW WATCHDOG REFRESH
WDEN
TIMER ACTIVE (restart double WDC-ACK WDEN)
DISAR
TIMEOUT WDC-ACK
during last WDC-ACK been (after releasing write lock, description Watchdog Control Register) Window watchdog deactivated, supervision active. Here timer used generate time events (i.e. wakeup from stop)
NORMAL MODE WINDOW DISABLED WAKEUP DISAR
WDEN TIMEOUT WDC-ACK
TIMER ACTIVE (restart double WDC-ACK WDEN)
WAKEUP &V1_UV
Programmed SLEEP Reset
Setting DISAR (see Voltage Regulator Control Register) Voltage regulator turned off, output voltage decreasing depending external load blocking capacitor. Note, that during this transition Reset will generated (due Debugmode). Upon wakeup howewer NRES will pulled low, V1was below programmable reset threshold (V1_UV).
WAKEUP&V1_UV
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Transceiver
Supports double wire unshielded busses Baud rate 125KBaud Short circuit protection (battery, ground, wires shorted) Single wire operation possible (automatic switching single wire upon failures) loaded case unpowered transceiver transceiver stage able transfer serial data independent communication wires either deferentially (normal operation) case single wire fault remaining line. physical bitcoding done using dominant (transmitter active) overwritable recessive states. long dominant phases detected internally further transmission automatically disabled (malfunction protocol unit does affect communication bus, "fail-safe" mechanism). current consumption during inactivity sleep mode available. operating mode entered from sleep mode either local wake (µC) upon detection dominant CAN-bus (external wake up). different errors physical buslines distinguished: 1.3.1 Detectable Physical Busline Failures
Type Errors Conditions
Errors caused damage datalines isolation CANH wire interrupted (tied Ground termination) CANL wire interrupted (floating tied termination) CANH short circuit VBAT (overvoltage condition) CANL short circuit (permanently dominant) CANH short circuit (permanently recessive) CANL short circuit VBAT (overvoltage condition) CANL shorted CANH Edgecount difference Edgecount difference V(CANH) 7.2V after 32us V(CANL) 3.1V V(CANH)-V(CANL) -3.25V after 1.3ms Edgecount difference V(CANL) 7.2V after 32us V(CANH) V(CANL) -3.25V after 1.3ms
Errors caused misbehavior transceiver stage VIII CANH short circuit (permanently dominant) CANL short circuit (permanently recessive) V(CANH) 1.8V V(CANH) V(CANL) -3.25V after 2.5ms Edgecount difference
Errors caused defective protocol unit CANH, CANL driven dominant more than 1.3ms
different errors lead breakdown whole communication. errors categorized into 'negligible', 'problematic' 'severe':
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1.3.2 Negligible Errors 1.3.2.1 Transmitter Error (CANH CANL interrupted still tied termination) Error VIII (CANH CANL permanently dominant short circuit) cases above data still transmitted differential mode. 1.3.2.2 Receiver Error (CANH CANL interrupted still tied termination) Error (CANH CANL permanently recessive short circuit) cases above data still received differential mode. 1.3.3 Problematic Errors
1.3.3.1 Transmitter Error (CANH CANL show overvoltage condition short circuit) Data transmitted using remaining dataline (single wire) 1.3.3.2 Receiver Error (CANH CANL show overvoltage condition short circuit) Data received using remaining dataline (single wire) 1.3.4 Severe Errors 1.3.4.1 Transmitter Error (CANH CANL permanently recessive short circuit) Data transmitted remaining dataline after short circuit detection Error (CANH shorted CANL) Data transmitted CANH CANL after overcurrent detected Error (attempt transmit more than successive dominant bits lowest bitrate specified) Transmission terminated (fail safe) 1.3.4.2 Receiver Error (CANH shorted CANL) Data received CANH CANL after detection permanent dominant state Error VIII (CANH CANL permanently dominant short circuit) Data received CANH CANL after short circuit detected Error (reception sequence dominant bits, violating protocol rules) Data received normally, error detected protocol-unit error conditions signaled issuing error flag inside dedicated register which readable through serial interface. information error type through also stored into this register.
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Oscillator power oscillator provides internal clock. sleep mode (Watchdog active) output frequency 250kHz, Watchdog function requested, internal Oscillator switched off. standby operating mode oscillator running 1MHz, calibrated range from -16% +16% using µC-XTAL reference. WatchdL4969og triple function programmable watchdog integrated perform following tasks: Wakeup Watchdog: When sleep standby mode watchdog generate wakeup condition after programmable period time ranging from 80ms minutes Startup Watchdog: Upon power-up failure during supervision (see SW-Watchdog) reset pulse generated periodically every 320ms 2.5ms until activity detected (SPI sequence) acknowledge received within cycles (2.2sec). this condition device forced into Sleep mode until Wakeup detected startup cycle reinitialized. Window Watchdog: After passing startup sequence, this watchdog request acknowledge within programmable timing frame, ranging from 40ms. Upon missing misplaced acknowledge Startup Watchdog initialized. Reset
1.6.1 Power-on Reset Upon Power-on 3.5V), internal reset forces device into predefined power-on state (see 1.1): Standby #3:V1 off,CAN-Standby mode, ID-Filter disabled, Startup Watchdog active With below regulator will follow with minimum drop. retrieves reset dropping below programmable voltage level either 4.5V (default) 4.0V. programmed state L4969 remains unchanged. act. Resetpulse duration fixed internally open-drain output stage 1ms. However, this time externally extended additional capacitance connect between NRESET GROUND which then charged internal pull-up typ. 120K. Depending Reset-Input-Threshold (UTR), reqired Capacitance typical calculated follows: CEXT (120E3 ln(1-UTR/V1)). obtain reset-pulse duration 50ms with UTR/V1 0.5, Capacitance CEXT= -50E-3 (120E3 0.5) 600nF required.
120K NRES
Reset Input
CEXT
1.6.2 Undervoltage Reset Upon detection voltage level below programmable voltage level either 4.5V (default) 4.0V,the NRES-pin pulled low. Since this undervoltage detection additionally sampled periodically every NRES time will extended sampling point (see below). sampling V1UV NRES
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1.6.3 Reset signalling during Sleepmode When entering sleep mode writing DISAR VRCR register, Voltageregulators their references will deactivated allow minimum current consumption. removing reference, outputvoltage longer supervised thus reset will generated. scenarios possible (see statediagram chapter 1.2): Wakeup with still above reset threshold: will reactivated Normal mode resumed Wakeup with below reset threshold: will activated, NRES will remain until above reset threshold Startup mode entered. scenario most critical when used with that have their circuitry. this case will ramp down with unknown application state. guarantee proper shut without internal circuitry following mechanism utilized: L4969 uses bidirectional Reset detect possible Watchdog failure this failure condition detected, NRES will forced (with activated timer) until wakeup condition occurs (WDEN register reset, thus RC-oscillator will switched during sleep). methods used allow proper sleep transition: With Timer (WDEN=1): immediately after setting DISAR program generate failure causing L4969 detect level NRES followed automatic pulse extension. ramping down slow, Cext defined way, that NRES will stay below input threshold until safe level. Without timer (WDEN=0): same procedure above, generate Reset within after WDEN been cleared. NRES will then stay low, until wakeup condition occurs.
DISAR
NRES
RC-Osc
CEXT
L4969
Identifier Filter 12-Bit CAN-ID-filter implemented allowing wakeup specific CAN-messages thus aiding implementation power partial communication networks like standby diagnostics without need power-up whole network. guarantee detection programmed Identifiers, local RC-oscillator calibrated allow programmable Bittime logic extract incoming stream with maximum tolerance over temperature deviation. Ground Shift Detection case single wire communication CANH signal noise ratio low. Detecting local ground shift used additional indicator current signal quality. information integrated ground shift detector will refreshed upon every falling edge read from Transceiver Status Register (CTSR). will set, V(CANH) -1V, reset V(CANH -1V) falling edge
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Thermal Protection device features three independent thermal warning circuits which monitor temperature output, output CAN_H CAN_L drivers together with voltage regulator Each circuit sets separate overtemperature flag register which read writable serial interface. overtemperature flags cause interrupt able switch drivers through dedicated enable registers. enhance system security following strategy chosen thermal warning shutdown: independent warning flags 140°C /CAN-Transceiver 170°C switched 200°C switched switched again through switched again wake-up (Watchdog wake-up, wake-up, external wake-up) Note, that wakeup source 1sec watchdog timeout will established enable proper retry cycle. 1.10 Serial Interface (SPI) standard serial peripheral interface (SPI) implemented allow access internal registers L4969. total Registers with different datalengths directly read from written providing requested address beginning dataframe. Upon every access this interface, content register currently accessed shifted SOUT. operations performed rising edge SCLK. frame completed, interface automatically reset after 1.5ms SCLK idle time (auto timeout detection). message corrupted (additional missing SCLK pulses), application software detect this evaluating returned value force communication 1.5ms allow communicvation recovery. corruption caused during startup initialization. application should then wait least 1.5ms after init prior starting communication. dataframe format used described next page: 1.10.1General Dataframe Format:
ADR/CMD
Datafield (W/R)
Datafield 2/CRC (W/R)
SOUT
ADR/CMD
Datafield
Datafield 2/CRC
SCLK
99AT0015
Data sampled rising edge clock SOUT will change upon SCLK falling. SOUT will show copy Address/Command field initial data path checks. Independent command state, SOUT will show content register addressed. contains either data written arbitrary data other operations. transaction will terminated with four data followed 4-Bit wide (Cyclic Redundancy Check) result either related data calculated automatically data returned SOUT. Here provide correct sequence order write command activated inside. CRC-failure signalled NINT. returned data also used verify successful transfer.
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1.10.2 Address/Command Field ADR3 ADR2 ADR1 ADR0
Frame start sequence always transmitted
Addressfield specifying Control/Status word accessed
command: Read register Clear illegal command Write register
Address/Command field starts with 2-Bit start sequence consisting `01'. other sequence will lead protocol error signalled NINT. addressfield specifying register accessed. command flags allow addition normal read/write operation clear Interrupt flag register after read.
1.10.3 Datafield
Lower data SIN: Data write SOUT: Data currently selected register
99AT0017
Datafield contains either lower bits 12-Bit frame complete byte 8-Bit transfer. Note, that SOUT always showing content register currently accessed copy during Address/ Command field.
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1.10.4 Datafield /CRC
CRC3
CRC2
CRC1
CRC0
Upper data (Zero data)
SIN: Data write SOUT: Data currently selected register
99AT0018
Check sequence appended tranferred data Note that upon check failure write operation will performed SIN: sequence SOUT: SOUT sequence
Datafield contains either upper four bits 12-Bit frame zeros case 8-Bit transfer. This field followed four sequence that calculated based upon polynom 0x11h decimal). This sequence simply remainder polynomial division performed data previously transferred. appended sequence fails, writing will disabled error signalled NINT. Another remainder calculated SOUT stream appended accordingly allow application software validate correctness incoming data. evaluation, checking turned writing arbitrary data with valid address CRC-checking will reenabled upon another operation this kind (Toggled information).
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1.11 Memory Table
L4969 Memory
EUV3 Undefined Register Memory WDEN ISET ESPI PS23 ISET PS22 IRES PS21 UV23 PS20 UVVS PS13 EUV2 TXEN IRES OVT3 EVIII PS12 RTC0 PGEN SWT1 OVT2 EVII PS11 SIGN SWT0 EOVT OVT1 PS10 ADJ3 ENV3 ADJ2 EIII ENV2 TMUX ADJ1 WDT1 DISAR ADJ0 WDT0 EIFW WKIF
Group VRCR CTCR GPTR RCADJ GIEN CTSR ID01 ID23 TEST
WDT3 WDT2
Undefined Register Memory NCRC STAT WNDF WAKE NPOR
Undefined Register Memory
memory space divided into different registers each being directly accessible using SPI. Each register contains specific information functional group. general reserved bitpositions (`RES') have written with `0'. Undefined bits read cannot overwritten. addition there register (CTSR) being read only, thus write attempt will leave register content unchanged. Certain interlock mechanism exist prevent unwanted overwriting important functions i.e. voltage regulators oscillator adjustments. These mechanisms described with functions these registers.
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CONTROL STATUS REGISTERS functionality device observed controlled through registers which read writable serial interface. VRCR Voltage Regulator Control Register EUV3 EUV2 RTC0 ENV3 ENV2 DISAR
Enable undervoltage detection Regulator (see note below) reset threshold value 4.0V Default value (4.5V)
written `0'.
Disable Regulators Sleep) Note, that least Wakeup Source without pending wakeup required enable access. This will automatically upon system failures Overtemperature watchdog startup failure. Note, that reset will generated from during Sleep mode transition Reset line forced externally, through window failure DISAR will cleared upon valid wakeup signal which either defined GIEN forced WAKE after system failure Enable Regulator Default value (disabled) This will automatically reset upon Overtemperature Regulator
Enable Regulator tracking option have following with constant offset Default value (disabled) Enable Regulator will activated either setting ENV3 upon enabling Lineinterface Default value (disabled) This will automatically reset upon Overtemperature from CANIF Regulator
DISAR
Note, that large initial charging current output capacitors, activation within same command recommended also leaving ENV2 ENV3 when setting DISAR therefor recommended (after wakeup would turned DISAR ENV2 (DISAR ENV3 ACT) TSDV3
will activated upon VRCR.ENV3 CCTR.ACT without pending thermal shutdown
Note, that when using Undervoltage-detection, EUV2 EUV3 have activated AFTER have been turned settled 1ms). Otherwise unwanted undervoltage detectected during turn corresponding voltage regulator.
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CTCR CAN-Transceiver Control Register TXEN
Standby-mode control only, 1.1)
CAN-Transceiver application control Standby Sleep
enable Auto-Osc-Off reduce Osc-frequency 250KHz
Receive only mode (Readback Normal Operation Note, that TXEN automatically reset upon occurence permanent dominant) reprogrammed after problem correction enter normal mode.
Reserved bits (`RES') have written `0'.
Three basic operating modes available using different logic combinations TXEN. Each these modes conjunction with other inputs unique combination parameters inside specification: Table Operating Modes Lineinterface
Input Signals TXEN VDD*1 VS*1 CANL*1 VS*1 GND*1 CANH*1 CANH CANL Mode Standby RXonly RXonly RXonly Normal Normal Normal Normal Error Error VII, VIII Error EIII, VII, VIII Error EI_V Error EII_IX Error Error EVII, Error EVII VBAT ISRC ISRC ISRC ISRC ISRC Output Signals CANH CANL CANH CANH CANH CANL CANL
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GPTR Global Parameter Test Register
TMUX
This register used testpurpose only, bits have remain `zero' RCADJ RC-Oscillator Adjust register
PGEN ADJ4 ADJ3 ADJ2 ADJ1
ADJ0
+16%
Program enable (read only) will after 'Finish cycle measurement', reset after register write
Oscillator Frequency Adjust default value 10000 Note, that programming only enabled with PGEN
Test cycle request pulse NINT fixed period time requested XTAL synchronization 99AT0022
request (Adjustment disabled) 2.5ms cycle NINT (repetitive) Finish cycle measurement request (Adjustment disabled)
During normal operation `01' force 200Hz rectangular waveform NINT with duty cycle. Note, that other pending interrupts have cleared before. After XTAL driven timer calculated relative cycle time corresponding deviation, have `10' disable adjustment cycle NINT. From deviation calculated correction factor RC-oscillator -15% reprogrammed with `00' `11'. (`11' used indicate that calibration already been performed). Note, that overwriting this register only valid, cycle measurement started terminated properly. This tested evaluating PGEN either prior during correction (Read back SOUT). Note also, that write register will reset timer thus reset phase testcycle. Therefore cyclic access window watchdog during pulsewidth measurement avoided timer watchdog used instead (i.e. 1sec)
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State transition during oscillator calibration
Request"
CG=01 "2.5ms cycle CG=10 CG=00 "Finish Cycle" "Update ADJ" NINT" CG=11 Start time measurement rising edge Calculate Write offset Offset Watchdog Interrupt enabled
Watchdog Interrupt disabled
ADR4: Watchdog Control Register
WDEN SWT1 SWT0 WDT3 WDT2 WDT1 WDT0
Disable Window Watchdog, only allowed with PGEN set, previous table adjust
Enable Wakeup Watchdog, Window Watchdog will automatically deactivated until wakeup watchdog expires
Software Window Watchdog timing configuration 10ms 20ms 40ms
Reserved bits (`RES') have written `0'.
Wakeup Watchdog timing configuration 0000 80ms 0001 160ms 0010 320ms 0011 640ms 0100 800ms 1000 1sec 1001 2sec 1010 4sec 1011 8sec 1100 45min
Startup Watchdog programmable will always generate 1.0ms cycle NRESET followed 320ms high cycle until Acknowledgment will occur. Acknowldege received after cycle, device will automatically forced into Sleep mode. Acknowledgment Reset Startup Window Watchdog automatically performed overwriting rewriting) this register. Note, that with WDEN set, cyclic setting IFR.WKW after programmed Wakeup time will occur. 2.5.1 Watchdog configuration:
NRESET forced externally Wakeup Prog Sleep ExtWake CAN-Wake Startup missing Forced (after 350ms) Sleep missing
Timeout Window Wakeup WDEN Timer
Note: writing this address, will restart timer
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L4969
After power-on-reset wakeup from Sleep NRESET being forced externally, Startup Watchdog active, supervising proper startup supplied Upon missing write operation register after reset cycles (1ms active, 320ms high) Sleep mode entered. Leaving forced Sleep mode will automatically performed upon wakeup CAN, edge WAKE upon device powerup. After successful startup, Window Watchdog supervision activated, meaning, that send acknowledge within predefined, programmable window. Upon failure, reset generated Startup Watchdog reactivated. Timer function requested, window watchdog deactivated until expiry wakeup time, rewriting this register. Note, that write this register will reset timer. 2.5.2 Startup
NRESET Startup Acknowledgement within 320ms NRESET Startup Acknowledgement within 640ms NRESET Startup Acknowledgement within 2.3s (Device will enter Sleep mode)
After powerup, L4969 expecting send acknowledgement within predefined segmented timing frame 320ms. missing acknowledgement until after 2.3s will force device into sleep mode until either external wakeup cause restart sequence above. 2.5.3 Window Watchdog
20ms Early (late) Acknowlede supervision 40ms Early (late) Acknowlede supervision Acknowledge restarting Window
After successful acknowledgement Startup sequence, Window watchdog automatically activated controlling proper activity supervising incoming acknowledge within predefined programmable window. Upon every acknowledge watchdog restarting window.
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L4969
2.5.4 Wakeup Watchdog
Window Timer (80ms 45min) Window
Window Start Timer NINT
restart timer time writing twice
Timeout resume Window
Interrupt active upon timeout (via GIEN)
Timer activated during Normal mode setting WDEN WDC, "acknowledge-free" sequence started predefied programmable time. Window Watchdog activity resumed after expiry timer. able detect timeout, corresponding interrupt enable must GIEN. This mode also used allow bootstrap loader mode with longer execution times than maximum specified window. Correct startup this loader safely detected upon missing response following timeout. timer always restarted rewriting WDEN twice with timing.
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L4969
ADR5: GIEN Global Interrupt Enable Register
ISET IRES EOVT
EIFW
Enable Interrupt upon error detection Enable wakeup Interrupt Enable Interrupt upon error recovery Enable Interrupt upon VREG Undervoltage
Enable Identifier based wakeup Interrupt Enable Wakeup,/ Interrupt Watchdog
Enable Wakeup Interrupt edge WAKE Enable Interrupt upon Overtemp. Warning
ADR6: Interrupt Flag Register
ESPI ISET IRES UV23 UVVS OVT3 OVT2 OVT1
WKIF
Linefailure detected (ISET) removed (IRES)
7.2V detected Undervoltage
Signal edge WAKE detected Wakeup condition detected Watchdog timeout detected Identifier passed ID-Filter
CRC- Format Error SCLKTimeout detected (non maskable)
Overtemperature Warning level reached OVT1 T(V1) 140degC OVT2 T(V2) 140degC OVT3 T(V3) 140degC
Reserved (`RES') written `0'.
Except ESPI bits this register maskable GIEN. masked will force NINT until register content reset (either explicitly `clear register).
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L4969
ADR7: CTSR Transceiver Status Register
EVIII EVII EIII EII_IX
EI_V
CANH falling edge permanent dominant detected CANH permanent dominant detected
CANL short circuit detected
CANL permanent dominant detected
Single wire communication detected (edge count difference EI_V CANH EII_IX CANL
Short circuit CANH CANL detected
CANH short circuit detected
Reserved bits (`RES') always read
Note, that this register read only only provides unlatched information current buserrors.
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L4969
ID01, ID23 Identifier Filter Sequence Select Register
SEGA ID10 Demux
SEGB
SEGC
SEGD
SEGE
SEGF
Demux
99AT0028
PASS
Identifier Frame divided into segments numbered from `F'. each segment filter register implemented, enabling different pass functions every wide block. Segments through (ID01) located with `C11' Segments through (ID23) located with `F11' Note, that clearing complete segment disables whole filter.
SEGE SEGD SEGF Examples: Identifiers pass:
SEGA SEGC SEGB
Valid sequence each segment SEGA: A10, SEGB: SEGC: C01, SEGD: D10, SEGE: E11, E01, SEGF: F10,
bits 0101 0010 ID01: 0011 0010 0101 0011 0110 1011 ID01: 0110 1011 0110 0011
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L4969
2.10 Identifier Filter Bittimelogic Control Register
PS23 PS22 PS21 PS13 PS12 PS11 PS10
Phasesegment length configuration tPSEG2 PSEG2
Phasesegment length configuration tPSEG1 PSEG1)
Dominant Rezessive bitlength difference control
tdom trez
Bittime synchronization mechanism
tPSEG1 Sample Point
99AT0030
tPSEG2
total bitlength equals PSEG1 PSEG2 units location sampling point determined length PSEG1. start frame (initial recessive dominant edge) bitlength counter reset. Upon every signal edge counter will lengthened shortened according location transition within programmed boundaries PSEG1 PSEG2. edge lies within PSEG1 additional cycles inserted order shift sampling point safe location after settling input signal. signal transition located within PSEG2, this segment will shortened accordingly with goal next edge beginning PSEG1. amount cycles segment lengthened shortened determined type edge (rec rec) programming resynchronization jump width will either (dom edge) (rec edge). Note, that length timequanta depends offset chip RC-oscillator therefore accuracy calibration (see register RCADJ (ADR details frequency correction)
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L4969
2.11 System Status Register
NCRC STAT WNDF WAKE
NPOR
CRC-Checking disabled Reserved status flag (test only) Warm start after failure Window watchdog
Cold Start after Warm start after leaving prog. Sleep mode
Warm start after Overtemp failure
Warm start after missing during Startup
Warm start after missing during Startup
lower this register used analyze reason startup (after NRESET low). This information valid until first Watchdog-Acknowldge, will then reinitialized 000001.
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L4969
INTERRUPT MANAGEMENT
ESPI ISET IRES UV23 UVVS
OVT3 OVT2 OVT1
WKIF
ISET
IRES
EOVT
EIFW
GIEN
NINT
Interrupt flags IFR) except ESPI masked global interrupt enable register (GIEN). Interrupt will signalled NINT going until either corresponding mask flag itself will reset application software. autoreset function available IFR, allowing remove interrupt flags after reading their state (see SPI).
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L4969
REMARKS APPLICATION General circuit connection diagram
Thermal Supervision
Standby Supply Adjustable RC-Oscillator 120K Programmable Timer NRES
Peripheral Supply
NINT Wakeup Interrupt Detection WAKE SCLK SOUT
Transceiver Groundshift Detection
CANH CANL
ID-Filter
99AT0032
ceramic close recommended
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L4969
DIM. MIN. 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch
OUTLINE MECHANICAL DATA
(min.), (max.) 0.10 0.004
dimension does include mold flash, protusions gate burrs. Mold flash, protusions gate burrs shall exceed 0.15mm side.
SO20
0016022
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L4969
MIN. 0.23 15.8 13.9 1.27 11.43 10.9 15.5 11.1 15.9 0.031 (typ.) (max.) 0.394 0.228 0.000 0.610 0.429 TYP. MAX. 0.53 0.32 14.5 0.000 0.016 0.009 0.622 0.370 0.547 0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.004 MIN. inch TYP. MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570
Weight: 1.9gr
DIM.
OUTLINE MECHANICAL DATA
include mold flash protusions. Mold flash protusions shall exceed 0.15mm (0.006") Critical dimensions: "E", "a3".
PowerSO20
DETAIL DETAIL
DETAIL
lead
DETAIL
Gage Plane 0.35
slug
BOTTOM VIEW
SEATING PLANE
(COPLANARITY)
PSO20MEC
0056635
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L4969
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