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OPA2674

Dual Wideband, High Output Current Operational Amplifier with Current Limit

OPA2674
SBOS270 - AUGUST 2003
Dual Wideband, High Output Current Operational Amplifier with Current Limit
FEATURES
DESCRIPTION
APPLICATIONS
POWER LINE MODEM xDSL LINE DRIVERS CABLE MODEM DRIVERS MATCHED I / Q CHANNEL AMPLIFIERS BROADBAND VIDEO LINE DRIVERS ARB LINE DRIVERS HIGH CAP LOAD DRIVER
OPA2674 RELATED PRODUCTS
+12V 20
AFE Output
+6.0V 2VPP
1µF 17.7VPP 15VPP Twisted Pair 100 82.5 324 17.4
Single- Supply CPE Upstream Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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ORDERING INFORMATION
PRODUCT OPA2674 PACKAGE-LEAD SO-8 PACKAGE DESIGNATOR(1) D SPECIFIED TEMPERATURE RANGE -40°C to +85°C PACKAGE MARKING OPA2674ID ORDERING NUMBER OPA2674ID OPA2674IDR OPA2674I-14D OPA2674I-14DR TRANSPORT MEDIA, QUANTITY Rails, 100 Tape and Reel, 2500 Rails, 58 Tape and Reel, 2500
OPA2674
SO-14
-40°C to +85°C
OPA2674I-14D
(1) For the most current specification and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PIN CONFIGURATIONS
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Boldface limits are tested at +25°C.
Peaking at a Gain of +1 Bandwidth for 0.1dB Gain Flatness Large-Signal Bandwidth Slew Rate Rise Time and Fall Time Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise NTSC Differential Gain NTCS Differential Phase Channel-to-Channel Crosstalk DC Performance(4) Open-Loop Transimpedance Gain Input Offset Voltage Offset Voltage Drift Noninverting Input Bias Current Noninverting Input Bias Current Drift Inverting Input Bias Current Inverting Input Bias Current Drift Input(4) Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Noninverting Input Impedance Minimum Inverting Input Resistance Maximum Inverting Input Resistance Output (4) Output Voltage Swing
Current Output Short-Circuit Current Closed-Loop Output Impedance Output (4) (SO-14 Only) Current Output at Full Power Current Output at Power Cutback Current Output at Idle Power
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Boldface limits are tested at +25°C.
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Boldface limits are tested at +25°C.
Peaking at a Gain of +1 Bandwidth for 0.1dB Gain Flatness Large-Signal Bandwidth Slew Rate Rise Time and Fall Time Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise Channel-to-Channel Crosstalk DC Performance(4) Open-Loop Transimpedance Gain Input Offset Voltage Offset Voltage Drift Noninverting Input Bias Current Noninverting Input Bias Current Drift Inverting Input Bias Current Inverting Input Bias Current Drift Input Most Positive Input Voltage(5) Most Negative Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Noninverting Input Impedance Minimum Inverting Input Resistance Maximum Inverting Input Resistance Output Most Positive Output Voltage Most Negative Output Voltage Current Output Closed-Loop Output Impedance Output (SO-14 Only) Current Output at Full Power Current Output at Power Cutback Current Output at Idle Power
min max max max max max max min min min typ min max
min min max max min typ min min min
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Boldface limits are tested at +25°C.
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Frequency (MHz)
Full Power 3 0 -3 See Figure 2 100 Idle Power 200 300 400 500
Power Cutback
Frequency (MHz)
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Output Voltage (100mV / div)
See Figure 1 Time (5ns / div)
-60 -65 Harmonic Distortion (dBc) -70 -75 -80 -85 -90 -95 -100 -105 0.1
Harmonic Distortion (dBc)
2nd- Harmonic
3rd- Harmonic -90 Single Channel, See Figure 1 -100
3rd- Harmonic Single Channel, See Figure 1 1 Frequency (MHz) 10 20
1 Output Voltage (VPP)
Harmonic Distortion (dBc)
2nd- Harmonic
Harmonic Distortion (dBc)
2nd- Harmonic
3rd- Harmonic
3rd- Harmonic -85 Single Channel, See Figure 1 -90 1 Gain Magnitude (V / V) 10
Single Channel, See Figure 2 -90 1 Gain Magnitude (-V / V) 10
Output Voltage (100mV / div)
Left Scale Output Voltage (1V / div)
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Power at Matched 50Load, See Figure 1 -100 -10 -5 0 5 Single- Tone Load Power (dBm)
MAXIMUM OUTPUT SWING vs LOAD RESISTANCE 6 5 4 Output Voltage (V) 3 2 VO (V) 1 0 -1 -2 -3 -4 -5 -6 10 100 Load Resistance () 1k 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -600
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
1 W In ternal P ower Single Ch ann el
0 IO (mA)
INPUT VOLTAGE AND CURRENT NOISE DENSITY 100 Inverting Current N oise Voltage Noise (nV / Hz) Current Noise (pA / Hz) 24pA / Hz Crosstalk, Input Referred (dB)
-60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 10M
CHANNEL- CHANNEL CROSSTALK TO- Input Referred
Noninverting Current Noise 16pA / H z
Voltage Noise 1 100 1k 10k 100k
2.0nV / Hz 1M
10M Frequency (Hz)
Frequency (Hz)
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RECOMMENDED RS vs CAPACITIVE LOAD 90 Normalized Gain to Capacitive Load (dB) 80 70 60 RS () 50 40 30 20 10 0 1 10 100 1k Capacitive Load (pF)
402 RS
1 / 2 OPA2674
1k(1)
-8 -10 1M
NOTE: (1) 1k is optional.
Frequency (Hz)
CMRR AND PSRR vs FREQUENCY 70 Power- Supply Rejection Ratio (dB) Common- Mode Rejection Ratio (dB) CMRR Transimpedance Gain (dB) 60 50 40 30 +PSRR 20 10 0 1k 10k 100k 1M 10M 100M Frequency (Hz) -PSRR 100 80 60 40 20 0 10k 120
COMPOSITE VIDEO dG / dP dP, Positive Video dP, Negative Video
dG , Negative Video
dG, Positive Video
Number of 150Loads
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Input Offset Voltage (mV) Input Bias Current (µA)
Input Offset Voltage
Positive Output Swing
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Frequency (MHz)
Harmonic Distortion (dB)
2nd- Harmonic -80 -90 -100 -110 See Figure 5 0.1 1 Frequency (MHz) 10 100 3rd- Harmonic
See Figure 5 10 100 Load Resistance () 1k
Harmonic Distortion (dBc)
See Figure 5 0 20 40 60 80 100 120 140 160
Frequency (kHz)
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INVERTING SMALL- SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
0 -3 -6 0 See Figure 4 100
Frequency (MHz)
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
Left Scale Input Voltage (100mV / div) Output Voltage (0.5V / div) Output Voltage (0.5V / div) 2VPP Large Signal Right Scale 200mVPP Small Signal
Left Scale Input Voltage (100mV / div) 2VPP Large Signal Right Scale 200mVPP Small Signal
See Figure 3
See Figure 4
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-50 -55 Harmonic Distortion (dBc) -60 -65 -70 -75 -80 -85 -90
Harmonic Distortion (dBc)
2nd- Harmonic -75 3rd- Harmonic -80 -85 Single Channel, See Figure 3 -90 0.1 1 Output Voltage (VPP) 5
3rd- Harmonic Single Channel, See Figure 3 0.1 1 Frequency (MHz) 10 20
Harmonic Distortion (dBc)
2nd- Harmonic
Harmonic Distortion (dBc)
3rd- Harmonic
Single Channel, See Figure 3 -85 1 Gain Magnitude (V / V) 10
Single Channel, See Figure 4 -85 1 Gain (-V / V) 10
-40 -45 Harmonic Distortion (dBc) -50 -55 -60 -65 -70 -75 -80 -85 -90
2- TONE, 3rd- ORDER SPURIOUS LEVEL -55 3rd- Order Spurious Level (dBc) -60 -65 -70 -75 -80 -85 -90 Single Channel. See Figure 3. Power at matched 50 load. -12 -10 -8 -6 -4 10MHz 5MHz 20MHz
2nd- Harmonic
3rd- Harmonic
Single Channel, See Figure 3 10 100 Load Resistance () 1k
Single- Tone Load Power (dBm)
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DIFFERENTIAL PERFORMANCE TEST CIRCUIT
RF 316 VI RG RL VO
RF CG 316
Frequency (MHz)
2nd- Harmonic
3rd- Harmonic
100 Load Resistance ()
Harmonic Distortion (dBc)
2nd- Harmonic
2nd- Harmonic -80
-90 3rd- Harmonic -100 1 Output Voltage (VPP) 10
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APPLICATION INFORMATION
WIDEBAND CURRENT-FEEDBACK OPERATION
Power- supply decoupling not shown. 50Load VO 50
1 / 2 OPA2674
50 Source VI
RG 100 RM 100
RF 402
Figure 3 shows the AC coupled, gain of +4, single-supply circuit configuration used as the basis of the +5V Electrical and Typical Characteristics. Though not a rail-to-rail design, the OPA2674 requires minimal input and output voltage headroom compared to other wideband current-feedback op amps. It will deliver a 3VPP output swing on a single +5V supply with greater than 100MHz bandwidth. The key requirement of broadband singlesupply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 3 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806 resistors). The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 1.3V of either supply pin, giving a 2.4VPP input signal range centered between the supply pins. The input impedance matching resistor (57.6) used for testing is adjusted to give a 50 input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1which puts the input DC bias voltage (2.5V) on the output as well. The feedback resistor value is adjusted from the bipolar supply condition to re-optimize for a flat frequency response in +5V, gain of +4, operation. Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 200mA output current. A demanding 100 load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA2674 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5V supply, harmonic distortion plots in the Typical Characteristics charts.
0.1µF
+6V +VS
6.8µF +
50 Source 50 Load
1 / 2 OPA2674
RF 402 RG 133 6.8µF -VS -6V + 0.1µF
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+5V +VS
reduction of even-order harmonic distortion products. Another important advantage for ADSL is that each amplifier needs only half of the total output swing required to drive the load.
0.1µF + 6.8µF +12V 20 VO 100 VS / 2 0.1µF
806 0.1µF VI
1 / 2 OPA2674 RF 453
RF 324 2k RG 82.5 1µF RF 324
RG 150 0.1µF
AFE 2VPP Max Assumed
+6V 0.1µF
17.7VPP 17.4 RM
ZLine 100
The last configuration used as the basis of the +5V Electrical and Typical Characteristics is shown in Figure 4. Design considerations for this inverting, bipolar supply configuration are covered either in single-supply configuration (as shown in Figure 3) or in the Inverting Amplifier Operation discussion.
The analog front-end (AFE) signal is AC-coupled to the driver and the noninverting input of each amplifier is biased to the mid-supply voltage (in this case, +6V). Furthermore, by providing the proper biasing to the amplifier, this scheme also provides high-pass filtering with a corner frequency set here at 5kHz. As the upstream signal bandwidth starts at 26kHz, this high-pass filter does not generate any problems and has the advantage of filtering out unwanted lower frequencies. The input signal is amplified with a gain set by the following equation:
0.1µF VO
6.8µF
1 / 2 OPA2674 RF 453
RG 0.1µF 113 VI RM 88.7
SINGLE-SUPPLY ADSL UPSTREAM DRIVER
Figure 5 shows a single-supply ADSL upstream driver. The dual OPA2674 is configured as a differential gain stage to provide signal drive to the primary of the transformer (here, a step-up transformer with a turns ratio of 1:1.7). The main advantage of this configuration is the
Z LINE 2n2
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OPA2674 HDSL2 UPSTREAM DRIVER
Figure 6 shows an HDSL2 implementation of a singlesupply driver.
Consolidating Equations 3 through 6 allows the required peak-to-peak voltage at the load function of the crest factor, the load impedance, and the power in the load to be expressed. Thus:
+12V 20
1 / 2 OPA2674
(1mW)
This VLPP is usually computed for a nominal line impedance and may be taken as a fixed design target.
0.1µF
324 2k
AFE 2VPP Max Assumed
+6V 0.1µF
82.5 1µF 324
17.7VPP 11.5
ZLine 135
The next step for the driver is to compute the individual amplifier output voltage and currents as a function of VPP on the line and transformer turns ratio. As the turns ratio changes, the minimum allowed supply voltage also changes. The peak current in the amplifier is given by:
1 / 2 OPA2674
With VLPP defined in Equation 7 and RM defined in Equation 2. The peak current is computed in Figure 7 by noting that the total load is 4RM and that the peak current is half of the peak-to-peak calculated using VLPP.
Figure 6. HDSL2 Upstream Driver
The two designs differ by the values of the matching impedance, the load impedance, and the ratio turns of the transformers. All of these differences are reflected in the higher peak current and thus, the higher maximum power dissipation in the output of the driver.
LINE DRIVER HEADROOM MODEL
The first step in a driver design is to compute the peak-to-peak output voltage from the target specifications. This is done using the following equations:
Figure 7. Driver Peak Output Model
With the required output voltage and current versus turns ratio set, an output stage headroom model will allow the required supply voltage versus turns ratio to be developed. The headroom model (see Figure 8) can be described with the following set of equations: First, as available output voltage for each amplifier:
VRMS log (1mW) RL
With PL power and VRMS voltage at the load, and RL load impedance, this gives:
(1mW)
(4) V RMS (5)
V P + CrestFactor
Or, second, as required single-supply voltage:
with VP peak voltage at the load and CF Crest Factor
with VLPP: peak-to-peak voltage at the load.
The minimum supply voltage for a power and load requirement is given by Equation 10.
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OPA2674
SBOS270 - AUGUST 2003 +VCC
The two output stages used to drive the load of Figure 7 can be seen as an H-Bridge in Figure 9. The average current drawn from the supply into this H-Bridge and load will be the peak current in the load given by Equation 8 divided by the crest factor (CF) for the xDSL modulation. This total power from the supply is then reduced by the power in RT to leave the power dissipated internal to the drivers in the four output stage transistors. That power is simply the target line power used in Equation 2 plus the power lost in the matching elements (RM). In the examples here, a perfect match is targeted giving the same power in the matching elements as in the load. The output stage power is then set by Equation 11.
VCC 2PL
The total amplifier power is then:
Figure 8. Line Driver Headroom Model
Table 1 gives V1, V2, R1, and R2 for both +12V and +5V operation of the OPA2674.
Table 1. Line Driver Headroom Model Values
V1 +5V +12V 0.9V 0.9V R1 5 2 V2 0.8V 0.9V R2 5 2
For the ADSL CPE upstream driver design of Figure 5, the peak current is 128mA for a signal that requires a crest factor of 5.33 with a target line power of 13dBm into 100 (20mW). With a typical quiescent current of 18mA and a nominal supply voltage of +12V, the total internal power dissipation for the solution of Figure 5 will be:
PTOT + 18mA(12V) ) 128mA (12V) 2(20mW) + 464mW 5.33
TOTAL DRIVER POWER FOR xDSL APPLICATIONS
The total internal power dissipation for the OPA2674 in an xDSL line driver application will be the sum of the quiescent power and the output stage power. The OPA2674 holds a relatively constant quiescent current versus supply voltage-giving a power contribution that is simply the quiescent current times the supply voltage used (the supply voltage will be greater than the solution given in Equation 10). The total output stage power may be computed with reference to Figure 9.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA2674 in the two package styles. These are available, free, as unpopulated PC boards delivered with descriptive documentation. Table 2 shows the summary information for these boards.
Table 2. Demo Board Availability
PRODUCT PACKAGE SO-8 SO-14 DEMO BOARD NUMBER DEM-OPA268XU DEM-OPA268XN ORDERING NUMBER SBOU003 SBOU002
OPA2674ID OPA2674I-14D
Go to the TI web site (www.ti.com) to request either of these boards.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and
Figure 9. Output Stage Power Model
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inductance can have a major effect on circuit performance. A SPICE model for the OPA2674 is available through the TI web site (www.ti.com). This model does a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions, but does not do as well in predicting the harmonic distortion or dG / dP characteristics. This model does not attempt to distinguish between the package types in small-signal AC performance, nor does it attempt to simulate channel-tochannel coupling.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH
A current-feedback op amp such as the OPA2674 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values, which are shown in the Typical Characteristics the small-signal bandwidth decreases only slightly with increasing gain. These characteristic curves also show that the feedback resistor is changed for each gain setting. The resistor values on the inverting side of the circuit for a current-feedback op amp can be treated as frequency response compensation elements, whereas the ratios set the signal gain. Figure 10 shows the small-signal frequency response analysis circuit for the OPA2674.
R F)R I Z(s) NG
VI VO RI Z(S) IERR
This is written in a loop-gain analysis format, where the errors arising from a non-infinite open-loop gain are shown in the denominator. If Z(s) were infinite over all frequencies, the denominator of Equation 14 reduces to 1 and the ideal desired signal gain shown in the numerator is achieved. The fraction in the denominator of Equation 14 determines the frequency response. Equation 15 shows this as the loop-gain equation:
Z(s) + LoopGain R F ) R I NG
Figure 10. Current-Feedback Transfer Function Analysis Circuit
The key elements of this current-feedback op amp model are:
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INVERTING AMPLIFIER OPERATION
As the OPA2674 is a general-purpose, wideband current-feedback op amp, most of the familiar op amp application circuits are available to the designer. Those dual op amp applications that require considerable flexibility in the feedback element (for example, integrators, transimpedance, and some filters) should consider a unity-gain stable, voltage-feedback amplifier such as the OPA2822, because the feedback resistor is the compensation element for a current-feedback op amp. Wideband inverting operation (and especially summing) is particularly suited to the OPA2674. Figure 12 shows a typical inverting configuration where the I / O impedances and signal gain from Figure 1 are retained in an inverting circuit configuration.
+6V Power- supply decoupling not shown. 50 Load
50 Source VI
RG 97.6
RF 392
Feedback Resistor ()
RM 102 -6V
Figure 12. Inverting Gain of -4 with Impedance Matching
200 0 5 10 15 20 25 Noise Gain
Figure 11. Feedback Resistor vs Noise Gain
The total impedance going into the inverting input may be used to adjust the closed-loop signal bandwidth. Inserting a series resistor between the inverting input and the summing junction increases the feedback impedance (the denominator of Equation 15), decreasing the bandwidth. The internal buffer output impedance for the OPA2674 is slightly influenced by the source impedance coming from of the noninverting input terminal. High-source resistors also have the effect of increasing RI, decreasing the bandwidth. For those single-supply applications that develop a midpoint bias at the noninverting input through high valued resistors, the decoupling capacitor is essential for power-supply ripple rejection, noninverting input noise current shunting, and to minimize the high-frequency value for RI in Figure 10.
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specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an analog-to-digital (A / D) converterincluding additional external capacitance that may be recommended to improve the A / D converter linearity. A high-speed, high open-loop gain amplifier like the OPA2674 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and / or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the Recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2674. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2674 output pin (see the Board Layout Guidelines section).
OUTPUT CURRENT AND VOLTAGE
DISTORTION PERFORMANCE
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In most op amps, increasing the output voltage swing directly increases harmonic distortion. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate, whereas the 3rd-harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the difference between it and the 2nd-harmonic decreases less than the expected 6dB, whereas the difference between it and the 3rd-harmonic decreases by less than the expected 12dB. This factor also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low-output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 10dBm / tone into a matched 50 load (i.e., 2VPP for each tone at the load, which requires 8VPP for the overall 2-tone envelope at the output pin), the Typical Characteristics show 67dBc difference between the test-tone power and the 3rd-order intermodulation spurious levels. This exceptional performance improves further when operating at lower frequencies.
The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 17 shows the general form for the output noise voltage using the terms given in Figure 13.
) 4kTRFNG
ENI 1 / 2 OPA2674 IBN EO
ERS 4kTRS RG IBI
4kT RG
Figure 13. Op Amp Noise Analysis Model
NOISE PERFORMANCE
Wideband current-feedback op amps generally have a higher output noise than comparable voltage-feedback op amps. The OPA2674 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (24pA / Hz) is lower than earlier solutions whereas the input voltage noise (2.0nV / Hz) is lower than most unity-gain stable, wideband voltage-feedback op amps. This low input voltage noise is achieved at the price of higher noninverting input current noise (16pA / Hz). As long as the AC source impedance from the noninverting node is less than 100, this current noise does not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 13 shows the op amp noise analysis model with all noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV / Hz or pA / Hz.
DIFFERENTIAL NOISE PERFORMANCE
As the OPA2674 is used as a differential driver in xDSL applications, it is important to analyze the noise in such a configuration. See Figure 14 for the op amp noise model for the differential configuration.
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IN Driver EN
In order to minimize the noise contributed by IN, it is recommended to keep the noninverting source impedance as low as possible.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp such as the OPA2674 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed, voltage-feedback amplifiers however, the two input bias currents are somewhat higher and are unmatched. While bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband current-feedback op amps. Because the two input bias currents are unrelated in both magnitude and polarity, matching the input source impedance to reduce error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to:
RS ERS 4kTRS II RG EO2 4kTRG RF IN 4kTRF 4kTRF
RS ERS 4kTRS
Figure 14. Differential Op Amp Noise Analysis Model
As a reminder, the differential gain is expressed as:
POWER CONTROL OPERATION (SO-14 ONLY)
The OPA2674I-14D provides a power control feature that may be used to reduce system power. The four modes of operation for this power control feature are full-power, power cutback, idle state, and power shutdown. These four operating modes are set through two logic lines A0 and A1. Table 3 shows the different modes of operation.
The output noise voltage can be expressed as shown below:
Table 3. Power Control Mode of Operation
MODE OF OPERATION Full-Power A1 1 1 0 0 A0 1 0 1 0
Power Cutback Idle State Shutdown
4kTR F GD
Evaluating this equation for the OPA2674 circuit and component values of Figure 5 gives a total output spot noise voltage of 31.0nV / Hz and a total equivalent input spot noise voltage of 3.5nV / Hz.
The full-power mode is used for normal operating condition. The power cutback mode brings the quiescent power to 13.5mA. The idle state mode keeps a low output impedance but reduces output power and bandwidth. The shutdown mode has a high output impedance as well as the lowest quiescent power (1.0mA). If the A0 and A1 pins are left unconnected, the OPA2674I-14D operates normally (full-power).
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To change the power mode, the control pins (either A0 or A1) must be asserted low. This logic control is referenced to the positive supply, as shown in the simplified circuit of Figure 15.
120k Q2 Q1
For extremely high internal power applications, where improved thermal performance is required, consider the PSO-8 package of the OPA2677-a similar part with no output stage current limit and a thermal impedance of less than 50°C / W.
60k 46k A0 or A1 -VS Control -VS
BOARD LAYOUT GUIDELINES
Figure 15. Supply Power Control Circuit
THERMAL ANALYSIS
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SBOS270 - AUGUST 2003
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devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case, and set the series resistor value as shown in the plot of RS vs Capacitive Load. However, this does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA2674 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2674 onto the board.
INPUT AND ESD PROTECTION
External Pin
Internal Circuitry
Figure 16. ESD Steering Diodes
MECHANICAL DATA
MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001
D (R-PDSO-G)
8 PINS SHOWN 0.050 (1, 27) 8 5 0.020 (0, 51) 0.014 (0, 35) 0.010 (0, 25)
PLASTIC SMALL-OUTLINE PACKAGE
0.008 (0, 20) NOM
Gage Plane 1 A 4 0°- 8° 0.044 (1, 12) 0.016 (0, 40)
Seating Plane 0.069 (1, 75) MAX 0.010 (0, 25) 0.004 (0, 10) 0.004 (0, 10)
PINS DIM A MAX A MIN
4040047 / E 09 / 01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0, 15). Falls within JEDEC MS-012
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