AK4584 24Bit 96kHz Audio CODEC with DIT/DIR GENERAL DESCRIPT

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AK4584 24Bit 96kHz Audio CODEC with DIT/DIR GENERAL DESCRIPT

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[AK4584]
AK4584
24Bit 96kHz Audio CODEC with DIT/DIR
GENERAL DESCRIPTION AK4584 high-performance 24-bit CODEC 96kHz consumer audio digital recording applications. on-board analog-to-digital converter impressive dynamic range, thanks part AKM's Enhanced Dual-Bit architecture. features newly developed Advanced Multi-Bit architecture achieves out-of-band noise high jitter tolerance through Switched Capacitor Filter (SCF) technology. AK4584 also S/PDIF-AES/EBU digital audio transmitter (DIT) digital audio receiver (DIR) that compatible with 24-bit, 192kHz formats. AK4584 automatically detect NON-PCM streams like AC-3, MPEG DTS. Either digital audio input routed directly digital audio output. AK4584 input Programmable Gain Amplifier well suited computer DAWs, MiniDisc, DVD-R, hard disk CD-R recording/playback systems.
*AC-3 trademark Dolby Laboratories. trademark Digital Theater Systems, Inc.
FEATURES 24bit 96kHz Single-end Input S/(N+D): 90dB Dynamic Range, S/N: 100dB Digital offset cancellation Input with +18dB gain 0.5dB step Input DATT with -72dB format: justified 24bit 192kHz 24bit times Digital Filter Ripple: ±0.005dB, Attenuation: 75dB Single-end Output S/(N+D): 94dB Dynamic Range, S/N: 104dB De-emphasis 32kHz, 44.1kHz, 48kHz sampling Digital Attenuator with soft-transition Soft Mute Zero Detect Function format: justified, justified Outputs 192kHz 3-Channel Transmission Outputs Through outputs Output) bits Channel Status Buffer
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[AK4584]
Inputs 24bit 192kHz Supports AES3, IEC60958, S/PDIF, EIAJ CP1201 Jitter Analog Lock Range: 192kHz Clock Source: X'tal Digital Receive Channel inputs Detect Function Non-PCM Stream Detection DTS-CD Stream Detection Validity Flag Detection Sampling Frequency Detection Unlock Parity Error Detection bits Channel Status Buffer Burst Preamble Buffer Non-PCM Stream Support External Audio Clock Input Master Clock Input 256fs, 384fs, 512fs, 768fs 44.1kHz 48kHz) 256fs, 384fs 88.2kHz 96kHz) 128fs, 192fs 176.4kHz 192kHz) Support Master Slave Mode Serial I/F: 4-wire serial operation Power Supply 44pin LQFP Package 70°C
MS0118-E-00
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[AK4584]
Block Diagram
INT0 INT1
OPS1-0 TX2E TX1E
AVDD AVSS DVDD DVSS
IPS1-0
R_LRCK R_BICK R_DATA R_MCLK
T_LRCK T_BICK T_DATA T_MCLK
TX3E
A_LRCK
D_LRCK
LOUT
IPGA
DATT
A_BICK A_DATA A_MCLK
Audio Interface
D_BICK D_DATA D_MCLK
DATT SMUTE
LOUT ROUT LRCK BICK SDTO SDTI TVDD
ROUT LRCK BICK SDTO
PVDD PVSS VREF
SDTI
X'tal
MCLK Selector
Divider
MCKI
MCKO1
VCOM MCKO1 MCKO2 DMCK XTALE
Block Diagram
MCKO2
Control Register
CDTO CDTI CCLK
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[AK4584]
Ordering Guide
AK4584VQ AKD4584 +70°C 44pin LQFP (0.8mm pitch) Evaluation Board AK4584
Layout
TEST1
PVDD
AVDD
PVSS
TEST2 INT0 INT1 CDTI CDTO CCLK XTALE XTI/MCKI TEST3 DMCK DVDD DVSS TVDD ROUT LOUT VCOM LRCK BICK SDTI SDTO MCKO2 MCKO1
AK4584VQ
View
MS0118-E-00
AVSS
VREF
2001/11
[AK4584]
PIN/FUNCTION
Name TEST2 INT0 INT1 CDTI CDTO CCLK TEST3 XTALE DVDD DVSS TVDD MCKI DMCK Function Test (Internal pull-down pin) Receiver Input with 0.2Vpp Internal bonding pin, Fixed "AVSS") Receiver Input with 0.2Vpp Power-Down Mode "H": Power "L": Power down reset initialize control registers. Interrupt Interrupt Control Data Input Control Data Output Control Data Clock Chip Select Test (Fixed AVSS) Transmitter Output Transmitter Output X'tal Enable Enable, Disable Transmitter Output Digital Power Supply Pin, 4.75 5.25V Digital Ground Output Buffer Power Supply Pin, 5.25V X'tal Output X'tal Input External Master Clock Input MCKO1 Disable MCKO1 output, MCKO1 output
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[AK4584]
MCKO1 MCKO2 SDTO SDTI BICK LRCK VCOM LOUT ROUT AVSS AVDD VREF PVDD PVSS TEST1
Master Clock Output Master Clock Output Audio Serial Data Output Audio Serial Data Input Audio Serial Data Clock Input Output Channel Clock Master Slave Mode Master Mode, Slave Mode Zero Input Detect Common Voltage Output Pin, AVDD/2 Bias voltage inputs outputs. Analog Output Analog Output Analog Ground Analog Power Supply Pin, 4.75 5.25V Voltage Reference Input Pin, AVDD Used voltage reference DAC. VREF connected externally filtered AVDD. Analog Input Analog Input Power Supply Pin, 4.75 5.25V External Resistor resistor PVSS externally. Ground Receiver Input with 0.2Vpp Test (Internal pull-down pin) Receiver Input with 0.2Vpp
Note: input pins except pull-down pins should left floating.
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[AK4584]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS, PVSS=0V; Note Parameter Power Supplies: Analog Digital Output Buffer |AVSS DVSS| (Note |AVSS PVSS| (Note Input Current, Except Supplies Analog Input Voltage (VREF, LIN, pins) Digital Input Voltage (Except RX1-4, BICK, LRCK pins) Digital Input Voltage (RX1-4 pins) Digital Input Voltage (BICK, LRCK pins) Ambient Temperature (powered applied) Storage Temperature Symbol AVDD DVDD PVDD TVDD GND1 GND2 VINA VIND1 VIND2 VIND3 Tstg -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 AVDD+0.3 DVDD+0.3 PVDD+0.3 TVDD+0.3 Units
Note: voltages with respect ground. Note: AVSS, DVSS PVSS must connected same analog ground plane.
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, PVSS=0V; Note Parameter Power Supplies Analog (Note Digital Output Buffer Voltage Reference (Note Symbol AVDD DVDD PVDD TVDD VREF 4.75 4.75 4.75 5.25 AVDD AVDD DVDD AVDD Units
Note: voltages with respect ground. Note: power sequence between AVDD, DVDD, PVDD TVDD critical. Note: Normally, VREF voltage same AVDD voltage.
WARNING: assumes responsibility usage beyond conditions this datasheet.
MS0118-E-00
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[AK4584]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD, TVDD=5.0V; AVSS=DVSS=PVSS=0V; VREF=AVDD; fs=44.1kHz, 96kHz, 192kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=10Hz 20kHz fs=44.1kHz, 10Hz 40kHz fs=96kHz; 10Hz 80kHz fs=192kHz; unless otherwise specified) Parameter Units Input Characteristics: Input Voltage (Note fs=44.1kHz, AIN=0.6 AVDD fs=96kHz, AIN=0.62 AVDD Input Resistance Step Size Gain Control Range Analog Input Characteristics: IPGA=0dB Resolution Bits S/(N+D) (-0.5dBFS) fs=44.1kHz fs=96kHz (-60dBFS) fs=44.1kHz, A-weighted fs=96kHz fs=44.1kHz, A-weighted fs=96kHz Interchannel Isolation Interchannel Gain Mismatch Gain Drift ppm/°C Power Supply Rejection (Note Analog Output Characteristics: Resolution Bits S/(N+D) (0dBFS) fs=44.1kHz fs=96kHz fs=192kHz (-60dBFS) fs=44.1kHz, A-weighted fs=96kHz fs=192kHz fs=44.1kHz, A-weighted fs=96kHz fs=192kHz Interchannel Isolation Interchannel Gain Mismatch Gain Drift ppm/°C Output Voltage (Note Load Resistance Load Capacitance Power Supply Rejection (Note Note: Full scale (0dB) input voltage IPGA 0dB. Note: applied AVDD, DVDD, PVDD TVDD with 1kHz, 50mVpp.VREF held constant voltage. Note: This voltage proportional VREF. Vout VREF.
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[AK4584]
Parameter Power Supplies Power Supply Current Normal Operation (PDN "H") AVDD PVDD (fs=44.1kHz) DVDD+TVDD (fs=44.1kHz) (fs=96kHz) Power-down mode (PDN "L") (Note AVDD PVDD DVDD+TVDD Note: digital input pins held DVDD DVSS.
Units
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD=4.75 5.25V; TVDD=2.7 5.25V) Parameter Symbol Input Resistance Input Voltage Input Hysteresis Input Sample Frequency Units mVpp
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[AK4584]
FILTER CHARACTERISTICS
(Ta=-10 70°C; AVDD, DVDD, PVDD=4.75 5.25V; TVDD=2.7 5.25V; fs=44.1kHz; DEM=OFF) Parameter Symbol Digital Filter (Decimation LPF): 19.76 Passband (Note ±0.005dB 20.02 -0.02dB 20.20 -0.06dB 22.05 -6.0dB Stopband 24.34 Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note Group Delay Distortion Digital Filter (HPF): Frequency Response (Note -3dB -0.5dB -0.1dB Digital Filter: Passband (Note ±0.01dB 20.0 -6.0dB 22.05 Stopband 24.1 Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note Digital Filter SMF: Frequency Response: -0.1 20.0kHz -0.2 40kHz (Note -1.0 80kHz (Note Units 1/fs 1/fs
Note: passband stopband frequencies scale with example, 20.02kHz -0.02dB 0.454 Note: calculated delay time induced digital filtering. This time from input analog signal setting 24bit data both channels output register ADC. DAC, this time from setting 24bit data both channels input register output analog signal. Note: 96kHz. Note: 192kHz.
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[AK4584]
CHARACTERISTICS
(Ta=-10 70°C; AVDD, DVDD, PVDD=4.75 5.25V; TVDD=2.7 5.25V) Parameter Symbol High-Level Input Voltage (Except pin) (XTI pin) 70%DVDD Low-Level Input Voltage (Except pin) (XTI pin) Input Voltage Coupling (XTI pin, Note 40%DVDD High-Level Output Voltage (Except TX1-3, pins Iout=-400µA) TVDD-0.5 (TX1-3 Iout=-400µA) DVDD-0.5 (DZF Iout=-400µA) AVDD-0.5 Low-Level Output Voltage (Iout=400µA) Output Voltage Level (Note Input Leakage Current Note: case connecting capacitance pin. (Refer Figure Note: Refer Figure 30%DVDD Units
MS0118-E-00
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[AK4584]
SWITCHING CHARACTERISTICS
(Ta=-10 70°C; AVDD, DVDD, PVDD=4.75 5.25V, TVDD=2.7 5.25V; CL=20pF) Parameter Symbol Master Clock Timing Crystal Resonator External Clock Frequency Frequency Pulse Width Pulse Width High Frequency Duty Cycle (Note Frequency Duty Cycle 11.2896 11.2896 0.4/fCLK 0.4/fCLK 11.2896 5.6448 88.2 176.4 24.576 36.864 Units
fCLK tCLKL tCLKH fMCK dMCK fMCK dMCK fPLL
MCKO1 Output MCKO2 Output
24.576 18.432
Clock Recover Frequency LRCK Frequency Normal Speed Mode (DFS0="0", DFS1="0") Double Speed Mode (DFS0="1", DFS1="0") Quad Speed Mode (DFS0="0", DFS1="1") Duty Cycle Slave mode Master mode Audio Interface Timing Slave mode BICK Period BICK Pulse Width Pulse Width High LRCK Edge BICK (Note BICK LRCK Edge (Note LRCK SDTO (MSB) (Except mode) BICK SDTO SDTI Hold Time SDTI Setup Time Master mode BICK Frequency BICK Duty BICK LRCK BICK SDTO SDTI Hold Time SDTI Setup Time
tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS
64fs
Note: Duty cycle guaranteed when using external clock input. Note: BICK rising edge must occur same time LRCK edge.
MS0118-E-00
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[AK4584]
Parameter Control Interface Timing CCLK Period CCLK Pulse Width Pulse Width High CDTI Setup Time CDTI Hold Time Time CCLK CCLK CDTO Delay CDTO Hi-Z Reset Timing Pulse Width (Note RSTADN SDTO valid (Note
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ tPDV
Units 1/fs
Note: AK4584 reset bringing "L". Note: This cycle number LRCK rising edges from RSTADN bit.
MS0118-E-00
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[AK4584]
Timing Diagram
1/fCLK tCLKH 1/fs tBCK tBCKH fMCK tBCKL tCLKL
MCLK
LRCK
BICK
MCKO dMCK dMCK
Clock Timing
50%TVDD
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[AK4584]
LRCK
tBLR tLRB tLRS tBSD
BICK
SDTO tSDS tSDH
50%TVDD
SDTI
Audio Interface Timing (Slave mode)
LRCK
50%TVDD
tMBLR
dBCK 50%TVDD
BICK
tBSD
SDTO tSDS tSDH
50%TVDD
SDTI
Audio Interface Timing (Master mode)
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[AK4584]
tCSS tCCKL tCCKH
CCLK
tCDS tCDH
CDTI
CDTO
Hi-Z
WRITE/READ Command Input Timing
tCSW tCSH
CCLK
CDTI
CDTO
Hi-Z
WRITE Data Input Timing
MS0118-E-00
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[AK4584]
CCLK
CDTI
tDCD
CDTO
Hi-Z
50%TVDD
READ Data Output Timing
tCSW tCSH
CCLK
CDTI tCCZ Hi-Z
CDTO
50%TVDD
READ Data Output Timing
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[AK4584]
tPDV
SDTO
50%TVDD
Power Down Reset Timing
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[AK4584]
OPERATION OVERVIEW Internal Signal Path
input source SDTO switched between outputs ADC, SDTI DIR. input source switched between outputs SDTI. There also through/bypass path from that also selected. Switch Names (DAC1-0 etc) Figure correspond register bits that control switch function. Refer "Register Definitions" (Address 08H).
IPGA DATT
DAC1-0
PCM1-0
DATT SMUTE
SDTI
SDTO
DIT1-0
DIT1-0
Figure Connection between Input Sources Output Sources
Clock Operation Mode
CM1-0 bits determine clock source AK4584; either X'tal (including external clock source, Table mode clock source switched automatically from X'tal when loses lock. mode clock source fixed external X'tal input, however also operating enabling monitoring recovered data such bits. mode mode frequency X'tal should different from that recovered frequency from PLL. When XTL1-0 bits "11", X'tal oscillator stopped mode default values "01" CM1-0 bits. Since signal path changed automatically when changing CM1-0 bits, output source should selected changing register 08H. Mode UNLOCK X'tal Clock Source X'tal X'tal X'tal Oscillation (Power-up), OFF: STOP (Power-down) XTALE XTL1-0 bits "11", others Table Clock Operation Mode Select
Default
MS0118-E-00
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[AK4584]
Master Clock Output
AK4584 clock outputs, MCKO1 MCKO2. These clocks derived from either recovered clock X'tal oscillator. mode, master clock output frequencies (MCKO1, MCKO2) OCKS1-0 bits shown Table X'tal mode external clock mode, frequency MCKO1 same X'tal external clock. MCKO2 outputs half frequency MCKO1 (Table MCKO1 output disabled DMCK pin. MCKO1 output (Disable) when DMCK "H", MCKO1 output normal output when DMCK "L". mode, mode does support 96kHz. default values OCKS1-0 bits "01" Mode OCKS1 OCKS0 MCKO1 512fs 256fs 128fs 64fs MCKO2 256fs 128fs 64fs 32fs 48kHz 96kHz 192kHz 192kHz
Default
Table Master Clock Output Frequency Select (PLL Mode) X'tal MCKO1 MCKO2 11.2896MHz 11.2896MHz 5.6448MHz 12.288MHz 12.288MHz 6.144MHz 24.576MHZ 24.576MHz 12.288MHz Table Master Clock Output Frequency Select (X'tal Mode) Table connection example when using AK5394 AK4394 slave mode. AK5394 AK4394 Clock Output MCKO2 MCKO1 Normal Speed 256fs 512fs Double Speed 128fs 256fs Quad Speed 64fs 128fs Table Clock Select AK5394 AK4394
MS0118-E-00
2001/11
[AK4584]
System Clock
master clock (MCLK) derived from either X'tal oscillator recovered clock from AK4584's PLL. MCLK frequency ICKS1-0 bits (Table X'tal mode external clock mode. sampling speed (normal, double quad speed modes) selected DFS1-0 bits (Table powered down during quad speed mode. When using X'tal oscillator, external loading capacitors between XTI/XTO pins DVSS required. external clock input with left floating. input accept both CMOS coupled clock sources with 40%DVDD. slave mode, LRCK clock input must synchronized with MCLK, however phase critical. external clocks (MCLK, BICK LRCK) must present unless parts powered down control register, otherwise excessive current produced internal dynamic logic. master mode, master clock (MCLK) must provided X'tal oscillator, external clock internal unless "L". MCLK Normal Double Quad ICKS1 ICKS0 (DFS1-0 "00") (DFS1-0 "01") (DFS1-0 "10") 256fs 384s 512fs 256fs 128fs 768fs 384fs 192fs Table Master Clock Input Frequency Select (X'tal Mode) DFS1 DFS0 Sampling Rate Default
Mode
Default
Normal Speed Double Speed Quad Speed Table Sampling Speed MCLK Double 128fs 192fs 256fs 384fs
MCLK Normal 256fs 384fs 512fs 768fs MCLK Normal 256fs 384fs 512fs 768fs
fs=44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
fs=88.2kHz 22.5792MHz 33.8688MHz
MCLK Quad 64fs 96fs 128fs 192fs
fs=176.4kHz 22.5792MHz 33.8688MHz
MCLK MCLK Double Quad fs=48kHz fs=96kHz 12.288MHz 128fs 64fs 18.432MHz 192fs 96fs 24.576MHz 256fs 24.576MHz 128fs 36.864MHz 384fs 36.864MHz 192fs Table Master Clock Frequencies example
fs=192kHz 24.576MHz 36.864MHz
X'tal mode supports from 11.2896MHz 24.576MHz. Frequencies over 24.576MHz supported external clock mode only.
MS0118-E-00
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[AK4584]
Clock Source
Using X'tal
AK4584
Figure X'tal mode Note: External capacitance depends crystal oscillator (Typ. 10-40pF) Using external clock
External Clock AK4584
External Clock
AK4584
Figure External Clock mode Figure External Clock Mode (Input CMOS Level) (Input 40%DVDD) Note: Input clock must exceed DVDD. Clock Operation Mode
AK4584
Figure mode
192kHz Clock Recovery
chip jitter wide lock range from 32kHz 192kHz lock time less than 20ms. AK4584 also sampling frequency detect function that works performing either clock comparison against X'tal oscillator using channel status. AK4584 detects following sampling frequencies 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz 192kHz. loses lock when incoming sync interval incorrect.
MS0118-E-00
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[AK4584]
Biphase Input
Four receiver inputs (RX1-4 pins) available. Each input includes unbalanced input amplifier accept input signals 200mV more. IPS1 IPS0 Input Data Table Recovery Data Select
Default
Biphase Output
AK4584 output through data from digital receiver inputs (RX1-4) TX1/2 pins. output transmitter data (SDTI data, converted data through output from DIR). OPS1-0 bits select source output from TX1-2 pins DIT1-0 bits select source pin. first bytes C-bit (Channel Status) controlled CT39-CT0 bits control registers. When (consumer mode), bits20-23 (Audio channel) cannot controlled directly. When "1", AK4584 outputs "1000" CT20-23 bits left channel outputs "0100" CT20-23 bits right channel automatically. When "0", AK4584 outputs "0000". (User Data) output formats. When UDIT "0", always "L". When UDIT "1", recovered bits passed through (DIR-DIT loop mode bit). This mode only available when locked. When unlocked, "L". OPS1 OPS0 Output Data Table Output Data Select TX1/2
Default
DIT1
DIT0 Input Source SDTI Table Output Data Select
Default
Note: When loses lock, (Validity) data block immediately following loss-of-lock accurate. Disregard this data following data blocks.
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[AK4584]
Biphase signal input/output circuit
0.1uF Coax
AK4584
Figure Consumer Input Circuit (Coaxial Input) Note Coax input only coupling level this input from next input line pattern exceeds 50mV, incorrect operation occur. this case, possible lower coupling level adding this decoupling capacitor. Note Ground connector terminator should connected PVSS AK4584 with impedance board. Optical Receiver Optical Fiber
AK4584
Figure Consumer Input Circuit (Optical Input) When using coaxial input, input level line small. Care must taken reduce, crosstalk among input lines inserting shield pattern between them. AK4584 includes output buffer. output level 0.5V, +/-20% using external resistor network shown below. Figure transformer. DVSS cable
Figure External Resistor Network
MS0118-E-00
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[AK4584]
Sampling Frequency Pre-emphasis Detection
AK4584 methods detecting sampling frequency. sampling frequency detected comparing recovered clock X'tal oscillator, detected frequency reported FS3-0 bits. XTL1-0 bits select reference X'tal frequency (Table 11). When XTL1-0 bits "11" XTALE "L", X'tal oscillator stopped sampling frequency detected channel status sampling frequency information. detected frequency reported FS3-0 bits. default values FS3-0 bits "0000". XTL1 XTL0 X'tal Frequency 11.2896MHz 12.288MHz 24.576MHz channel status Table Reference X'tal Frequency
Default
Except XTL1-0 bits="11" Register Output 44.1kHz Reserved 48kHz 32kHz 88.2kHz 96kHz 176.4kHz 192kHz Table Information Clock comparison
XTL1-0 bits="11" Consumer Mode Mode (Note Byte3 Byte0 Byte4 Bit3,2,1,0 Bit7,6 Bit6,5,4,3 0000 0000 0001 (others) 0000 0010 0000 0011 0000 (1000) 1010 (1010) 0010 (1100) 1011 (1110) 0011
Note consumer mode, Byte3 Bit3-0 copied FS3-0. pre-emphasis information detected reported bit. This information extracted from channel (default). switched channel CS12 control register.
Byte0 Bit3,4,5 0X100 0X100 Table Consumer Mode Pre-emphasis Byte0 Bit2,3,4 Table Mode Pre-emphasis
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[AK4584]
Error Handling
following eight events will cause INT1-0 pins "H".
UNOCK: when goes UNLOCK state. AK4584 loses lock when distance between preambles correct when those preambles correct. PAR: when parity error biphase coding error detected. Updated every sub-frame cycle. Reading this register resets when Non-Linear Stream detected.
AUTO:
DTSCD: when DTS-CD Stream detected. AUDION:"1" when "AUDIO" recovered channel status indicates "1". PEM: when "PEM" recovered channel status indicates "1". Updated every block cycle. when validity flag detected. when FS3-0 bits change. FS3-0 bits changed, during sub-frame. contents FS3-0 bits frequency detection result fs-bit C-bit X'tal (refer Table 12), this compared last data every block. Reading this register resets
INT1-0 pins output OR'ed signal among those eight factors. However, each mask mask each factor. When masks factor, factor does affect INT1-0 pins operation (those masks affect those registers (UNLOCK, PAR, etc.) themselves). Once INT0 goes "H", maintains 1024 cycles (this value changed EFH1-0 bits) after factors removed. Once "1", holds until reading register. While AK4584 loses lock, channel status bits updated hold previous data. initial state, INT0 outputs OR'ed signal between UNLOCK bits. INT1 outputs OR'ed signal among AUTO, DTSCD, AUDION VDIR bits. INT1-0 pins when OFF. Register DTSCD AUDION VDIR Table Error Handling Don't Care) SDTO Previous Data Output Output Output Output Output Output
UNLOCK
AUTO
Output Output Output Output Output Output Output Output
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[AK4584]
Error (UNLOCK, PAR,.) INT0
(Error)
Hold Time (max: 4096/fs)
INT1 Register (PAR, Register (others) Command MCKO,BICK,LRCK (UNLOCK) MCKO,BICK,LRCK (except UNLOCK) SDTO (UNLOCK) SDTO (PAR error) SDTO (others) Previous Data
Hold Time
Hold
Reset
READ
Free (fs: around 20kHz)
Normal Operation Figure INT0/1 Timing
MS0118-E-00
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[AK4584]
Initialize Read
INT0/1
Release Muting
Mute Output
Read Each Error Handling
INT0/1
Figure Error Handling Sequence Example
Non-PCM (AC-3, MPEG, etc.) DTS-CD Bitstream Detection
AK4584 Non-PCM steam auto-detect function. When 32-bit mode Non-PCM preamble based Dolby's "AC-3 Data Stream IEC60958 Interface" detected, AUTO goes "1". 96-bit sync code consists 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 0x4E1F. Detection this pattern will AUTO "1". Once AUTO "1", will remain until 4096 frames pass through chip without additional sync pattern being detected. When those preambles detected, burst preambles that follow sync codes stored registers. AK4584 also DTS-CD stream auto-detection. When AK4584 detects DTS-CD streams, DTSCD goes "1". next sync code does appear within 4096 flames, DTSCD goes until when AK4584 detects stream again.
MS0118-E-00
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[AK4584]
Audio Interface Format
Five serial modes supported shown Table selected DIF2-0 bits. modes, serial data first, compliment format. SDTO clocked falling edge BICK SDTI latched rising edge. audio interface supports both master slave modes. master mode, BICK LRCK output with BICK frequency fixed 64fs LRCK frequency fixed When format equal less than 20-bit (mode 0-1), LSBs sub-frame truncated. mode 2-4, last 4LSBs auxiliary data (see Figure 10). Mode SDTI input formats used 16-20bit data zeroing unused LSBs.
sub-frame IEC60958
Aux.
preamble
AK4584 Audio Data (SDTO, First)
Figure Structure Mode DIF2 DIF1 DIF0 SDTO SDTI 24bit, justified 16bit, justified 24bit, justified 20bit, justified 24bit, justified 24bit, justified 24bit, Compatible 24bit, Compatible 24bit, justified 24bit, justified Table Audio Data Format LRCK BICK 32fs 40fs 48fs 48fs 48fs
Default
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[AK4584]
LRCK
BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i)
Don't Care Don't Care
SDTO-23:MSB, 0:LSB SDTI-15:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care
Don't Care
SDTO-23:MSB, 0:LSB SDTI-19:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care
Don't Care
23:MSB, 0:LSB Data Data
Figure Mode Timing
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[AK4584]
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care Don't Care
23:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care 23:MSB, 0:LSB
Don't Care
Data
Data
Figure Mode Timing
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[AK4584]
Master Mode Slave Mode
selects between master slave modes. master mode, slave mode. master mode, MCKO, BICK LRCK output. slave mode, only MCKO output from AK4584 dividing MCKO externally provides BICK LRCK. MCKO1/2 BICK, LRCK MCKO1 Output BICK Input Slave Mode MCKO2 Output LRCK Input MCKO1 Output BICK Output Master Mode MCKO2 Output LRCK Output Table Master mode/Slave mode
Relationship Clock operation Power down
When AK4584 powered down, XTALE controls master clock output. DMCK disables MCKO1 output. Don't Care Available Default Fixed "01" XTALE CM1-0 MCKO1/2 MCKO1 MCKO2 MCKO1 Output1) MCKO2 Output1) MCKO1 MCKO2 MCKO1 Output1) MCKO2 Output1) MCKO1 Output2) MCKO2 Output2) BICK, LRCK BICK Input LRCK Input DIR, DIT, CODEC Power Down
BICK LRCK BICK Input LRCK Input BICK Output LRCK Output
Power Down
Normal Operation
Table Clock Operation Note Since powered down, X'tal oscillator external clock selected clock source. Note CM1-0 bits select clock source. When changing between modes, there possibility that master clock output (MCKO) stops momentarily. Note When "L", fixed when XTALE external clock coupled.
Digital High Pass Filter
digital high-pass filter offset cancellation. cut-off frequency 0.9Hz 44.1kHz also scales with sampling rate (fs).
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[AK4584]
Input Volume
AK4584 includes channel-independent analog volumes (IPGA), each with levels 0.5dB increments. These located front ADCs while digital volume controls (IATT) with levels (including MUTE) located after ADCs. Control both these volumes setting handled same register address. When register "1", IPGA changes when IATT changes. IPGA analog volume control that improves ratio compared with digital volume controls (Table 19). Level changes only occur during zero-crossings minimize switching noise. Channel independent zero-crossing detection used. there zero-crossings, then level will change after time-out. time-out period scales with periods 256/fs, 512/fs, 1024/fs 2048/fs selected ZTM1-0 bits normal speed mode. value written IPGA register before IPGA changes zero crossing time-out, previous value becomes invalid. timer (channel independent) time-out reset timer restarts IPGA value. ZCEI control register enable zero-crossing detection. IATT pseudo-log volume that linear-interpolated internally. When changing level, transition between values 8031 levels done soft changes (zero crossings), eliminating switching noise. Input Gain Setting +6dB fs=44.1kHz, A-weight 100dB 98dB Table PGA+ADC ZTM1
+18dB 90dB
ZTM0 Normal Speed Double Speed 256/fs 512/fs 512/fs 1024/fs 1024/fs 2048/fs 2048/fs 4096/fs Table Zero Crossing Timeout
Default
De-emphasis Control
includes digital de-emphasis filter (tc=50/15µs) filter. This filter corresponds three frequencies (32kHz, 44.1kHz, 48kHz). This setting done control register (DEM1-0 bits). This filter always double speed quad speed modes. DEM1 DEM0 Mode
44.1kHz Default 48kHz 32kHz Table De-emphasis Control
Output Volume
AK4584 includes channel independent digital output volumes (ATT) with levels 0.5dB steps including MUTE. These volumes front attenuate input data from -127dB mute. When changing level, transitions executed soft changes (zero crossings), eliminating switching noise.
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[AK4584]
Soft Mute Operation
Soft mute operation performed digital domain input. When SMUTE goes "1", output signal attenuated during 1024 LRCK cycles. When SMUTE returned "0", mute cancelled output attenuation gradually changes during 1024 LRCK cycles. soft mute cancelled within 1024 LRCK cycles after starting operation, attenuation discontinued returned 0dB. soft mute effective changing signal source without stopping signal transmission. Soft mute function independent output volume cascade connected between both functions.
SMUTE 1024/fs Attenuation 1024/fs
LOUT ROUT
8192/fs
Figure Soft mute function Zero detection function output signal attenuated during 1024 LRCK cycles (1024/fs). Analog output delay from digital input called group delay (GD). soft mute cancelled within 1024 LRCK cycles, attenuation discontinued returned 0dB. When input data both channels continuously zeros 8192 LRCK cycles, goes "H". immediately goes input data channel zero after going "H".
Zero Detection Function
AK4584 channel-dependent zeros detect function. When input data both channels continuously zero 8192 LRCK cycles, each channel goes "H". each channel immediately goes input data each channel zero after "H". Zero detect function disabled DZFE bit. this case, always "L". When "L", always "L". "H", goes from "H". When PWVRN "0", "L". goes when RSTDAN becomes "0", then AK4584 reset after 4~5/fs goes 6~7/fs after RSTDAN becomes "1". after RSTDAN becomes within 5/fs, RSTDAN becomes "1", then AK4584 will properly reset. goes when PWDAN becomes "0", then AK4584 reset after 4~5/fs goes 6~7/fs after PWDAN becomes "1". PWDAN becomes "0", PWDAN becomes within 5/fs, then AK4584 will properly reset. When becomes PWDAN becomes RSTDAN becomes "1", 8192 counts start after 1/fs zero detect function.
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[AK4584]
Reset Power Down
AK4584 both power-down mode circuits pulling partial power-down mode that enabled internal register (see Table 22). AK4584 should reset once bringing upon power-up. PWDITN PWVRN PWADN PWDAN CM1-0 Function Power-down Power-down VREF Power-down Power-down Power-down X'tal Power-down Power-down Table Reset Power Down Register Initialization
Serial Control Interface
internal registers either written read 4-wire interface pins: CSN, CCLK, CDTI CDTO. data this interface consists Chip address (2bits, C1/0 fixed "00"), Read/Write (1bit), Register address (MSB first, 5bits) Control data (MSB first, 8bits). Address data clocked rising edge CCLK data clocked falling edge. write operations, data latched after 16th rising edge CCLK, after high-to-low transition CSN. read operations, CDTO output goes high impedance after low-to-high transition CSN. maximum speed CCLK 5MHz. chip address fixed "00". access chip address except "00" invalid. resets registers their default values.
CCLK
CDTI Write CDTO
Hi-Z
CDTI Read CDTO
Hi-Z Chip Address (Fixed "00") READ WRITE ("1" WRITE, READ) Register Address Control Data
Hi-Z
Figure Control Timing
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[AK4584]
Register
Addr Register Name Power Down Control Reset Control Clock Format Control Deem Volume Control IPGA Control IPGA Control OATT Control OATT Control In/Out Source Control Clock Mode Control Control Control INT0 Mask INT1 Mask Receiver Status Receiver Status Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte MSDTO IPGL7 IPGR7 ATTL7 ATTR7 OCKS1 MAT0 MAT1 AUTO CR15 CR23 CR31 CR39 CT15 CT23 CT31 CT39 PC15 PD15 SMUTE IPGL6 IPGR6 ATTL6 ATTR6 OCKS0 CS12 MDTS0 MDTS1 DTSCD CR14 CR22 CR30 CR38 CT14 CT22 CT30 CT38 PC14 PD14 DZFE IPGL5 IPGR5 ATTL5 ATTR5 DAC1 ICKS1 OPS1 TX3E MAN0 MAN1 AUDION CR13 CR21 CR29 CR37 CT13 CT21 CT29 CT37 PC13 PD13 TEST DIF2 ZCEI IPGL4 IPGR4 ATTL4 ATTR4 DAC0 ICKS0 OPS0 TX2E VDIR CR12 CR20 CR28 CR36 CT12 CT20 CT28 CT36 PC12 PD12 PWDITN DIF1 ZTM1 IPGL3 IPGR3 ATTL3 ATTR3 PCM1 IPS1 TX1E MPE0 MPE1 CR11 CR19 CR27 CR35 CT11 CT19 CT27 CT35 PC11 PD11 PWVRN DIF0 ZTM0 IPGL2 IPGR2 ATTL2 ATTR2 PCM0 IPS0 UDIT MUL0 MUL1 UNLOCK CR10 CR18 CR26 CR34 CT10 CT18 CT26 CT34 PC10 PD10 PWADN RSTADN DFS1 DEM1 IPGL1 IPGR1 ATTL1 ATTR1 DIT1 XTL1 EFH1 VDIT MPR0 MPR1 CR17 CR25 CR33 CT17 CT25 CT33 PWDAN RSTDAN DFS0 DEM0 IPGL0 IPGR0 ATTL0 ATTR0 DIT0 XTL0 EFH0 MFS0 MFS1 CR16 CR24 CR32 CT16 CT24 CT32
resets registers their default values.
Control Register Setup Sequence
When goes from upon power-up etc., AK4584 will ready normal operation next sequence. this case, control registers initial values AK4584 reset state. clock mode audio data interface mode. Cancel reset state setting RSTADN RSTDAN "1". Refer Control Register (01H). output output should muted externally until canceling each reset state, since master mode there possibility that frequency duty cycle LRCK BICK outputs become distorted. clock mode should changed after setting RSTADN RSTDAN "0". that time, outputs should muted externally since master mode, there possibility that frequency duty LRCK BICK outputs become distorted.
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[AK4584]
Register Definitions
Addr Register Name Power Down Control Default TEST PWDITN PWVRN PWADN PWDAN
PWDAN: Power Down Power down Power powers down only section then places LOUT ROUT immediately high-Z state. OATTs also "FFH". contents register initialized enabled write registers. After exiting power down mode, OATTs fade setting value control register (06H 07H). analog output should muted externally some noise occur when entering exiting from this mode. PWADN: Power Down Power down Power powers down only section then SDTO goes immediately. IPGAs also "00H". contents register initialized enabled write registers. After exiting power down mode, IPGAs fade setting value control register (04H 05H). that time, output during first LRCK cycles. PWVRN: VREF Power Down Power down Power powers down sections then both operate. contents register initialized enabled write registers. When PWADN PWDAN PWVRN goes "1", only VREF section powered PWDITN: Power Down Power down Power powers down only section. Therefore, output disabled output biphase signal. contents register initialized enabled write registers. TEST: TEST Must fixed
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[AK4584]
Addr
Register Name Reset Control Default
RSTADN
RSTDAN
RSTDAN: Reset Reset Normal Operation resets internal timing immediately drives LOUT ROUT VCOM voltage. OATTs "FFH". contents registers unaffected write-enabled. After exiting power down mode, OATTs fade based values control registers (06H 07H). analog outputs should muted externally some noise occur when entering exiting from this mode. RSTADN: Reset Reset Normal Operation resets internal timing SDTO immediately goes "L". IPGAs "00H". contents registers unaffected write-enabled. After exiting power down mode, IPGAs fade based values control registers (04H 05H). that time, output during first LRCK cycles.
Addr
Register Name Clock Format Control Default
DIF2
DIF1
DIF0
DFS1
DFS0
DFS1-0: Sampling Speed Control (see Table Initial values "00". DIF2-0: Audio Data Interface Modes (see Table Initial values "010" (24bit justified both DAC).
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[AK4584]
Addr
Register Name Deem Volume Control Default
MSDTO
SMUTE
DZFE
ZCEI
ZTM1
ZTM0
DEM1
DEM0
DEM1-0: De-emphasis Response (see Table Initial values "01" (OFF). ZTM1-0: Zero Crossing Time-out Period Select (see Table Initial values "10" (1024/fs). ZCEI: IPGA Zero Crossing Enable Input gain changes occur immediately Input gain changes occur only zero-crossing after timeout. Initial value (Enable). DZFE: Data Zero Detect Enable Disable Enable Zero detect function disabled DZFE bit. this case, always "L". Initial value (Disable). SMUTE: Input Soft Mute Control Normal operation outputs soft-muted soft mute independent output performed digitally. MSDTO: SDTO Mute Control Disable Enable When MSDTO "1", SDTO outputs "L". Initial value (Disable).
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[AK4584]
Addr
Register Name IPGA Control IPGA Control Default
IPGL7 IPGR7
IPGL6 IPGR6
IPGL5 IPGR5
IPGL4 IPGR4
IPGL3 IPGR3
IPGL2 IPGR2
IPGL1 IPGR1
IPGL0 IPGR0
IPGL/R7-0: Input Gain Level (see Table Initial value "7FH" (0dB). Digital with levels operates when writing data less than 7FH. This linear with 8032 levels internally these levels assigned pseudo-log data with levels. transition between values 8032 levels done soft changes. example, when changes from 126, internal value decreases from 8031 7775, every cycle. takes 8031 cycles (182ms@fs=44.1kHz) from (Mute). IPGAs "00H" when goes "L". After returning "H", IPGAs fade into initial value, "7FH" 8031 cycles. IPGAs "00H" when PWADN goes "0". After returning "1", IPGAs fade into current value. output during first cycles. IPGAs "00H" when RSTADN goes "0". After returning "1", IPGAs fade into current value. output during first cycles.
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[AK4584]
Data
Internal (DATT) 8031 7775 7519 4191 3999 3871 2079 1983 1919 1023
Gain (dB) +17.5 +1.0 +0.5 -0.28 -0.57 -5.65 -6.06 -6.34 -11.74 -12.15 -12.43 -17.90 -18.32 -18.61 -24.20 -24.64 -24.94 -30.82 -31.29 -31.61 -38.18 -38.73 -39.11 -47.73 -48.55 -49.15 -58.10 -60.03 -62.53 -66.05 -72.07 MUTE
Step width (dB) 0.28 0.29 0.51 0.41 0.28 0.52 0.41 0.28 0.53 0.42 0.29 0.54 0.43 0.30 0.58 0.46 0.32 0.67 0.54 0.38 0.99 0.83 0.60 1.58 1.94 2.50 3.52 6.02
IPGA Analog volume with 0.5dB step
IATT External levels converted internal 8032 linear levels DATT. Internal DATT soft-changes between data. DATT=2^m 3-bits data 4-bits data
Table IPGA Code Table
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[AK4584]
Addr
Register Name OATT Control OATT Control Default
ATTL7 ATTR7
ATTL6 ATTR6
ATTL5 ATTR5
ATTL4 ATTR4
ATTL3 ATTR3
ATTL2 ATTR2
ATTL1 ATTR1
ATTL0 ATTR0
ATTL/R7-0: OATT Level (see Table Initial value "FFH" (0dB). transition from initial final levels 7425 levels. takes 7424/fs (168ms@fs=44.1kHz) from FFH(0dB) 00H(MUTE). goes "L", ATTs initialized FFH. ATTs when PWDAN "0". When PWDAN returns "1", ATTs fade their current value. ATTs when RSTDAN "0". When RSTDAN returns "1", ATTs fade their current value. Digital attenuation independent soft mute function. ATTL/R7-0 Attenuation -0.5dB -1.0dB -1.5dB -126.5dB -127dB MUTE Table OATT Code Table
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[AK4584]
Addr
Register Name In/Out Source Control Default
DAC1
DAC0
PCM1
PCM0
DIT1
DIT0
DIT1-0:
Input Selector (see Table Initial values "00". When DIT1-0 bits "10", selected input sent output.
PCM1-0: Input Selector SDTO (see Table Initial values "00". PCM1 PCM0 Input Source SDTI Table Input Selector SDTO
Default
DAC1-0: Input Selector (see Table Initial values "00". DAC1 DAC0 Input Source SDTI Table Input Selector
Default
Addr
Register Name Clock Mode Control Default
OCKS1
OCKS0
ICKS1
ICKS0
XTL1
XTL0
XTL1-0: X'tal Frequency Select (see Table Initial values "00". CM1-0: Master Clock Operation Mode Select (see Table Initial values "01".
ICKS1-0: Master Clock Input Frequency Select X'tal Mode (see Table Initial values "00". 768fs supported external clock mode. OCKS1-0: Master Clock Output Frequency Select Mode (see Table Initial values "01".
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[AK4584]
Addr
Register Name Control Default
CS12
OPS1
OPS0
IPS1
IPS0
EFH1
EFH0
EFH1-0: Interrupt Hold Count Select (Table Initial values "01". LRCK Table DIR's LRCK, hold time scales with 1/fs. EFH1 EFH0 Hold Count 512LRCK 1024LRCK 2048LRCK 4096LRCK Table Hold Count Select
Default
IPS1-0:
Input Recovery Data Select (see Table Initial values "00".
OPS1-0: Output Through Data Select TX1/2 (see Table Initial values "00". CS12: Channel Status Select Channel Channel Selects which channel status used derive C-bit buffers, AUDION, PEM,
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[AK4584]
Addr
Register Name Control Default
TX3E
TX2E
TX1E
UDIT
VDIT
TCH: Channel Number Select Don't care (bit20-23 0000) Stereo (bit20-23 1000 channel, bit20-23 0100 channel) Automatically sets channel number (bit20-23 C-bit). Initial value "0". consumer mode (CT0 "0"), CT20-23 bits address cannot controlled directly. VDIT: V-bit Control Valid Invalid Initial value "0". UDIT: U-bit Control U-bit fixed "0". Recovered U-bit used DIT. (Loop mode U-bit) When unlocked U-bit "0". Initial value "1". TX1E: Output Enable Disable, outputs "L". Enable Initial value "1". TX2E: Output Enable Disable, outputs "L". Enable Initial value "1". TX3E: Output Enable Disable, outputs "L". Enable Initial value "1".
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[AK4584]
Addr
Register Name INT0 Mask Default
MAT0
MDTS0
MAN0
MPE0
MUL0
MPR0
MFS0
MFS0: Mask Enable Mask disable Mask enable MPR0: Mask Enable Mask disable Mask enable MUL0: Mask Enable UNLOCK Mask disable Mask enable MPE0: Mask Enable Mask disable Mask enable MV0: Mask Enable VDIR Mask disable Mask enable MAN0: Mask Enable AUDION Mask disable Mask enable MDTS0: Mask Enable DTSCD Mask disable Mask enable MAT0: Mask Enable AUTO Mask disable Mask enable
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[AK4584]
Addr
Register Name INT1 Mask Default
MAT1
MDTS1
MAN1
MPE1
MUL1
MPR1
MFS1
MFS1: Mask Enable Mask disable Mask enable MPR1: Mask Enable Mask disable Mask enable MUL1: Mask Enable UNLOCK Mask disable Mask enable MPE1: Mask Enable Mask disable Mask enable MV1: Mask Enable VDIR Mask disable Mask enable MAN1: Mask Enable AUDION Mask disable Mask enable MDTS1: Mask Enable DTSCD Mask disable Mask enable MAT1: Mask Enable AUTO Mask disable Mask enable
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[AK4584]
Addr
Register Name Receiver Status Default
AUTO
DTSCD
AUDION
VDIR
UNLOCK
Sampling Frequency Status change Change This when FS3-0 bits changed. When this address read, this reset. PAR: Parity Error Bi-phase Error Status error Error This Parity Error Biphase Error detected sub-frame. When this address read, this reset. UNLOCK: Lock Status Lock Unlock When this address read, this reset. PEM: Pre-emphasis Output This made encoding channel status bits. When this address read, this reset. VDIR: Validity Valid Invalid When this address read, this reset. AUDION: Audio Output Audio audio This made encoding channel status bits. When this address read, this reset. DTSCD: DTS-CD Auto Detect detect Detect When this address read, this reset. AUTO: Non-PCM Auto Detect detect Detect When this address read, this reset.
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[AK4584]
Addr
Register Name Receiver Status Default
FS3-0:
Sampling Frequency Detection (see Table Initial values "0000".
Addr
Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default
CR15 CR23 CR31 CR39
CR14 CR22 CR30 CR38
CR13 CR21 CR29 CR37
CR12 CR20 CR28 CR36
CR11 CR19 CR27 CR35
CR10 CR18 CR26 CR34
CR17 CR25 CR33
CR16 CR24 CR32
Initialized
CR39-0:
Receiver Channel Status Byte
Addr
Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default
CT15 CT23 CT31 CT39
CT14 CT22 CT30 CT38
CT13 CT21 CT29 CT37
CT12 CT20 CT28 CT36
CT11 CT19 CT27 CT35
CT10 CT18 CT26 CT34
CT17 CT25 CT33
CT16 CT24 CT32
CT39-0:
Transmitter Channel Status Byte consumer mode (CT0 "0"), bit20-23 (Audio channel) cannot controlled directly.
Addr
Register Name Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Default
PC15 PD15
PC14 PD14
PC13 PD13
PC12 PD12
PC11 PD11
PC10 PD10
Initialized
PC15-0: PD15-0:
Burst Preamble Byte Burst Preamble Byte
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[AK4584]
SYSTEM DESIGN
Figure shows system connection diagram. evaluation board available which demonstrates application circuits, optimum layout, power supply arrangements measurement results. [Measurement Condition] TVDD 3.0V, Master mode, XTALE "H", DMCK
S/PDIF sources
Shield 0.1µ Shield TEST2 TEST1 PVSS PVDD
Analog
0.1µ VREF AVDD AVSS ROUT LOUT VCOM
MUTE MUTE
Shield
0.1µ
2.2µ
Control
INT0 INT1
AK4584
LRCK BICK SDTI SDTO MCKO2 XTI/MCKI MCKO1 DMCK
CDTI CDTO CCLK XTALE TEST3 DVDD TVDD DVSS
Audio
0.1µ 0.1µ
S/PDIF
Digital
Note: X'tal Oscillation circuit specified from 11.2896MHz 24.576MHz. Capacitors depend X'tal. AGND DGND AK4584 should distributed separately from ground external digital devices (MPU, etc.). When LOUT/ROUT drives capacitive load, resistors should added series between LOUT/ROUT capacitive load. input pins except pull-down (TEST1,2 pins) should left floating. prevent coupling TEST1, TEST2 signals, pins connected PVSS. Figure Typical Connection Diagram
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[AK4584]
Grounding Power Supply Decoupling AK4584 requires careful attention power supply grounding arrangements. AVDD, DVDD PVDD usually supplied from analog supply system. Alternatively AVDD, DVDD PVDD supplied separately, power sequence critical. TVDD power supply interface with external supplied from digital supply system. AVSS, DVSS PVSS AK4584 must connected analog ground plane. System analog ground digital ground should connected together near where supplies brought onto printed circuit board. Decoupling capacitors should near AK4584 possible, with small value ceramic capacitor being nearest. Voltage Reference Inputs differential voltage between VREF AVSS sets analog input/output range. VREF normally connected AVDD with 0.1µF ceramic capacitor. VCOM signal ground this chip. electrolytic capacitor 2.2µF parallel with 0.1µF ceramic capacitor attached VCOM eliminates effects high frequency noise. load current drawn from VCOM pin. signals, especially clocks, should kept away from VREF VCOM pins order avoid unwanted coupling into AK4584. Analog Inputs inputs single-ended input resistance (typ). input signal range scales with supply voltage nominally VREF (typ). Usually input signal coupled with capacitor. cut-off frequency 1/(2RC). AK4584 accept input voltages from AVSS AVDD. output data format compliment. internal removes offset. AK4584 samples analog inputs 64fs. digital filter rejects noise above stop band except multiples 64fs. AK4584 includes anti-aliasing filter filter) attenuate noise around 64fs. Analog Outputs analog outputs single-ended centered around VCOM voltage. input signal range scales with supply voltage, nominally VREF Vpp. input data format complement. output voltage positive full scale 7FFFFFH(@24bit) negative full scale 800000H(@24bit). ideal output 000000H(@24bit). internal analog filters remove most out-of-band noise generated DAC's delta-sigma modulator. depends X'tal (typ. 40pF). When external clock supplied, left floating clock source connected pin. input voltage should exceed DVDD. When applying CMOS level signal pin, when XTALE "L", fixed "L". means that accept CMOS level clock well level clock. only restriction this clock high level must equal greater than DVDD, exceed DVDD. value clock must DVDD lower, drop below DGND. When pins used, leave floating connect DVSS.
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2001/11
[AK4584]
PACKAGE
44pin LQFP (Unit: 12.80 0.30 10.00
1.70max
12.80 0.30
0.80
10.00
0.37 0.10
0.17 0.05
0.15
0.60 0.20
Material Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Solder free) plate
MS0118-E-00
2001/11
[AK4584]
MARKING
AK4584VQ XXXXXXX
XXXXXXX Date Code Identifier digits)
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
MS0118-E-00
2001/11

AK4584 24Bit 96kHz Audio CODEC with DIT/DIR GENERAL DESCRIPT

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