HYMD564M646A(L)6-D43/D4/J Document Title 64Mx64 bits Unbuffered S
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Unbuffered SO-DIMM
HYMD564M646A(L)6-D43/D4/J
Document Title 64Mx64 bits Unbuffered SO-DIMM Revision History
Initial draft Reflected "notational" change module thickness page Real Corrected some typos History Draft Date Oct. 2003 Apr. 2004 Remark
This document general product description subject change without notice. Hynix Semiconductor does assume responsibility circuits described. patent licenses implied. Rev. Apr. 2004
Unbuffered SO-DIMM
HYMD564M646A(L)6-D43/D4/J
DESCRIPTION
Preliminary
Hynix HYMD564M646A(L)6-D43/D4/J series unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which organized 64Mx64 high-speed memory arrays. Hynix HYMD564M646A(L)6-D43/D4/J series consists eight 32Mx16 SDRAM 400mil TSOP packages 200pin glass-epoxy substrate. Hynix HYMD564M646A(L)6-D43/D4/J series provide high performance 8-byte interface 67.60mmX 31.75mm form factor industry standard. suitable easy interchange addition. Hynix HYMD564M646A(L)6-D43/D4/J series designed high speed 200MHz offers fully synchronous operations referenced both rising falling edges differential clock inputs. While addresses control inputs latched rising edges clock, Data, Data strobes Write data masks inputs sampled both rising falling edges data paths internally pipelined 2-bit prefetched achieve very high bandwidth. input output voltage levels compatible with SSTL_2. High speed frequencies, programmable latencies burst lengths allow variety device operation high performance memory system. Hynix HYMD564M646A(L)6-D43/D4/J series incorporates SPD(serial presence detect). Serial presence detect function implemented serial 2,048-bit EEPROM. first bytes serial data programmed Hynix identify DIMM type, capacity other information DIMM last bytes available customer.
FEATURES
200-pin small outline dual in-line memory module(SO-DIMM) 2.6V +/-0.1V VDDQ Power supply Double data rate architecture; data accesses clock cycle Differential Clock inputs /CK) Data inputs centers when write (centered Bidirectional data strobes synchronized with output data read input data write Programmable Latency (clock) DDR400, (clock) DDR333 Programmable Burst Length 2/4/8 with both sequential interleave mode Internal four bank operations with single pulsed Auto Self refresh mode 8192 refresh cycles /64ms
ORDERING INFORMATION
Part
HYMD564M646A(L)6-D43 VDD,VDDQ=2.6V HYMD564M646A(L)6-D4 HYMD564M646A(L)6-J VDD,VDDQ=2.5V 200MHz (*DDR400) 166MHz (*DDR333) 3-4-4 2.5-3-3
JEDEC Defined Specifications compliant
Power Supply
Clock Frequency
200MHz (*DDR400)
CL-tRCD-tRP
3-3-3
Form Pactor
200pin Unbuffered SO-DIMM 67.6mm 31.75mm
This document general product description subject change without notice. Hynix Semiconductor does assume responsibility circuits described. patent licenses implied. Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
DESCRIPTION
CK0, /CK0, CK1, /CK1 CS0, CKE0, CKE1 /RAS, /CAS, BA0, DQ0~DQ63 DQS0~DQS7 DM0~DM7 Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply VDDQ VREF VDDSPD SA0~SA2 VDDID Description Power Supply Ground Reference Power Supply Power Supply E2PROM Address Inputs E2PROM Clock E2PROM Data Identification Flag Connection
ASSIGNMENT
Name VREF DQS0 DQS1 DQ10 DQ11 /CK0 DQ16 DQ17 DQS2 DQ18 Name VREF DQ12 DQ13 DQ14 DQ15 DQ20 DQ21 DQ22 Name DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 CKE1 Name DQ23 DQ28 DQ29 DQ30 DQ31 CKE0 Name A10/AP /CS0 DQ32 DQ33 DQS4 DQ34 DQ35 DQ40 DQ41 DQS5 Name /RAS /CAS /CS1 DQ36 DQ37 DQ38 DQ39 DQ44 DQ45 Name DQ42 DQ43 DQ48 DQ49 DQS6 DQ50 DQ51 DQ56 DQ57 DQS7 DQ58 DQ59 VDDSPD VDDID Name DQ46 DQ47 /CK1 DQ52 DQ53 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
FUNCTIONAL BLOCK DIAGRAM
/CS1
/CS0
DQS0
LDQS UDQS
LDQS UDQS
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS1
DQS5
LDQS UDQS
LDQS UDQS
DQS2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS3
LDQS UDQS
LDQS UDQS
DQS6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS7
LDQS UDQS
LDQS UDQS
Serial
VDDSPD
VDD/VDDQ
VREF VDDID
Strap:see Note
BA0-BA1 /RAS /CAS CKE0 CKE1
SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs SDRAMz
Notes: wiring differ from that described this drawing however DQ/DM/DQS relationship maintained shown. VDDID strap connections; (for memory device VDD, VDDQ) Strap :(open) VDD=VDDQ Strap (Vss) VDD= VDDQ
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature (Ambient) Storage Temperature Voltage relative Voltage relative Voltage VDDQ relative Output Short Circuit Current Power Dissipation Soldering Temperature Time TSTG VIN, VOUT VDDQ TSOLDER Symbol -0.5 -0.5 -0.5 Components Rating
Unit
Note Operation above absolute maximum rating adversely affect device reliability
OPERATING CONDITIONS (TA=0 Voltage referenced VSS=
Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Voltage Termination Voltage Reference Voltage VDDQ VREF Symbol VREF 0.15 -0.3 VREF 0.04 0.49*VDDQ Typ. VREF 0.5*VDDQ VDDQ VREF 0.15 VREF 0.04 0.51*VDDQ Unit Note
Note VDDQ must exceed level VDD. (min) acceptable -1.5V pulse width with duration. value VREF approximately equal 0.5VDDQ.
OPERATING CONDITIONS (TA=0 Voltage referenced
Parameter Input High (Logic Voltage, signals Input (Logic Voltage, signals Input Differential Voltage, inputs Input Crossing Point Voltage, inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.5*VDDQ-0.2 VREF 0.31 VREF 0.31 VDDQ 0.5*VDDQ+0.2 Unit Note
Note magnitude difference between input level input /CK. value expected equal 0.5*V transmitting device must track variations level same.
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
OPERATING TEST CONDITIONS (TA=0 70oC, Voltage referenced
Parameter Reference Voltage Termination Voltage Input High Level Voltage (VIH, min) Input Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance Access Time Measurement (CL) Value VDDQ VDDQ VREF 0.31 VREF 0.31 VREF Unit V/ns
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
CAPACITANCE (TA=25oC, f=100MHz
Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Data Input Output Capacitance A12, BA0, /RAS, /CAS, CKE0, CKE1 /CS0, /CS1 CK0, /CK0, CK1, /CK1 DQ63, DQS0 DQS7 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIO1 Unit
Note min. max., VDDQ 2.5V 2.7V, VODC VDDQ/2, VOpeak-to-peak 0.2V Pins under test tied GND. These values guaranteed design tested sample basis only.
OUTPUT LOAD CIRCUIT
RT=50
Output
Zo=50 VREF
CL=30pF
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
CHARACTERISTICS (TA=0 70oC, Voltage referenced
Parameter
Add, CMD, /CS, /CKE
Symbol
Min.
0.76
Unit
Note
Input Leakage Current
CK0, /CK0, CK1, /CK1 CK2, /CK2
Output Leakage Current Output High Voltage Output Voltage
0.76
-15.2mA +15.2mA
Note 3.6V, other pins tested under DOUT disabled, VOUT=0 2.7V
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
CHARACTERISTICS (TA=0 70oC, Voltage referenced
Parameter Symbol Test Condition
bank; Active Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM inputs changing twice clock cycle address control inputs changing once clock cycle bank; Active Read Precharge; Burst Length tRC=tRC(min); tCK=tCK(min); address control inputs changing once clock cycle banks idle; Power down mode; CKE=Low, tCK= tCK(min) Vin>=Vih(min) Vin=<Vil(max) /CS=High, banks idle; tCK=tCK(min); CKE= High; address control inputs changing once clock cycle. VIN=VREF /CS>=Vih(min); banks idle; CKE>=Vih(min); Addresses other control inputs stable, Vin=Vref bank active Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); inputs changing twice clock cycle; Address other control inputs changing once clock cycle Burst=2; Reads; Continuous burst; bank active; Address control inputs changing once clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; bank active; Address control inputs changing once clock cycle; tCK=tCK(min); inputs changing twice clock cycle tRC=tRFC(min) 8*tCK DDR200 100Mhz, 10*tCK DDR266A DDR266B 133Mhz; distributed refresh CKE=<0.2V; External clock =tCK(min) Normal Power
2200
Speed
Unit Note
Operating Current
IDD0
Operating Current Precharge Power Down Standby Current Idle Standby Current Idle Standby Current
IDD1
IDD2P
IDD2N
IDD2F
Idle Quiet Standby Current Active Power Down Standby Current
IDD2Q
IDD3P
Active Standby Current
IDD3N
Operating Current
IDD4R
1120
1040
Operating Current
IDD4W
1120
1040
Auto Refresh Current
IDD5
1240
1080
1880
Self Refresh Current Operating Current Four Bank Operation
IDD6
IDD7
Four bank interleaving with BL=4 Refer following page detailed test condition 4banks active read with activate every 20ns, AP(Auto Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 100% inputs changing twice clock cycle; 100% addresses changing once clock cycle
Random Read Current
IDD7A
2200
1880
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Cycle Time Auto Refresh Cycle Time Active Time Active Read with Auto Precharge Delay Address Column Address Delay Active Active Delay Column Address Column Address Delay Precharge Time Write Recovery Time Write Read Command Delay Auto Precharge Write Recovery+Precharge Time CL=3 System Clock Cycle Time Clock High Level Width Clock Level Width Data-Out edge Clock edge Skew DQS-Out edge Clock edge Skew DQS-Out edge Data-Out edge Skew Data-Out hold time from Clock Half Period Data Hold Skew Factor Data-out high-impedance window from Data-out low-impedance window from Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Rev. Apr. 2004 tDQSCK tDQSQ tQHS tIPW (Min) Symbol tRFC tRAS tRAP tRCD tRRD tCCD tWTR tDAL D43(DDR400) tRCD tRASmin (tWR/tCK)+ (tRP/tCK) 0.45 0.45 -0.7 -0.55 tHPmin -tQHS tCH/L 0.55 0.55 0.55 (Max) (Max) (Min) D4(DDR400) tRCD tRASmin (tWR/tCK)+ (tRP/tCK) 0.45 0.45 -0.7 -0.55 tHPmin -tQHS tCH/L 0.55 0.55 0.55 (Max) (Max) J(DDR333) tRCD tRASmin (tWR/tCK)+ (tRP/tCK) 0.45 0.45 -0.7 -0.55 tHPmin -tQHS tCH/L -0.7 -0.7 0.75 0.75 0.55 0.55 0.55 0.45 0.55 Unit Note
2,3,5, 2,3,5, 2,4,5, 2,4,5,
HYMD564M646A(L)6-D43/D4/J
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Write High Level Width Write Level Width Clock First Rising edge DQS-In Data-In Setup Time DQS-In Data-in Hold Time DQS-In Input Pulse Width Read Preamble Time Read Postamble Time Write Preamble Setup Time Write Preamble Hold Time Write Postamble Time Mode Register Delay Exit Self Refresh Execute Command Average Periodic Refresh Interval Note This calculation accounts tDQSQ(max), pulse width distortion on-chip circuit jitter. Data sampled rising edges clock A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. command/address input slew rate >=1.0V/ns command/address input slew rate >=0.5V/ns <1.0V/ns This derating table used increase tIS/tIH case where input slew-rate below 0.5V/ns. Input Setup Hold Slew-rate Derating Table. Input Setup Hold Slew-rate V/ns slew rates >=1.0V/ns These parameters guarantee device timing, they necessarily tested each device, they guaranteed design tester correlation Data latched both rising falling edges Data Strobes(LDQS/UDQS) LDM/UDM. Minimum cycles stable input clocks after Self Refresh Exit command, where held high, required complete Self Refresh Exit lock internal circuit SDRAM. (tCL, tCH) refers smaller actual clock time actual clock high time provided device (i.e. this value greater than minimum specification limits tCH). Delta +100 Delta Symbol tDQSH tDQSL tDQSS tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI D43(DDR400) 0.35 0.35 0.72 0.25 1.28 D4(DDR400) 0.35 0.35 0.72 0.25 1.28 J(DDR333)
Unit Note
continued
0.35 0.35 0.75 0.45 0.45 1.75 0.25
1.25 6,7, 11~13 6,7, 11~13
minimum half clock period given cycle defined clock high clock (tCH, tCL). tQHS consists tDQSQmax, pulse width distortion on-chip clock circuits, data skew output pattern effects p-channel n-channel variation output drivers. Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
11.This derating table used increase tDS/tDH case where input slew-rate below 0.5V/ns. Input Setup Hold Slew-rate Derating Table. Input Setup Hold Slew-rate V/ns Delta +150 Delta +150
Setup/Hold Plateau Derating. This derating table used increase tDS/tDH case where input level flat below VREF +/-310mV duration 2ns. Input Level +280 Delta Delta
Setup/Hold Delta Inverse Slew Rate Derating. This derating table used increase tDS/tDH case where slew rates differ. Delta Inverse Slew Rate calculated (1/SlewRate1)-(1/SlewRate2). example, slew rate 0.5V/ns Slew Rate2 0.4V/n then Delta Inverse Slew Rate -0.5ns/V. (1/SlewRate1)-(1/SlewRate2) ns/V +/-0.25 Delta +100 Delta +100
DQS, input slew rate specified prevent double clocking data preserve setup hold times. Signal transi tions through region must monotonic. tDAL (tDPL (tRP each terms above, already integer, round next highest integer. equal actual system clock cycle time. Example: DDR400(D4) CL=3 tDAL (15.0 (18.0ns 5.0ns) (3.00) (3.60) Round each non-integer next highest integer: (4), tDAL 7clock parts which internal lockout circuit, Active Read with Auto precharge delay should tRAS BL/2 tCK.
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
SIMPLIFIED COMMAND TRUTH TABLE
Command Extended Mode Register Mode Register Device Deselect Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit Precharge Power Down Mode Entry Exit Active Power Down Mode (Clock Suspend) Entry Exit CKEn-1 CKEn /RAS /CAS
ADDR
A10/ code code
Note
H=Logic High Level, L=Logic Level, X=Don't Care, V=Valid Data Input, Code=Operand Code, NOP=No Operation Note LDM/UDM states Don't Care. Refer below Write Mask Truth Table. Code(Operand Code) consists A0~A12 BA0~BA1 used Mode Registering duing Extended MRS. Before entering Mode Register mode, banks must precharge state command issued after period from Prechagre command. Read with Autoprecharge command detected memory component CK(n), then there will command presented activated bank until CK(n+BL/2+tRP). Write with Autoprecharge command detected memory compoment CK(n), then there will command presented activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In Prechage delay(tDPL) which also called Write Recovery Time (tWR) needed guarantee that last data been completely written. A10/AP High when Precharge command being issued, BA0/BA1 ignored banks selected precharged.
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
PACKAGE DIMENSIONS
Front
2.00 Component Keepout Area
67.60
2.00
31.75
20.00
Back
Side
3.8mm MAX.
(Front)
1.1mm MAX.
Rev. Apr. 2004
SERIAL PRESENCE DETECT
SPECIFICATION
(64Mx64 Unbuffered SO-DIMM)
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
SERIAL PRESENCE DETECT
Byte# Function Description Number Bytes written into serial memory module manufacturer Total number Bytes device Fundamental memory type Number address this assembly Number column address this assembly Number physical banks DIMM Module data width Module data width (continued) Module voltage Interface levels(VDDQ) SDRAM cycle time Latency=2.5(tCK) SDRAM access time from clock CL=2.5 (tAC) Module configuration type Refresh rate type Primary SDRAM width Error checking SDRAM data width Minimum clock delay back-to-back random column address(tCCD) Burst lengths supported Number banks each SDRAM latency supported latency latency SDRAM module attributes SDRAM device attributes General 5.0ns Sort D43(DDR400@CL=3, D4(DDR400@CL=3), J(DDR333@CL=2.5) Function Supported Bytes Bytes SDRAM 2Bank Bits SSTL 2.5V 5.0ns +/-0.7ns Non-ECC 7.8us Self refresh 2,4,8 Banks 2.5, Differential Clock Input +/-0.2Voltage tolerance, Concurrent Auto Precharge tRAS Lock 6.0ns 7.5ns +/-0.75ns 15ns 10ns 15ns 40ns 0.60ns 0.60ns 0.40ns 0.40ns 55ns 70ns 10ns 0.40ns 0.50ns 18ns 10ns 18ns 40ns 256MB 0.60ns 0.60ns 0.40ns 0.40ns Undefined 58ns 70ns 10ns 0.40ns 0.50ns Undefined Initial release 60ns 72ns 12ns 0.45ns 0.55ns 0.75ns 0.75ns 0.45ns 0.45ns 6.0ns +/-0.7ns 7.5ns 6.0ns Hexa Value
Note
SDRAM cycle time CL=2.0(tCK) SDRAM access time from clock CL=2.0(tAC) SDRAM cycle time CL=1.5(tCK) SDRAM access time from clock CL=1.5(tAC) Minimum precharge time(tRP) Minimum activate active delay(tRRD) Minimum delay(tRCD) Minimum active precharge time(tRAS) Module density Command address signal input setup time(tIS) Command address signal input hold time(tIH) Data signal input setup time(tDS) Data signal input hold time(tDH) Minimum active auto-refresh Time (tRC) Minimum auto-refresh active auto-refresh command period (tRFC) Maximum cycle time (tCK max) Maximum DQS-DQ skew time (tDQSQ) Maximum read data hold skew factor (tQHS) Revision code Checksum Bytes 0~62
18ns 12ns 18ns 42ns
36~40 Reserved VCSDRAM
46~61 Superset Information(may used future)
Rev. Apr. 2004
HYMD564M646A(L)6-D43/D4/J
SERIAL PRESENCE DETECT(continued)
Byte 65~71 Function Description Manufacturer JEDEC Code Manufacturer JEDEC Code Function Supported Hynix(Korea Area) HSA(United States Area) HSE(Europe Area) HSJ(Japan Area) Singapore Asia Area 6(8K refresh,4Bank) Blank Blank Undefined Undefined Blank Blank Hexa Value Note
Hynix JEDEC
Manufacturing location
95~98 99~127 128~255
Manufacture part number(Hynix Memory Module) Manufacture part number(Hynix Memory Module) Manufacture part number(Hynix Memory Module) Manufacture part number (DDR SDRAM) Manufacture part number(Memory density) Manufacture part number(Module Depth) Manufacture part number(Module Depth) Manufacture part number(Module type) Manufacture part number(Data width) -Manufacture part number(Data width) Manufacture part number(Refresh, Bank.) Manufacture part number(Component Generation) Manufacture part number(Component configuration) Manufacture part number(Hyphen) Manufacture part number(Minimum cycle time) Manufacture part number(Minimum cycle time) Manufacture part number(Minimum cycle time) Manufacture part number(T.B.D) Manufacture revision code(for Component) Manufacture revision code (for PCB) Manufacturing date(Year) Manufacturing date(Week) Module serial number Manufacturer specific data (may used future) Open customer
Note bank address excluded These value based component specification These bytes programmed code date week date year These bytes apply Hynix's Module Serial Number system These bytes undefined coded `00h' Refer Hynix site
Byte 85~86, power part
Byte# Function Description Manufacture part number(Low power part) Manufacture part number(Component Configuration) Function Supported Hexa Value Note
Rev. Apr. 2004
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