DESCRIPTIO 2.8Msps Conversion Rate Power Dissipation: 14mW Single
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LTC1403/LTC1403A Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown
DESCRIPTIO
2.8Msps Conversion Rate Power Dissipation: 14mW Single Supply Operation 2.5V Internal Bandgap Reference Overdriven 3-Wire Serial Interface Sleep (10µW) Shutdown Mode (3mW) Shutdown Mode 80dB Common Mode Rejection 2.5V Unipolar Input Range Tiny 10-Lead Package
LTC1403/LTC1403A 12-bit/14-bit, 2.8Msps serial ADCs with differential inputs. devices draw only 4.7mA from single supply come tiny 10-lead package. Sleep shutdown feature lowers power consumption 10µW. combination speed, power tiny package makes LTC1403/LTC1403A suitable high speed, portable applications. 80dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. devices convert 2.5V unipolar inputs differentially. absolute voltage swing +AIN -AIN extends from ground supply voltage. serial interface sends conversion results during clock cycles following CONV compatibility with standard serial interfaces. additional clock cycles acquisition time allowed after data stream between conversions, full sampling rate 2.8Msps achieved with 50.4MHz clock.
registered trademarks Linear Technology Corporation.
APPLICATIO
Communications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control Multiplexed Data Acquisition
BLOCK DIAGRA
10µF
LTC1403A AIN+ AIN-
THREESTATE SERIAL OUTPUT PORT
14-BIT
THD, 2nd, SFDR, (dB)
14-BIT LATCH
VREF 2.5V REFERENCE
10µF
TIMING LOGIC EXPOSED
CONV
1403A TA01
-104
2nd, SFDR Input Frequency
FREQUENCY (MHz)
1403A TA02
2nd, SFDR
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LTC1403/LTC1403A
ABSOLUTE
(Notes
RATI
PACKAGE/ORDER ATIO
ORDER PART NUMBER
VIEW AIN+ AIN- VREF CONV
Supply Voltage (VDD) Analog Input Voltage (Note .-0.3V (VDD 0.3V) Digital Input Voltage 0.3V (VDD 0.3V) Digital Output Voltage 0.3V (VDD 0.3V) Power Dissipation 100mW Operation Temperature Range LTC1403C/LTC1403AC 70°C LTC1403I/LTC1403AI 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
LTC1403CMSE LTC1403IMSE LTC1403ACMSE LTC1403AIMSE PART MARKING LTBDN LTBDP LTADF LTAFD
PACKAGE 10-LEAD PLASTIC MSOP TJMAX 125°C, 150°C/ EXPOSED (PIN MUST SOLDERED
Consult Marketing parts specified with wider operating temperature ranges.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Offset Error Gain Error Gain Tempco (Notes (Notes (Note CONDITIONS
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With internal reference.
LTC1403 ±0.25
LTC1403A ±0.5
UNITS Bits ppm/°C ppm/°C
Internal Reference (Note External Reference
ALOG
SYMBOL PARAMETER tACQ tJITTER CMRR
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C.
CONDITIONS 2.7V 3.3V
UNITS
Analog Differential Input Range (Notes Analog Common Mode Differential Input Range (Note Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
(Note
1MHz, 100MHz,
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LTC1403/LTC1403A
ACCURACY
SYMBOL SINAD PARAMETER Signal-to-Noise Plus Distortion Ratio
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C.
CONDITIONS 100kHz Input Signal 1.4MHz Input Signal 100kHz Input Signal, External VREF 3.3V, 3.3V 750kHz Input Signal, External VREF 3.3V, 3.3V 100kHz First Harmonics 1.4MHz First Harmonics 100kHz Input Signal 1.4MHz Input Signal 1.25V 2.5V 1.25MHz into AIN+ 1.25V, 1.2MHz into AIN- VREF 2.5V (Note 2.5VP-P, 11585LSBP-P (Note S/(N 68dB
SFDR
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time CONDITIONS IOUT
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C.
2.7V 3.6V, VREF 2.5V Load Current 0.5mA UNITS ppm/°C µV/V
DIGITAL PUTS DIGITAL OUTPUTS
SYMBOL ISOURCE ISINK PARAMETER High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current VOUT VOUT CONDITIONS 3.3V 2.7V
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C.
LTC1403 70.5 70.5 0.25
LTC1403A 73.5 73.5 76.3 76.3
UNITS LSBRMS
Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth
UNITS
IOUT 200µA 2.7V, IOUT 160µA 2.7V, IOUT 1.6mA VOUT
0.05 0.10
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LTC1403/LTC1403A
POWER REQUIRE
SYMBOL PARAMETER Supply Voltage Positive Supply Voltage
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS Active Mode Mode Sleep Mode (LTC1403) Sleep Mode (LTC1403A) Active Mode with Fixed State
Power Dissipation
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C.
SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV PARAMETER Maximum Sampling Frequency Channel (Conversion Rate) Minimum Sampling Period (Conversion Acquisiton Period) Clock Period Conversion Time Minimum Positive Negative SCLK Pulse Width CONV Setup Time Nearest Edge Before CONV Minimum Positive Negative CONV Pulse Width Sample Mode CONV Hold Mode 16th CONV Interval (Affects Acquisition Period) Minimum Delay from Valid Bits Through Hi-Z Previous Remains Valid After VREF Settling Time After Sleep-to-Wake Transition (Note (Note (Note (Notes (Note (Note (Note (Notes (Notes (Notes (Notes (Notes (Notes CONDITIONS
CHARACTERISTICS
Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect GND. Note When these pins taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below greater than without latchup. Note Offset full-scale specifications measured singleended AIN+ input with AIN- grounded using internal 2.5V reference. Note Integral linearity tested with external 2.55V reference defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Guaranteed design, subject test. Note Recommended operating conditions. Note analog input range defined voltage difference between AIN+ AIN-. Note absolute voltage AIN+ AIN- must within this range. Note less than allowed, output data will appear clock
UNITS
UNITS
19.8 10000
SCLK cycles
cycle later. best CONV rise half clock before SCK, when running clock rated speed. Note same aperture delay. Aperture delay smaller (1ns) because 2.2ns delay through sample-and-hold subtracted from CONV Hold mode delay. Note rising edge guaranteed catch data coming into storage latch. Note time period acquiring input signal started 16th rising clock ended rising edge convert. Note internal reference settles after wakes from Sleep mode with more cycles 10µF capacitive load. Note full power bandwidth frequency where output code swing drops with 2.5VP-P input sine wave. Note Maximum clock period guarantees analog performance during conversion. Output data read without arbitrarily long clock. Note fSAMPLE 2.8Msps. Note LTC1403A measured specified with 14-bit Resolution (1LSB 152µV) LTC1403 measured specified with 12-bit Resolution (1LSB 610µV).
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LTC1403/LTC1403A TYPICAL PERFOR CHARACTERISTICS
ENOBs SINAD Input Frequency
12.0 11.5 11.0 FREQUENCY (MHz)
1403A
10.0
-104 FREQUENCY (MHz)
1403A
SFDR (dB)
10.5
THD, 2nd, (dB)
ENOBs (BITS)
Input Frequency
MAGNITUDE (dB)
(dB)
FREQUENCY (MHz)
1403A
-100 -110 -120 350k 700k 1.05M FREQUENCY (Hz) 1.4M
1403A
MAGNITUDE (dB)
1.4MHz Input Summed with 1.56MHz Input 4096 Point Plot
DIFFERENTIAL LINEARITY (LSB)
2.8Msps
INTEGRAL LINEARITY (LSB)
MAGNITUDE (dB)
-100 -110 -120 350k 700k 1.05M FREQUENCY (Hz) 1.4M
1403A
25°C, (LTC1403A)
THD, Input Frequency
SFDR Input Frequency
SINAD (dB)
FREQUENCY (MHz)
1403A
98kHz Sine Wave 4096 Point Plot
2.8Msps -100 -110 -120
1.3MHz Sine Wave 4096 Point Plot
2.8Msps
350k
700k 1.05M FREQUENCY (Hz)
1.4M
1403A
Differential Linearity Output Code
-0.2 -0.4 -0.6 -0.8 -1.0 4096 8192 12288 OUTPUT CODE 16383
1403A
Integral Linearity Output Code
4096 8192 12288 OUTPUT CODE 16383
1403A
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LTC1403/LTC1403A TYPICAL PERFOR CHARACTERISTICS
Differential Integral Linearity Conversion Rate
LINEARITY (LSB) CONVERSION RATE (Msps)
1403A
CLOCKS CONVERSION
S/(N+D)
25°C, (LTC1403 LTC1403A) 2.5VP-P Power Bandwidth
AMPLITUDE (dB)
CMRR (dB)
PSRR (dB)
100M FREQUENCY (Hz)
1403A
Reference Voltage Load Current
2.4902 2.4900 2.4898 2.4902 2.4900 2.4898
SUPPLY CURRENT (mA)
VREF
VREF
2.4896 2.4894 2.4892 2.4890 LOAD CURRENT (mA)
1403A
25°C, (LTC1403A)
SINAD Conversion Rate
INTERNAL 2.5V fIN~fS/40 INTERNAL VREF 2.5V fIN~fS/3 CONVERSION RATE (Msps)
1403A
EXTERNAL VREF 3.3V fIN~fS/3 EXTERNAL VREF 3.3V fIN~fS/40
CMRR Frequency
PSRR Frequency
-100
-120
100k FREQUENCY (Hz)
100M
FREQUENCY (Hz) 100k
1403A
1403A
Reference Voltage
2.4890
1403A
Supply Current Conversion Rate
2.4896 2.4894 2.4892
CONVERSION RATE (Msps)
1403A
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LTC1403/LTC1403A
CTIO
AIN+ (Pin Noninverting Analog Input. AIN+ operates fully differentially with respect AIN- with 2.5V differential swing common mode swing. AIN- (Pin Inverting Analog Input. AIN- operates fully differentially with respect AIN+ with 2.5V differential swing common mode swing. VREF (Pin 2.5V Internal Reference. Bypass solid analog ground plane with 10µF ceramic capacitor 10µF tantalum parallel with 0.1µF ceramic). overdriven external reference between 2.55V VDD. (Pins 11): Ground Exposed Pad. These ground pins exposed must tied directly solid ground plane under part. Keep mind that analog signal currents digital output signal currents flow through these pins. (Pin Positive Supply. This single power supplies entire chip. Bypass solid analog ground plane with 10µF ceramic capacitor 10µF tantalum parallel with 0.1µF ceramic). Keep mind that internal analog currents digital output signal currents flow through this pin. Care should taken place 0.1µF bypass capacitor close Pins possible. (Pin Three-State Serial Data Output. Each output data words represents difference between AIN+ AIN- analog inputs start previous conversion. (Pin External Clock Input. Advances conversion process sequences output data rising edge. Responds (3V) CMOS levels. more pulses wake from sleep. CONV (Pin 10): Convert Start. Holds analog input signal starts conversion rising edge. Responds (3V) CMOS levels. pulses with fixed high fixed state start mode. Four more pulses with fixed high fixed state start Sleep mode.
BLOCK DIAGRA
14-BIT
14-BIT LATCH
AIN+ AIN-
10µF
10µF
LTC1403A
THREESTATE SERIAL OUTPUT PORT
VREF 2.5V REFERENCE
TIMING LOGIC EXPOSED
CONV
1403A
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LTC1403/LTC1403A DIAGRA
CONV INTERNAL STATUS SAMPLE Hi-Z HOLD REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION SAMPLE Hi-Z
1403A TD01
*BITS MARKED AFTER SHOULD IGNORED.
CONV INTERNAL STATUS
SAMPLE
CONV
SLEEP VREF
1403A TD02
NOTE: SLEEP INTERNAL SIGNALS
LTC1403 Timing Diagram
tACQ HOLD 14-BIT DATA WORD tCONV tTHROUGHPUT
LTC1403A Timing Diagram
tACQ HOLD REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION SAMPLE Hi-Z
1403A TD01b
HOLD
Hi-Z
14-BIT DATA WORD tCONV tTHROUGHPUT
Mode Sleep Mode Waveforms
Delay
1403A TD03
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LTC1403/LTC1403A
APPLICATIO ATIO
DRIVING ANALOG INPUT
differential analog inputs LTC1403/LTC1403A easy drive. inputs driven differentially single-ended input (i.e., AIN- input grounded). Both differential analog inputs, AIN+ with AIN-, sampled same instant. unwanted signal that common both inputs each input pair will reduced common mode rejection sample-and-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion, analog inputs draw only small leakage current. source impedance driving circuit low, then LTC1403/ LTC1403A inputs driven directly. source impedance increases, will acquisition time. minimum acquisition time with high source impedance, buffer amplifier must used. main requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts (settling time must 39ns full throughput rate). Also keep mind while choosing input amplifier, amount noise harmonic distortion added amplifier. CHOOSING INPUT AMPLIFIER Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance (<100) closed-loop bandwidth frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz must less than 100. second requirement that closed-loop bandwidth must greater than 40MHz ensure adequate small-signal settling full throughput rate. slower amps used, more time settling provided increasing time between conversions. best choice drive LTC1403/LTC1403A will depend application. Generally, applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical. following list summary amps that suitable driving LTC1403/LTC1403A. (More
detailed information available Linear Technology Databooks LinearViewCD-ROM.) LTC®1566-1: Noise 2.3MHz Continuous Time LowPass Filter. LT1630: Dual 30MHz Rail-to-Rail Voltage Amplifier. 2.7V ±15V supplies. Very high AVOL, 500µV offset 520ns settling 0.5LSB swing. noise -93dB 40kHz below 1LSB 320kHz 2VP-P into 5V), making part excellent applications Nyquist) where rail-to-rail performance desired. Quad version available LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage Amplifier. 2.7V ±15V supplies. Very high AVOL, 1.5mV offset 400ns settling 0.5LSB swing. suitable applications with single supply. noise -93dB 40kHz below 1LSB 800kHz 2VP-P into 5V), making part excellent applications where rail-to-rail performance desired. Quad version available LT1633. LT1813: Dual 100MHz 750V/µs Voltage Feedback Amplifier. supplies. Distortion -86dB 100kHz -77dB 1MHz with supplies (2VP-P into 500). Excellent part fast applications with supplies. LT1801: 80MHz GBWP, -75dBc 500kHz, 2mA/Amplifier, 8.5nV/Hz. LT1806/LT1807: 325MHz GBWP, -80dBc Distortion 5MHz, Unity-Gain Stable, Out, 10mA/Amplifier, 3.5nV/Hz. LT1810: 180MHz GBWP, -90dBc Distortion 5MHz, Unity-Gain Stable, Out, 15mA/Amplifier, 16nV/Hz. LT1818/LT1819: 400MHz, 2500V/µs,9mA, Single/Dual Voltage Mode Operational Amplifier. LT6200: 165MHz GBWP, -85dBc Distortion 1MHz, UnityGain Stable, Out, 15mA/Amplifier, 0.95nV/Hz. LT6203: 100MHz GBWP, -80dBc Distortion 1MHz, Unity-Gain Stable, Out, 3mA/Amplifier, 1.9nV/Hz. LT6600-10: Amplifier/Filter Differential In/Out with 10MHz Cutoff.
LinearView trademark Linear Technology Corporation.
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LTC1403/LTC1403A
APPLICATIO ATIO
47pF AIN- LTC1403/ LTC1403A VREF
1403A
AIN+ 3VREF 10µF VREF LTC1403/ LTC1403A
1403A
10µF
Figure Input Filter
INPUT FILTERING SOURCE IMPEDANCE noise distortion input amplifier other circuitry must considered since they will LTC1403/LTC1403A noise distortion. smallsignal bandwidth sample-and-hold circuit 50MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example, Figure shows 47pF capacitor from AIN+ ground source resistor limit input bandwidth 47MHz. 47pF capacitor also acts charge reservoir input sample-and-hold isolates input from sampling-glitch sensitive circuitry. High quality capacitors resistors should used since these components distortion. silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors generate distortion from self heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems. When high amplitude unwanted signals close frequency desired signal frequency, multiple pole filter required. High external source resistance, combined with 13pF input capacitance, will reduce rated 50MHz bandwidth increase acquisition time beyond 39ns.
Figure
INPUT RANGE analog inputs LTC1403/LTC1403A driven fully differentially with single supply. Each input swing 3VP-P individually. conversion range, noninverting input each channel always 2.5V more positive than inverting input each channel. 2.5V range also ideally suited single-ended input with single supply applications. common mode range inputs extend from ground supply voltage VDD. difference between AIN+ AIN- inputs exceeds 2.5V, output code will stay fixed ones this difference goes below ouput code will stay fixed zeros. INTERNAL REFERENCE LTC1403/LTC1403A on-chip, temperature compensated, bandgap reference that factory trimmed near 2.5V obtain 2.5V input span. reference amplifier output VREF, (Pin must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance, 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic recommended. VREF overdriven with external reference shown Figure voltage external reference must higher than 2.5V class pull-up output internal reference. recommended range external reference 2.55V VDD. external reference 2.55V will quiescent load 0.75mA much during conversion.
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LTC1403/LTC1403A
APPLICATIO ATIO
CMRR Frequency
UNIPOLAR OUTPUT CODE
CMRR (dB) -100 -120
100k FREQUENCY (Hz)
100M
1403A
Figure
INPUT SPAN VERSUS REFERENCE VOLTAGE differential input range unipolar voltage span that equals difference between voltage reference buffer output VREF voltage ground (Exposed Ground). differential input range 2.5V when using internal reference. internal referenced these nodes. This relationship also holds true with external reference. DIFFERENTIAL INPUTS LTC1403/LTC1403A unique differential sampleand-hold circuit that allows inputs from ground VDD. will always convert unipolar difference AIN+ AIN-, independent common mode voltage
LTC1403/LTC1403A Transfer Characteristic
111.111 111.110 111.101 000.010 000.001 000.000 INPUT VOLTAGE
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1LSB
Figure
inputs. common mode rejection holds extremely high frequencies, Figure only requirement that both inputs below ground exceed VDD. Integral nonlinearity errors (INL) differential nonlinearity errors (DNL) largely independent common mode voltage. However, offset error will vary. change offset error typically less than 0.1% common mode voltage. Figure shows ideal input/output characteristics LTC1403/LTC1403A. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, 1.5LSB). output code natural binary with 1LSB 2.5V/16384 153µV LTC1403A, 1LSB 2.5V/4096 610µV LTC1403. LTC1403A 1LSB random white noise.
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LTC1403/LTC1403A
APPLICATIO ATIO
Figure Recommended Layout
Board Layout Bypassing Wire wrap boards recommended high resolution and/or high speed converters. obtain best performance from LTC1403/LTC1403A, printed circuit board with ground plane required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital track alongside analog signal track. optimum phase match between inputs desired, length input wires should kept matched. High quality tantalum ceramic bypass capacitors should used VREF pins shown Block Diagram first page this data sheet.
optimum performance, 10µF surface mount capacitor with 0.1µF ceramic recommended VREF pins. Alternatively, 10µF ceramic chip capacitors such Murata GRM235Y5V106Z016 used. capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. Figure shows recommended system ground connections. analog circuitry grounds should terminated LTC1403/LTC1403A (Pins exposed pad). ground return from LTC1403/LTC1403A (Pins exposed pad) power supply should impedance noise free operation. Digital circuitry grounds must connected digital supply common. applications where data outputs control signals connected continuously active microprocessor bus, possible errors conversion results. These errors feedthrough from microprocessor successive approximation comparator. problem eliminated forcing microprocessor into Wait state during conversion using three-state buffers isolate data bus. POWER-DOWN MODES Upon power-up, LTC1403/LTC1403A initialized active state ready conversion. Sleep mode waveforms show power-down modes LTC1403/LTC1403A. CONV inputs control power-down modes (see Timing Diagrams). rising edges CONV, without intervening rising edges SCK, LTC1403/LTC1403A. mode power drain drops from 14mW 6mW. internal reference remains powered mode. more rising edges wake LTC1403/LTC1403A service very quickly, CONV start accurate conversion within clock cycle. Four rising edges
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LTC1403/LTC1403A
APPLICATIO ATIO
CONV, without intervening rising edges SCK, LTC1403/LTC1403A Sleep mode power drain drops from 16mW 10µW. more rising edges wake LTC1403/LTC1403A operation. internal reference (VREF takes slew settle with 10µF load. Note that, using sleep mode more frequently than every 2ms, compromises settled accuracy internal reference. Note that, slower conversion rates, Sleep modes used substantial reductions power consumption. DIGITAL INTERFACE LTC1403/LTC1403A 3-wire (Serial Protocol Interface) interface. CONV inputs output implement this interface. CONV inputs accept swings from logic compatible, logic swing does exceed VDD. detailed description three serial port signals follows: Conversion Start Input (CONV) rising edge CONV starts conversion, subsequent rising edges CONV ignored LTC1403/ LTC1403A until following rising edges have occurred. necessary have minimum rising edges clock input between rising edges CONV. obtain maximum conversion speed, necessary allow more clock periods between conversions allow 39ns acquisition time internal sample-and-hold circuit. With clock periods conversion, maximum conversion rate limited 2.8Msps allow 39ns acquisition time. either case, output data stream comes within first clock periods ensure compatibility with processor serial ports. duty cycle CONV arbitrarily chosen used frame sync signal processor serial port. simple approach generate CONV create pulse that wide drive LTC1403/LTC1403A then buffer this signal with appropriate number inverters ensure correct delay driving frame
sync input processor serial port. good practice drive LTC1403/LTC1403A CONV input first avoid digital noise interference during sample-to-hold transition triggered CONV start conversion. also good practice keep width portion CONV signal greater than 15ns avoid introducing glitches front just before sampleand-hold goes into hold mode rising edge CONV. Minimizing Jitter CONV Input high speed applications where high amplitude sinewaves above 100kHz sampled, CONV signal must have little jitter possible (10ps less). square wave output common crystal clock module usually meets this requirement easily. challenge generate CONV signal from this crystal clock without jitter corruption from other digital circuits system. clock divider gates signal path from crystal clock CONV input should share same integrated circuit with other parts system. shown interface circuit examples, CONV inputs should driven first, with digital buffers used drive serial port interface. Also note that master clock already corrupted with jitter, even comes directly from crystal. Another problem with high speed processor clocks that they often cost, speed crystal (i.e., 10MHz) generate fast, jittery, phase-locked-loop system clock (i.e., 40MHz). jitter these PLL-generated high speed clocks several nanoseconds. Note that choose frame sync signal generated port, this signal will have same jitter DSP's master clock. Serial Clock Input (SCK) rising edge advances conversion process also udpates each data stream. After CONV rises, third rising edge starts clocking 12/14 data bits with sent first. simple approach generate drive LTC1403/
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LTC1403/LTC1403A
APPLICATIO ATIO
LTC1403A first then buffer this signal with appropriate number inverters drive serial clock input processor serial port. falling edge clock latch data from Serial Data Output (SDO) into your processor serial port. 14-bit Serial Data will received right justified, 16-bit word with more clocks frame sync. good practice drive LTC1403/LTC1403A input first avoid digital noise interference during internal comparison decision internal high speed comparator. Unlike CONV input, input sensitive jitter because input signal already sampled held constant. Serial Data Output (SDO) Upon power-up, output automatically reset high impedance state. output remains high impedance until conversion started. sends 12/14 bits output data stream beginning third rising edge after rising edge CONV. always high impedance mode when sending data bits. Please note delay specification from valid SDO. always guaranteed valid next rising edge SCK. 16-bit output data stream compatible with 16-bit 32-bit serial port most processors.
CONV LTC1403/ LTC1403A CONV
LOGIC SWING
Figure Serial Interface TMS320C54x
HARDWARE INTERFACE TMS320C54x LTC1403/LTC1403A serial output whose interface been designed high speed buffered serial ports fast digital signal processors (DSPs). Figure shows example this interface using TMS320C54X. buffered serial port TMS320C54x direct access segment memory. ADC's serial data collected alternating segments, real time, full 2.8Msps conversion rate LTC1403/ LTC1403A. assembly code sets frame sync mode BFSR accept external positive going pulse serial clock BCLKR accept external positive edge clock. Buffers near LTC1403/LTC1403A added drive long tracks prevent corruption signal LTC1403/LTC1403A. This configuration adequate traverse typical system board, source resistors buffer outputs termination resistors DSP, needed match characteristic impedance very long transmission lines. need terminate transmission line, buffer first with 74ACTxx gates. threshold inputs port respond properly swing from pin.
BFSR BCLKR TMS320C54x
1403A
3-WIRE SERIAL INTERFACELINK
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LTC1403/LTC1403A
APPLICATIO ATIO
01-08-01 Files: 014SI.ASM 1403A Sine wave collection with Serial Port interface bvectors.asm buffered mode avoid standard mode bug. s2k14ini.asm buffer size. first element 1024, last element 1023, middles 2047 0000 unipolar mode Works clock frames. negative edge BCLKR negative BFSR pulse data shifted cable from counter CONV cable from counter .width .length .title "sineb0 auto buffer mode" .mmregs .setsect ".text", 0x500,0 ;Set address .setsect "vectors", 0x180,0 ;Set address .setsect "buffer", 0x800,0 ;Set address .setsect "result", 0x1800,0 ;Set address .text ;.text marks
start: ;this label seems necessary ;Make sure /PWRDWN J1-9 turn AC01 tim=#0fh prd=#0fh #10h tspc pmst #01a0h #0700h #1800h #0800h call sineinit sinepeek: call sineinit wait goto wait
stop timer stop serial port AC01 iptr. Processor Mode STatus register init stack pointer. data page pointer computed receive buffer. pointer Buffered Serial Port receive buffer reset record counter Double clutch initialization insure proper reset. external frame sync must occur clocks more after port comes reset.
-Buffered Receive Interrupt Routine
breceive: #10h clear interrupt flags bitf(@BSPCE,#4000h) check which half (bspce(bit14)) buffer (NTC) goto bufull this still first half next half bspce #(2023h 08000h); turn halt second half (bspce(bit15)) return_enable -mask shift input data -bufull: *ar3+ #03FFFh *ar2+ data(#0bh) (@ar2 #02000h) (TC) goto start goto bufull load with buffer shift right mask TRISTATE bits with #03FFFh store buffer advance pointer output buffer starting 1800h restart buffer 1fffh
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executable incoming 1403 data buffer clearing result clearing start code
LTC1403/LTC1403A
bsend -dummy bsend return-return_enable ;this also dummy return define bsend vector table file BVECTORS.ASM -.copy "c:\dskplus\1403\s2k14ini.asm" ;initialize buffered serial port .space 16*32 ;clear chunk mark VECTORS .sect "vectors" ;The vectors start here .copy "c:\dskplus\1403\bvectors.asm" ;get vectors .sect "buffer" .space 16*0x800 .sect "result" .space 16*0x800 .end ;Set address buffer clearing ;Set address result clearing
COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 File: s2k14ini.ASM initialization code 'C54x DSKplus with 1403A standard mode BSPC same 'C542 BSPCE SPCE seem same 'C542 .title "Buffered Serial Port Initialization Routine" .set .set .set .set !YES BIT_8 .set BIT_10 .set BIT_12 .set BIT_16 .set .set 0x80 This example initialize Buffered Serial Port (BSP). initialized require external operation. data format 16-bits, burst mode, with autobuffering enabled. *LTC1403 timing from LCC28 socket board with 10MHz crystal. *10MHz, divided from 40MHz, forced CLKIN 1403 board. *Horizontal scale 25ns/chr 100ns period BCLKR *Timing measured pins. labels jumper cable. *BFSR J1-20 ~\_/~\_/~* *BCLKR J1-14 *BDR J1-26 *CLKIN J5-09 ~\_/~\_/~\_/~\_/~\_/~* *C542 read B12*
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LTC1403/LTC1403A
negative edge BCLKR negative BFSR pulse data shifted cable from counter CONV cable from counter right shift needed right justify input data main program *the msbs should also masked Loopback .set ;(digital looback mode?) Format .set BIT_16 ;(Data format? 16,12,10,8) IntSync .set ;(internal Frame syncs generated?) IntCLK .set ;(internal clks generated?) BurstMode .set ;(if BurstMode=NO, then Continuous) CLKDIV .set ;(3=default value, CLOCKOUT) PCM_Mode .set ;(Turn mode?) FS_polarity .set ;(change polarity)YES=^^^\_/^^^, NO=_/^\_ CLK_polarity .set ;(change polarity)for BCLKR YES=_/^, NO=~\_ Frame_ignore .set !YES ;(inverted !YES -ignores frame) XMTautobuf .set ;(transmit autobuffering) RCVautobuf .set ;(receive autobuffering) XMThalt .set ;(transmit buff halt buff full) RCVhalt .set ;(receive buff halt buff full) XMTbufAddr .set 0x800 ;(address transmit buffer) XMTbufSize .set 0x000 ;(length transmit buffer) RCVbufAddr .set 0x800 ;(address receive buffer) RCVbufSize .set 0x800 ;(length receive buffer)works notes 'C54x Peripherals Reference Guide setting valid buffer start length values. Page 9-44 .eval ((Loopback 1)|((Format 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,SPCval .eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format SPCEval .eval SPCEval sineinit: bspc #SPCval #10h #210h intm bspce #SPCEval #XMTbufAddr #XMTbufSize #RCVbufAddr #RCVbufSize bspc #(SPCval return
places buffered serial port reset clear interrupt flags Enable HPINT,enable BRINT0 unmasked interrupts enabled. programs BSPCE initializes transmit buffer start address initializes transmit buffer size initializes receive buffer start address initializes receive buffer size bring buffered serial port reset ;for transmit receive because GO=0xC0
File: BVECTORS.ASM Vector Table 'C54x DSKplus 10.Jul.96 vectors Debugger vectors vectors just return vectors this table configured processing external internal software interrupts. DSKplus debugger uses four interrupt vectors. These RESET, TRAP2, INT2, HPIINT. MODIFY THESE FOUR VECTORS PLAN DEBUGGER
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LTC1403/LTC1403A
APPLICATIO ATIO
other vector locations free use. When programming always sure HPIINT unmasked (IMR=200h) allow communications kernel host interact. INT2 should normally masked (IMR(bit that will interrupt itself during HINT. HINT tied INT2 externally.
.title "Vector Table" .mmregs reset goto #80h return_enable goto #88h .space 52*16 return_enable return_enable return_enable return_enable goto breceive goto bsend return_enable return_enable return_enable dgoto #0e4h .space 24*16 ;00; RESET MODIFY USING DEBUGGER
;04; non-maskable external interrupt
trap2
;08; trap2
MODIFY USING DEBUGGER
int0
;0C-3F: vectors software interrupts 18-30 ;40; external interrupt int0
int1
;44; external interrupt int1
int2
;48; external interrupt int2
tint
;4C; internal timer interrupt
brint
;50; receive interrupt
bxint
;54; transmit interrupt
trint
;58; receive interrupt
txint
;5C; transmit interrupt
int3
;60; external interrupt int3
hpiint
;64; HPIint
MODIFY USING DEBUGGER
;68-7F; reserved area
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LTC1403/LTC1403A
PACKAGE DESCRIPTIO
2.794 0.102 (.110 .004)
5.23 (.206)
0.50 0.305 0.038 (.0197) (.0120 .0015) RECOMMENDED SOLDER LAYOUT
0.254 (.010) GAUGE PLANE
0.18 (.007)
NOTE: DIMENSIONS MILLIMETER/(INCH) DRAWING SCALE DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH, PROTRUSIONS GATE BURRS SHALL EXCEED 0.152mm (.006") SIDE DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSIONS. INTERLEAD FLASH PROTRUSIONS SHALL EXCEED 0.152mm (.006") SIDE LEAD COPLANARITY (BOTTOM LEADS AFTER FORMING) SHALL 0.102mm (.004")
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
Package 10-Lead Plastic MSOP
(Reference 05-08-1663)
BOTTOM VIEW EXPOSED OPTION
0.889 0.127 (.035 .005)
2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004)
2.083 0.102 3.20 3.45 (.082 .004) (.126 .136)
3.00 0.102 (.118 .004) (NOTE
0.497 0.076 (.0196 .003)
4.90 0.152 (.193 .006) DETAIL 0.53 0.152 (.021 .006) DETAIL SEATING PLANE 1.10 (.043)
3.00 0.102 (.118 .004) (NOTE
0.86 (.034)
0.17 0.27 (.007 .011)
0.50 (.0197)
0.127 0.076 (.005 .003)
MSOP (MSE) 0603
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LTC1403/LTC1403A RELATED PARTS
PART NUMBER ADCs LTC1608 LTC1604 LTC1609 LTC1411 LCT1414 LTC1407/LTC1407A LTC1420 LTC1405 LTC1412 LTC1402 LTC1864/LTC1865 DACs LTC1666/LTC1667/LTC1668 LTC1592 References LT1790-2.5 LT1461-2.5 LT1460-2.5 Micropower Series Reference SOT-23 Precision Voltage Reference Micropower Series Voltage Reference 0.05% Initial Accuracy, 10ppm Drift 0.04% Initial Accuracy, 3ppm Drift 0.1% Initial Accuracy, 10ppm Drift 12-/14-/16-Bit, 50Msps DACs 16-Bit, Serial SoftSpanIOUT 87dB SFDR, 20ns Settling Time ±1LSB INL/DNL, Software Selectable Spans 16-Bit, 500ksps Parallel 16-Bit, 333ksps Parallel 16-Bit, 250ksps Serial 14-Bit, 2.5Msps Parallel 14-Bit, 2.2Msps Parallel 12-Bit, 10Msps Parallel 12-Bit, 5Msps Parallel 12-Bit, 3Msps Parallel 12-Bit, 2.2Msps Serial 16-Bit, 250ksps Serial Supply, ±2.5V Span, 90dB SINAD Supply, ±2.5V Span, 90dB SINAD Configurable Bipolar/Unipolar Inputs Selectable Spans, 80dB SINAD Supply, ±2.5V Span, 78dB SINAD Selectable Spans, 72dB SINAD Selectable Spans, 115mW Supply, ±2.5V Span, 72dB SINAD Supply, 4.096V ±2.5V Span Supply, Channel, 4.3mW, MSOP Package DESCRIPTION COMMENTS
12-/14-Bit, 3Msps Simultaneous Sampling 2-Channel Differential, 14mW, MSOP Package
SoftSpan trademark Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT/TP 1203 PRINTED
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
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