SERCOS INTERFACE CONTROLLER Single-chip controller SERCOS interfa

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SERCOS INTERFACE CONTROLLER Single-chip controller SERCOS interfa

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SERCON816
SERCOS INTERFACE CONTROLLER
Single-chip controller SERCOS interface Real time communication industrial control systems 8/16-bit interface, Intel Motorola control signals Dual port with 2048 word *16-bit Data communications optical fiber rings, rings busses Maximum transmission rate Mbaud with internal clock recovery Internal repeater ring connections Full duplex operation Modulation power optical transmitter diode Automatic transmission synchronous data telegrams communication cycle Flexible configuration, communication data stored (single double buffer) transfer Synchronization external signal
PQFP100 ORDERING NUMBERS: SERC816 SERC816/TR
Timing control signals Automatic service channel transmission Watchdog monitor software external synchronization signals Compatible mode SERCON410B SERCOS interface controller 100-pin plastic flat-pack casing
Figure SERCON816 Block Diagram
D[15:0] A[15:0] ALEL ALEH N0/1 BHEN
ADMUX MODE[1:0] WIDT
interfac
interrupt reset
O2/4 MCLK DMAR EQR/T DMAACKNR/T
watc hdog telegramproc essing timingc ontrol
WDOGN
C_CLK CON_CLK DIV_CLK
BAUD BAUD16 M0/1
serial
interfac
ECACT IDLE
xD[6:1] optical transm itter/ receiver -485 drive
January 2003
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SERCON816
TABLE CONTENTS GENERAL DESCRIPTION.3 Description Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions ELECTRICAL CHARACTERISTCS Power Dissipation 3.4.1 Power Dissipation Considerations.9 Electrical Characteristics.10 3.5.1 Clock Input MCLK.10 3.5.2 Clock Input SCLK 3.5.3 Address Latch.11 3.5.4 Read Access Control Registers.12 3.5.5 Read Access Dual Port 3.5.6 Write Access Control Registers.14 3.5.7 Write Access DUAL Port Control Registers Data Structures.16 Control Register Addresses Data Structures within 4.2.1 Telegram Headers.16 4.2.2 Data Containers.17 4.2.3 Marker 4.2.4 Service Containers Additional Specifications, Tools Support Additional Specifications Hardware Software Components Tools Package Mechanical Data: SERCON816 Plastic Quad Flat Pack Package (PQFP100)
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SERCON816
GENERAL DESCRIPTION SERCOS interface controller SERCON816 integrated circuit SERCOS interface communication systems. SERCOS interface digital interface communication between systems which have exchange information cyclically short, fixed intervals (62,5 ms). appropriate synchronous operation distributed control test equipment (e.g. connection between drives numeric control). SERCOS interface communication system consists master several slaves. These units connected fiber optical ring. This ring starts ends master. slaves regenerate repeat their received data send their telegrams. this method telegrams sent master received slaves while master receives data telegrams from slaves. optical fiber assures reliable high-speed data transmission with excellent noise immunity. SERCOS interface controller contains hardware-related functions SERCOS interface considerably reduces hardware costs computing time requirements microprocessor. direct link between electro-optical receiver transmitter microprocessor that executes control algorithms. SERCON816 used both SERCOS interface masters slaves. circuit contains following functions (Fig. Interface microprocessor with data width bits with control lines according Intel Motorola standards. serial interface making direct connection with optical receiver transmitter fiber optic ring with drivers electric ring bus. Data clock regeneration, repeater ring topologies serial transmitter receiver integrated. signals monitored test signals generated. serial interface operates Mbaud without external circuitry. dual port (2048 bit) control communication data. organization memory flexible. Telegram processing automatic transmission monitoring synchronous data telegrams. Only transmission data which intended particular interface user processed. transmitted data either stored internal (single double buffer) transferred direct memory access (DMA). transmission service channel information over several communication cycles executed automatically. addition SERCOS interface SERCON816 also used other real-time communications tasks. alternative fiber optical ring also topologies with RS-485 signals supported (Fig. SERCON816 therefore suitable wide range applications. Remark: SERCON816 based former SERCON410B SERCOS interface controller. Figure SERCON816 Configuration
BHEN ALEL ALEH
ADMUX BUSMODE0 BUSMODE1 BUSWIDTH BYTDIR
SERCON816
PCS1 PCSN0 MCSN1 MCSN0 BUSYN INT0 INT1 DMAACKTN DMAACKRN DMAREQT DMAREQR DIV_CLK CON_CLK CYC_CLK L_ERRN
SCLK MCLK SCLK04 SCLK02 TEST NDTRO RSTN OUTZ TxD1 TxD2 TxD3 TxD4 TxD5 TxD6 WDOGN IDLE RECACTN SBAUD16 SBAUD
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SERCON816
Figure SERCON816 with Ring Connection (SERCOS interface)
interfac
ERCON816
aster
fibre
optical
ring
ERCON816
CON816
RCON816
interfac
interfac
interfac
slave
slave
slave
Figure SERCON816 with RS-485 connection
interfac
CON816
ster
IDLE
IDLE
CON816
IDLE
CON816
IDLE
CON816
interfa
interfa
interfac
ING.CDR
slave
slave
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SERCON816
DESCRIPTION
Table SERCON816 Port Function Summary
Signal(s) D15-0 Pin(s) 77-80, 82-85, 87-90, 92-95 Function Data bus: 8-bit-wide interfaces, data written read D7-0, 16-bit-wide interfaces D15-0. When ADMUX address which stored address latch with ALEL ALEH input D15-0. Address latch enable, high, active high: they only used when ADMUX When ALEL/ALEH signals from data address bus, when ALEL/ALEH they store address. When ADMUX ALEL/ALEH have connected VDD. Read: Intel interface, data read when Motorola interface, data read written when (BUSMODE1 (BUSMODE1 Write: Intel interface, data written when Motorola interace, selects read (WRN write (WRN operations data bus. Byte high enable, active low: 16-bit mode, data transferred D15-8 when BHEN Memory chip select, active low: access internal MCSN0 MCSN1 must Periphery chip select, active (PCSN0) active high (PCS1): access control registers PCSN0 must equal PCS1 must equal busy, active low: becomes active access address dual port performed simultaneously access same memory location internal telegram processing. request receive, active high: becomes active data from receive FIFO read. beginning read operation last word receive FIFO, DMAREQR becomes inactive. acknowledge receive, active low: when DMAACKRN receive FIFO read, independent levels A6-1 chip select signals. request transmit, active high: becomes active when data written transmit FIFO. DMAREQT becomes inactive again beginning last write access transmit FIFO. acknowledge transmit, active low: when DMAACKTN transmit FIFO written when there write access independent levels A6-1 chip select signals. Address data bus: when ADMUX A15-0 address inputs, when ADMUX A15-0 outputs address latch. mode: BUSMODE0 turns Intel interface (RDN read, write), BUSMODE0 selects Motorola interface (RDN data strobe, read/write). BUSMODE1 selects 0-active data strobe (BUSMODE1 1-active data strobe (BUSMODE1 width: selects 8-bit- 16-bit-wide interface (1). Byte address sequence: when BYTEDIR addresses lower bits word (low byte first), when BYTEDIR upper bits word addressed (high byte first). Interrupts, active active high. Interrupt sources signal polarity programmable. Baud rate SERCON410B compatible mode: SBAUD SBAUD16 selects baud rate serial interface. SBAUD16 SERCON410B compatible mode selected. Baud rate. overwritten microprocessor.
ALEL, ALEH
BHEN MCSN0, MCSN1 PCSN0, PCS1 BUSYN
46,47 48,49
DMAREQR
DMAACKRN DMAREQT
DMAACKTN
ADMUX BUSMODE0, BUSMODE1
97,98
BUSWIDTH BYTEDIR
INT0, INT1 SBAUD16
44,43
SBAUD
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SERCON816
Table SERCON816 Port Function Summary (continued)
Signal(s) RECACTN TxD1 TxD6-2 Pin(s) 22,21,20, 18,17 Function Receive data serial interface. Receive clock serial interface. Output internally generated receive clock. Receive active, active low. Indicates that serial receiver receiving telegram. Transmit data. switched high impedance state. Transmit data output port. pins either output serial data used parallel output ports. When they output transmit data, each switched high impedance state individually. Transmit clock serial interface. Output internally generated transmit clock. Transmitter active, active low. When transmitting data IDLE request transmit, active high: becomes active when data written transmit FIFO. DMAREQT becomes inactive again beginning last write access transmit FIFO. acknowledge transmit, active low: when DMAACKTN transmit FIFO written when there write access independent levels A6-1 chip select signals. Address data bus: when ADMUX A15-0 address inputs, when ADMUX A15-0 outputs address latch. mode: BUSMODE0 turns Intel interface (RDN read, write), BUSMODE0 selects Motorola interface (RDN data strobe, read/write). BUSMODE1 selects 0-active data strobe (BUSMODE1 1-active data strobe (BUSMODE1 width: selects 8-bit- 16-bit-wide interface (1). Byte address sequence: when BYTEDIR addresses lower bits word (low byte first), when BYTEDIR upper bits word addressed (high byte first). Interrupts, active active high. Interrupt sources signal polarity programmable. Baud rate SERCON410B compatible mode: SBAUD SBAUD16 selects baud rate serial interface. SBAUD16 SERCON410B compatible mode selected. Baud rate. overwritten microprocessor. Receive data serial interface. Receive clock serial interface. Output internally generated receive clock. Receive active, active low. Indicates that serial receiver receiving telegram. Transmit data. switched high impedance state. Transmit data output port. pins either output serial data used parallel output ports. When they output transmit data, each switched high impedance state individually. Transmit clock serial interface. Output internally generated transmit clock. Transmitter active, active low. When transmitting data IDLE Turn test generator: switches TxD1-6 contiuous signal light, switch-over zero stream. processor overwrite level TM1-0. Select repeater mode reset time: TM1=0 TM2=0 repeater off, other repeater
IDLE DMAREQT
DMAACKTN
ADMUX BUSMODE0, BUSMODE1
97,98
BUSWIDTH BYTEDIR
INT0, INT1 SBAUD16
44,43
SBAUD RECACTN TxD1 TxD6-2
22,21,20, 18,17 30,31
IDLE TM0,
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SERCON816
Table SERCON816 Port Function Summary (continued)
Signal(s) WDOGN L_ERRN Pin(s) Watchdog output (active low) Line error, active low: goes when signal distortion high when receive signal missing. operating mode programmed processor. SERCOS interface cycle clock: CYC_CLK synchronizes communication cycles. polarity programmable. Control clock: becomes active within communication cycle. Time, polarity width programmable. Divided control clock: becomes active several times within communication cycle once several communication cycles. Number pulses, start time, repetition rate polarity programmable, pulse width Serial clock clock regeneration: maximum frequency MHz. Clock output: outputs SCLK clock divided Clock output: outputs SCLK clock divided Master clock telegram processing timing control, frequency MHz. Reset, active low. Must zero least after power Test, active high. tied VSS. Puts outputs into high impedance state, active high: OUTZ puts pins into high impedance state. clocks turned circuit reset. in-circuit test turning power-down mode. NAND tree output. test semiconductor manufacturers connection test after board production. NDTRO high impedance state. Ground pins: Function
CYC_CLK CON_CLK DIV_CLK
SCLK SCLKO2 SCLKO4 MCLK RSTN TEST OUTZ
NDTRO
3,15,23,33 ,42,50,60, 70,81,91 1,8,19,27, 37,55,65, 76,86
Power supply
ELECTRICAL CHARACTERISTICS
Absolute Maximum RatingSymbol TSTG Supply voltage Input voltage Output voltage Storage temperature Parameter Value -0.5 -0.5 -0.5 +150 Unit
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SERCON816
Recommended Operating ConditionSymbol fSCLK fMCLK Operating temperature Chip junction temperature Operating supply voltage Clock frequency SCLK Clock frequency MCLK Parameter Min. 4.75 Max. 5.25 Unit
Notes: Only used (SBAUD16=0) normal operation, during testing fMCLK possible
ELECTRICAL CHARACTERISTCS (VDD Tamb unless otherwise specified)
Symbol Vhyst Parameter level input voltage (TTL) inputs High level input voltage (TTL) inputs Schmitt trigger hysteresis L_ERRN, TXD6-1, MCLK, SCLK, RSTN, ADMUX, BUSMODE1-0, BUSWIDTH, BYTEDIR, TM1-0, SBAUD16, SBAUD, TEST, OUTZ, RXD, CYC_CLK level input current with pullup D15-0, A15-0, TXD6-1, ADMUX, BUSMODE1-0, BYTEDIR, TM10, SBAUD16, SBAUD, TEST, OUTZ, RXD, CYC_CLK, BHEN, MCSN1-0, PCSN0, PCS1, DMAACKTN, DMAACKRN High level input current with pulldown MCLK, SCLK, RSTN, ALEH, ALEL Equivalent pull-up resistance Equivalent pull-down resistance level output voltage, Oand I/O-pins except TXD6-1, L_ERRN High level output voltage, Oand I/O-pins except TXD6-1, L_ERRN Test Condition Min. Typ. Max. Unit
-100
-240
112.5 112.5
KOhm KOhm
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SERCON816
ELECTRICAL CHARACTERISTCS (continued) (VDD Tamb unless otherwise specified)
Symbol IKLU VESD CPIN Parameter level output voltage, pins TXD6-1, L_ERRN High level output voltage, pins TXD6-1, L_ERRN Tri-state output leakage latch-up current Electrostatic protection capacitance Test Condition V<VSS V>VDD Leakage human body model 2000 Min. Typ. Max. Unit
Power Dissipation (VDD Tamb unless otherwise specified)
Symbol Parameter Power dissipation Maximum allowed power dissipation Test Condition Mbaud, MCLK=64 TA=+85°, flow Min. Typ. 8501 1000 Max. Unit
Notes: estimated
3.4.1 Power Dissipation Considerations Most current consumed CMOS devices alternate current (AC) which charging discharging capacitances pins internal nodes. current consumption rises with frequency which pins internal nodes will toggle with capacitances connected pins device: (C=capacitance, V=voltage, f=frequency) applications which require power consumption exceeds maximum allowed power consumption following required: Connect unused pins pull-up pull-down resistors Minimize capacitive load pins Reduce clock frequency SCLK MCLK Minimize accesses internal control registers maximum allowed power consumption limited maximum allowed chip junction temperature number VCC/VDD pins. chip junction temperature influenced ambient temperature package thermal resistance. ambient temperature could influenced application through good temperature management like heat sinks ambient cooling.
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SERCON816
Typical current consumption: measured (VCC/VDD) 25°C
Mode 410B
fSCLK (MHz)
fMCLK (MHz)
Current (mA)
Electrical Characteristics (Cload Tamb 3.5.1 Clock Input MCLK Figure Timing clock MCLK related output
fMCLK MCLK DMAREQR/T CON_CLK, DIV_CLK tMCLD
tMCLK0
tMCLK1
Symbol fMCLK tMCLK0 tMCLK1 tMCLD fMCLK fMCLK Clock frequency MCLK MCLK MCLK high
Parameter
Min.
Typ.
Max.
Unit
Output delay rising edge MCLK DMAREQR/T, CON_CLK, DIV_CLK Baudrate Mbit/s Baudrate Mbit/s
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SERCON816
3.5.2 Clock Input SCLK Figure Timing Clock SCLK
fSCLK SCLK
tSCLK0
tSCLK1
Symbol fSCLK Clock frequency SCLK used (SBAUD16=0)
Parameter
Min.
Typ.
Max.
Unit
unused (SBAUD16=1) tSCLK0 tSCLK1 SCLK SCLK high
3.5.3 Address Latch Figure Address Latch
tALEW ALEH, ALEL tALESU D15-0 A15-0 tALEHD
Symbol TALEW TALESU TALEHD Pulse width ALEL, ALEH
Parameter
Min.
Typ.
Max.
Unit
Setup time D15-0 falling edge ALEH, ALEL hold time falling edge ALEH, ALEL D15-0 Delay from D15-0 A15-0
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SERCON816
3.5.4 Read Access Control Registers Figure Read Access Control Register
A6-0, BHEN PCSN0, PCS1, DMAACKNR, (Motorola mode)
tPAD tASU tPRDD tAHD tRDZ
D15-0 tPRQ DMAREQR
Symbol tASU
Parameter Setup time A6-0, (Note Setup time BHEN, PCSN0, PCS1, DMAACKNR, (only Motorola mode), (Note
Min.
Typ.
Max.
Unit
tAHD
Hold time A6-0, BHEN, PCSN0, PCS1, DMAACKNR, (only Motorola mode) rising edge (Intel Motorola mode with active strobe) falling edge (Motorola mode with high active strobe) Access time A6-0, BHEN, PCSN0, PCS1, DMAACKNR, (only Motorola mode) D15-0 valid Access time D15-0 valid Delay D15-0 high-Z Delay DMAREQR
tPAD tPRDD tRDZ tPRQ
Note: Setup time input signals falling edge (Intel Motorola mode with active strobe) rising edge (Motorola mode with high active strobe)
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SERCON816
3.5.5 Read Access Dual Port Figure Read Access Dual Port
A10-0, BHEN, MCSN0-1, (Motorola mode)
tASU
tAHD tRD1 tMRDD tRDZ tMBHD
D15-0 tMBSY
Symbol tASU
Parameter Setup time A11-0, (Note Setup time MCSN0-1, both signals activated simultaneously. (Note Setup time MCSN0-1, these both signals activated earlier. (Note Setup time BHEN, (only Motorola mode), (Note
Min.
Typ.
Max.
Unit
tAHD
hold time A11-0, BHEN, MCSN0-1, (only Motorola mode) rising edge (Intel Motorola mode with active strobe) falling edge (Motorola mode with high active strobe) Cycle time read clock SBAUD16 (fRDNCLK fSCLK) SBAUD16 (fRDNCLK fSCLK)
tRDNCLK
fSCLK fSCLK tRDNCLK tRDNCLK
tMRDD tMBSY tMBHD tRDZ tRD1
access time D15-0 valid delay BUSYN Delay BUSYN high D15-0 valid Delay D15-0 high-Z high after read acces
Notes: Setup time input signals falling edge (Intel Motorola mode with active strobe) rising edge (Motorola mode with high active strobe)
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SERCON816
3.5.6 Write Access Control Registers Figure Write Access Control Register
A6-0, BHEN, PCS1, DMAACKNT (Motorola mode) (Intel mode) (Motorola mode) D15-0
tASU tPWRW tDSU tPRQ
tAHD
tDHD
DMAREQT
Symbol tASU
Parameter Setup time A6-0, (Note Setup time BHEN, PCSN0, PCS1, DMAACKNR, (only Motorola mode), (Note
Min.
Typ.
Max.
Unit
tAHD
hold time A6-0, BHEN, PCSN0, PCS1, DMAACKNT, (only Motorola mode) rising edge (Intel mode) (Motorola mode, strobe active low) falling edge (Motorola mode, strobe active high) pulse width (Intel mode) (Motorola mode) setup time D15-0 write access hold time D15-0 write access delay DMAREQT
tPWRW tDSU tDHD tPRQ
Notes: Setup time input signals falling edge (Intel mode) (Motorola mode with active strobe) rising edge (Motorola mode with high active strobe)
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SERCON816
3.5.7 Write Access DUAL Port Figure Write Access DUAL Port
A10-0, BHEN, MCSN0-1, (Motorola mode) (Intel mode) (Motorola mode) D15-0
tASU tMWRW tDSU tMBSY tMBHWH
tAHD tWR1 tDHD
Symbol tASU
Parameter Setup time A11-0, (Note Setup time MCSN0-1, both signals activated simultaneously. (Note Setup time MCSN0-1, these both signals activated earlier. (Note Setup time BHEN, (only Motorola mode), (Note
Min.
Typ.
Max.
Unit
tAHD
hold time A11-0, BHEN, MCSN0-1, (only Motorola mode) rising edge (Intel mode) (Motorola mode with active strobe) falling edge (Motorola mode with high active strobe) Pulse width Setup time D15-0 write access Hold time D15-0 after write access Delay (begin write access) BUSYN Setup time BUSYN high write access high after write acces
tMWRW tDSU tDHD tMBSY tMBHWH tWR1
Notes: Setup time input signals falling edge (Intel mode) (Motorola mode with active strobe) rising edge (Motorola mode with high active strobe)
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SERCON816
CONTROL REGISTERS DATA STRUCTURES
Control Register Addresses following table overview control registers. address word address which input A6-1. calculate byte address, value multiplied two. control registers written read (R/W), with exception control bits that initiate action (W). status registers only read (R). When control registers which contain bits that used only read, written these bits they evaluated internally. control registers read with bits that used, these bits
A6-1
Bits 0-15 0-15
Name VERSION
Value 0010H Circuit code (0010H)
Function
Please refer SERCON816 Reference Guide detailed description control registers.
Data Structures within this first eleven words have fixed meaning.
A10-1 Contents COMPT0-1: Start transmission blocks SCPT0-7: Address service containers NMSTERR: Error counter
rest divided into data structures required. 4.2.1 Telegram Headers telegram header receive telegram contains following five control words:
Index Name DBUF Telegram address Data storage internal (DMA transfer (DMA Data RAM: single buffer (DBUF double buffer (DBUF single buffering (DMA DBUF transfer (DMA telegram data invalid (VAL valid (VAL double buffering (DMA DBUF data buffer (VAL buffer (VAL valid. Modified controller beginning receive telegrams. Telegrams received address valid (ACHK independent received address (ACHK received address stored ADR. time receiving checked (TCHK checked (TCHK last telegram free error (RERR errored received (RERR Marker telegram header receive telegram. Marker telegram header. Time start telegram after MST. Length telegram data words (not including address). Word address within next telegram header marker. (Not used) NERR Error counter Function
0-15 0-15 0-10 9-15 0-15
ACHK TCHK RERR TLEN
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SERCON816
4.2.2 Data Containers data container comprises 16-bit control words well variable number data words. data stored internal (DMA single buffer used (DBUF data container buffer. Using storage double buffering (DBUF data buffers needed. case transfer (DMA data container only comprises control words (Fig. 12). structure control words depends whether telegram transmitted received:
Index 11-13 0-15 Name SVFL SCMASTER LASTDC Function Number 16-bit data words data block. Flag, whether data block uses service container (SVFL Number service container, which used Processing service container slave mode (SCMASTER master mode (SCMASTER Last data container telegram further data containers follow (0). Position data block within telegram number words. first data record telegram (only case receive telegrams).
Figure Structure Data Container
DBUF
DBUF
ontrol word
control word
ontrol word
buffer
buffer
buffer
transm telegram
DBUF
DBUF
ontrol word ontrol word
control word control word
ontrol word ontrol word
buffer
buffer eive telegrams buffer
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SERCON816
4.2.3 Marker marker comprises 16-bit words:
Index 0-13 0-15 TEND Name (Not used) Marker marker. Marker marker. Time after which last telegram ended µs). Function
4.2.4 Service Containers service container contains control words buffer (BUFLEN words, max. length 255) Figure Structure Service Container
control word control word control word control word control word write read buffer
BUFLEN
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SERCON816
master mode (SCMASTER control words coded follows:
Index
10-11
Name HS_MDT L/S_MDT END_MDT ELEM_MDT SETEND M_BUSY NINFO_WRITE Handshake-bit Read/write Data element type END_MDT
Function
Service container waits interaction microprocessor (M_BUSY Number info words write buffer (Not used)
INT_ERR INT_END_WRBUF INT_END_RDBUF
Slave reports error write buffer reached read buffer reached (Not used)
10-15
HS_AT BUSY_AT ERR_AT CMD_AT
Handshake Busy Error Command modification (Not used)
RECERR NINFO_READ
Last transmission correct erroneous Number info words read buffer (Not used)
8-15
WRDATPT WRDATLAST RDDATPT RDDATLAST ERR_CNT BUSY_CNT INT_SC_ERR INT_HS_TIMEOUT INT_BUSY_TIMEOUT INT_CMD
Pointer present position write buffer Pointer last position write buffer Pointer present position read buffer Pointer last position read buffer Error counter Error counts differences handshake BUSY cycles Interrupt protocol error Interrupt handshake timeout Interrupt BUSY timeout Slave command modification (Not used)
8-15
13-15
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SERCON816
coding five control words depends mode service channel. Using slave mode (SCMASTER they have following structure:
Index
10-11
Name HS_AT BUSY_AT ERR_AT CMD_AT ELEM NINFO_WRITE Handshake
Function
Busy also waiting microprocessor interaction Error Command modification Data element present transmission Read (0)/write present transmission Number info words write buffer (Not used)
INT_ELEM_CHANGE INT_END_WRBUF INT_END_RDBUF INT_END_MDT HS_MDT L/S_MDT END_MDT ELEM_MDT
Master modified data element read/write write buffer reached read buffer reached Master reports END_MDT-bit Handshake Read/write Data element (Not used)
10-15
RECERR NINFO_READ
Last transmission correct erroneous Number info words read buffer (Not used)
8-15
WRDATPT WRDATLAST RDDATPT RDDATLAST
Pointer present position write buffer Pointer last position write buffer Pointer present position read buffer Pointer last position read buffer (Not used)
8-15
10-15 INT_SC_ERR
Interrupt protocol error (Not used)
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SERCON816
ADDITIONAL SPECIFICATIONS, TOOLS SUPPORT
Additional Specifications Reference Manual SERCON816 reference manual (160 pages) SERCON816 Asic contains complete very detailed specification SERCON816 Asic, including description pinning controller, microprocessor interface, serial interface, telegram processing, master slave modes, additional modes, control data structures, programming examples, electrical mechanical characteristics chip, differences between SERCON816 SERCON410B controller. SERCOS interface specification SERCOS interface specification (IEC/EN 61491) contains detailed description transfer medium physical layer, data transfer data link layer, protocol structure data contents, communication phases, functional handling error handling, list description identifier numbers. functions described separate document.
Hardware Software Components Master slave routines (driver software) SERCON816 controller available from several suppliers world-wide. Furthermore different boards wide range computer interfaces offered, including ISA-, VME-, PCI- PC/104 systems. Tools Different development testing tools available SERCOS interface. These tools include monitors, configuration simulation tools, well tools conformance testing.
specification additional application notes please contact: Interests Group SERCOS interface
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SERCON816
PACKAGE MECHANICAL DATA: SERCON816 PLASTIC QUAD FLAT PACK PACKAGE (PQFP100)
DIM. MIN. 0.65 16.95 13.90 0.25 2.55 0.22 0.13 22.95 19.90 23.20 20.00 18.85 0.65 17.20 14.00 12.35 0.80 1.60 0°(min.), 7°(max.) 0.95 0.026 17.45 14.10 0.667 0.547 2.80 3.05 0.38 0.23 23.45 20.10 TYP. MAX. 3.40 0.010 0.100 0.0087 0.005 0.903 0.783 0.913 0.787 0.742 0.026 0.677 0.551 0.486 0.031 0.063 0.037 0.687 0.555 0.110 0.120 0.015 0.009 0.923 0.791 MIN. inch TYP. MAX. 0.134
OUTLINE MECHANICAL DATA
PQFP100
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SERCON816
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. STMicroelectronics acknowledges trademarks companies referred this document. logo registered trademark STMicroelectronics 2003 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan -Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States. http://www.st.com
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SERCOS INTERFACE CONTROLLER Single-chip controller SERCOS interfa

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