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Acoustic Echo Canceller 2170 Version
Preliminary Data Sheet 10.99
Revision History: Current Version:Preliminary Data Sheet 10.99 Previous Version: Page previous Version) Page Version) Subjects (major changes since last revision) MIPS table added Minor changes some pages
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC ®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®2, ISAC®-P, ISAC ®-S, ISAC®-S ISAC®-P ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI® registered trademarks Infineon Technologies ACETM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUTare trademarks Infineon Technologies
Edition 10.99 Published Infineon Technologies 81541 Infineon Technologies 1999. Rights Reserved. Attention please! patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 Infineon Technologies only used life-support devices systems2 with express written approval Infineon Technologies critical component component used life-support device system whose failure reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endangered.
2170
Table Contents 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.6.6 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.5.1 2.10 2.11 2.12 2.13 2.14 2.15
Page
Overview Features Configuration Definitions Functions Logic Symbol Functional Block Diagram System Integration Full-Duplex Speakerphone ISDN Terminal Full-Duplex Speakerphone Terminal DECT Basestation with Full-Duplex Speakerphone Videophone with External Line Interface Videophone with Software Video Compression Full-Duplex Speakerphone Environment Backward Compatibility Functional Units Full-Duplex Speakerphone Echo Cancellation Unit Noise Reduction Echo Suppression Comfort Noise Generator Noise Controlled Adaptation Line Echo Cancellation Unit DTMF Detector Call Progress Tone Detector Alert Tone Detector Universal Tone Detector Caller Decoder DTMF Generator Analog Interface Digital Interface Universal Attenuator Automatic Gain Control Unit Noise Reduction Unit Equalizer Tone Generator Peak Detector Miscellaneous Reset Power Down Mode Control Register Interrupt Abort
10.99
Preliminary Data Sheet
2170
Table Contents 3.6.1 3.6.2 3.6.3 3.6.4 4.2.1 4.2.2 4.5.1 4.5.2 4.5.3
Page
Revision Register Hardware Configuration Frame Synchronization Clock Tracking Clock Source Used Clock Frame Sync Gereration Restrictions Mutual Dependencies Modules Interfaces IOM®-2 Interface SSDI Interface SSDI Interface Transmitter SSDI Interface Receiver Analog Front Interface Serial Control Interface General Purpose Parallel Port Static Mode Multiplex Mode Interrupt Generation Detailed Register Description .101 Status Register .101 Hardware Configuration Registers .102 Electrical Characteristics .273 Absolute Maximum Ratings .273 Characteristics .273 Characteristics .274 Package Outlines .286
Preliminary Data Sheet
10.99
2170
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
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Configuration Logic Symbol 2170 Block Diagram Full-Duplex Featurephone ISDN Terminal Full-Duplex Featurephone Terminal DECT Basestation with Full-Duplex Speakerphone Videophone with External Line Interface (Hardware Video Codec). Videophone with External Line Interface (Software Video Codec) Full-Duplex Speakerphone Environment. Functional Units Overview Functional Units Speakerphone. Speakerphone Signal Connections Speakerphone Block Diagram Echo Cancellation Unit (Fullband Mode) Block Diagram Echo Cancellation Unit Double Talk Reduction Echo Cancellation Unit (Subband Mode) Block Diagram Echo Cancellation with Noise Reduction (Subband Mode) Coupling with Echo Suppression Unit States Operation Echo Suppression Unit Block Diagram Speech Detector Block Diagram Speech Comparator Block Diagram Speech Comparator Acoustic Echoes Speech Comparator Interdependence Parameters Echo Suppression Unit Automatic Gain Control Comfort Noise Generator Integration into Speakerphone Correlation Adaptation Double Talk Detection Adaptation Adaptive Attenuation Reduction. Loudspeaker Gain Adaptation Line Echo Cancellation Unit Block Diagram Line Echo Cancellation Unit Superior Mode with Shadow DTMF Detector Block Diagram Call Progress Tone Detector Block Diagram Call Progress Tone Detector- Cooked Mode Alert Tone Detector Block Diagram Universal Tone Detector Block Diagram Caller Decoder Block Diagram DTMF Generator Block Diagram Analog Frontend Interface Block Diagram Digital Interface Block Diagram Universal Attenuator Block Diagram
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Preliminary Data Sheet
2170
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
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Automatic Gain Control Unit Block Diagram Noise Reduction Block Diagram Equalizer Block Diagram Tone Generator Block Diagram Tone Generator Tone Sequences Peak Detector Block Diagram Operation Modes State Chart IOM®-2 Interface Frame Structure SSDI/IOM®-2 Interface Frame Start IOM®-2 Interface Single Clock Mode IOM®-2 Interface Double Clock Mode IOM®-2 Interface Channel Structure. SSDI Interface Transmitter Timing SSDI Interface Active Pulse Selection SSDI Interface Receiver Timing Analog Front Interface Frame Structure. Analog Front Interface Frame Start Analog Front Interface Data Transfer. Configuration Register Read Access Configuration Register Write Access Register Read Command Status Register Read Access Data Read Access Register Write Access General Purpose Parallel Port Multiplex Mode Input/Output Waveforms AC-Tests .274 Oscillator Circuit. .278 SSDI/IOM®-2 Interface Synchronization Timing .279 SSDI/IOM®-2 Interface Frame Synchronization Timing .279 SSDI Interface Strobe Timing .281 Interface .282 Analog Front Interface .283 General Purpose Parallel Port Multiplex Mode .284 Reset Timing .285
Preliminary Data Sheet
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2170
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
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Definitions Functions Signal Summary. Echo Cancellation Modes Mode (QU) Encoding. Echo Cancellation Unit Registers Subband Mode Registers Noise Reduction Registers Speech Detector Parameters. Speech Comparator Parameters Attenuation Control Parameters. Encoding Automatic Gain Control Parameters Fixed Gain Parameters Speakerphone Registers Comfort Noise Generator Registers. general Noise Control Adaption Register. Correlation Adaptation Registers Double Talk Detection Adaptation Registers Adaptive Attenuation Reduction Registers Loudspeaker Gain Adaptation Registers Power Down Register Interrupt Source Summary Frame Synchronization Selection Dependencies Modules Reprogram parameters Module Weights SSDI IOM®-2 Interface IOM®-2 Interface Registers. SSDI Interface Register Control Amplifier. Analog Front Interface Register Analog Front Interface Clock Cycles Command Words Register Access Address Field Configuration Register Write Address Field Configuration Register Read General Purpose Parallel Port Mode Registers Static Mode Registers Multiplex Mode Registers. Interrupt Mask Definition Parallel Port Status Register Update Timing
Preliminary Data Sheet
10.99
2170
Overview
General General
Overview
2170, Version provides full-duplex speakerphone analog digital featurephones. assure excellent speech quality even noisy environments like cars, 2170 provides acoustic echo cancellation, comfort noise insertion, noise reduction adaptive environment. Depending requirements runtime delay, this performed fullband subband mode. Furthermore Version features caller decoder (Bellcore compliant), DTMF recognition generation call progress tone detection. frequency response cheap microphones loudspeakers corrected programmable equalizers. provides IOM®-2 compatible interface with three channels speech data. Alternatively IOM®-2 compatible interface, supports simple serial data interface (SSDI) with separate strobe signals each direction (linear data, channel). separate interface used glueless connection 4851 (dual codec). chip programmed simple four wire serial control interface inform microcontroller events interrupt signal. supports interface pins input levels.
Preliminary Data Sheet
10.99
Acoustic Echo Canceller
2170
Version
CMOS
Features
modes acoustic echo cancellation: ERLE1) @16-80 0.25-2 delay ERLE1) @60-159 delay Fast adaptation without learning tone noise reduction blocks Comfort noise generator Line echo cancellation without learning tone DTMF tone generation Flexible ringing generation Programmable side gain transducer correction filters (equalizer) DTMF tone detector Call progress tone detector Universal tone detector Caller decoder General purpose parallel port bits) Independent gain channels Serial control interface programming 3.3V power supply, interface IOM®-2 interface (three data channels) Interface 4851 Interface Burst Mode Controllers
P-MQFP-80
ERLE: Echo Return Loss Enhancement
Type 2170
Preliminary Data Sheet
Package P-MQFP-80
10.99
2170
Overview
Configuration
(top view)
GP10 GP11 GP12 GP13 GP14 GP15
SPS1 SPS0 DRST DXST DD/DR DU/DX
Figure
Configuration
Preliminary Data Sheet
VDDA XTAL1 XTAL2 VSSA SCLK AFEFS AFECLK AFEDD AFEDU
10.99
2170
Overview
Table
P-MQFP-80
Definitions Functions
Definitions Functions Symbol Dir.1) Reset Function Power supply (3.3V Power supply logic.
VDDA VSSA
Power supply (3.3V Power supply clock generator. Power supply Ground clock generator. Power supply Ground logic interface.
AFEFS
Analog Frontend Frame Sync: frame synchronization signal communication with analog frontend. Analog Frontend Clock: Clock signal analog frontend (6.912 MHz). Analog Frontend Data Downstream: Data output analog frontend. Analog Frontend Data Upstream: Data input from analog frontend. Reset: Active high reset signal. Data Frame Synchronization: frame synchronization signal (IOM®-2 SSDI mode). Data Clock: Data Clock serial data IOM®-2 compatible SSDI interface.
AFECLK
AFEDD AFEDU
Preliminary Data Sheet
10.99
2170
Overview Table Definitions Functions DD/DR I/OD DU/DX I/OD DXST DRST SCLK XTAL1 XTAL2 SPS0 SPS1 IOM®-2 Compatible Mode: Receive data from IOM®-2 controlling device. SSDI Mode: Receive data strobed serial data interface. IOM®-2 Compatible Mode: Transmit data IOM®-2 controlling device. SSDI Mode: Transmit data strobed serial data interface. Strobe: Strobe SSDI interface mode. Strobe: Strobe SSDI interface mode. Chip Select: Select signal serial control interface (SCI). Serial Clock: Clock signal serial control interface (SCI). Serial Data Receive: Data input serial control interface (SCI). Serial Data Transmit: Data Output serial control interface (SCI). Interrupt status available. Alternative AFECLK Source 13,824 Oscillator: XTAL1: External clock input oscillator loop. XTAL2: output oscillator loop crystal. Speakerphone State: Current speakerphone unit state, general purpose outputs status register output
Preliminary Data Sheet
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2170
Overview Table Definitions Functions GP10 GP11 GP12 GP13 GP14 GP15 General Purpose Parallel Port 0-15: General purpose I/O.
Reserved Output: connect. Reserved Input: Connect Vss.
connected
Input Output Open Drain These lines driven with (typical) during reset.
Preliminary Data Sheet
10.99
2170
Overview
Logic Symbol
XTAL1 XTAL2 DU/DX AFECLK DD/DR
4851
AFEFS AFEDD AFEDU
2170
DXST DRST
IOM®-2 SSDI
SCLK
GP0-GP15
Parallel Port
Figure
Logic Symbol
Preliminary Data Sheet
10.99
2170
Overview
Functional Block Diagram
XTAL1 XTAL2
Reset Timing Unit
AFECLK AFEFS AFEDD AFEDU Analog Frontend Interface
DRST DXST
Data Interface
DU/DX DD/DR
Control Interface
Parallel Port
SCLK
GP0-GP15
Figure
2170 Block Diagram
Preliminary Data Sheet
10.99
2170
Overview
System Integration
2170 provides full-duplex speakerphone variety applications. Some applications given following sections.
1.6.1
Full-Duplex Speakerphone ISDN Terminal
Figure shows example ISDN featurephone with 2170 providing fullduplex speakerphone.
2170
IOM®-2
SCOUT-S S0-BUS 21381
077-3445
Power Controller Microcontroller 2023
Figure
Full-Duplex Featurephone ISDN Terminal
Preliminary Data Sheet
10.99
2170
Overview
1.6.2
Full-Duplex Speakerphone Terminal
Figure shows example phone with 2170 providing full-duplex speakerphone.
2170
IOM®-2
SCOUT-P UPN-BUS 21381
077-3445
Microcontroller
DC/DC Converter
Figure
Full-Duplex Featurephone Terminal
Preliminary Data Sheet
10.99
2170
Overview
1.6.3
DECT Basestation with Full-Duplex Speakerphone
Figure shows DECT basestation with acoustic echo cancellation based 2170. full-duplex speakerphone switched basestation mobile handset dynamically. programming, serial control interface (SCI) used while voice data transferred strobed serial data interface (SSDI).
4851
2170 Antenna
®-2/SSDI
077-3445
tip/ ring Microcontroller
Burstmode Controller
DECT
line
Figure
DECT Basestation with Full-Duplex Speakerphone
Preliminary Data Sheet
10.99
2170
Overview
1.6.4
Videophone with External Line Interface
videophone using external line interface with 2170 providing full-duplex speakerphone shown figure
ARCOFI
2161
2170
JADE Video Codec 7238
Interface
Figure
Videophone with External Line Interface (Hardware Video Codec)
transmit direction 2161 (ARCOFI provides uncompressed audio data from microphone acoustic echo canceller (PSB 2170). acoustic echo canceller provides echo-free data audio compression device JADE (PSB 7238). JADE offers necessary compression algorithms cover H.320/323/ applications, i.e. ITU-T G.711, G.722, G.723 G.728. compressed data then multiplexed into audio/video data stream video codec. video codec turn sends combined data interface host unit (e.g. which passes line interface (e.g. ISAC-S ISDN, V.34bis modem POTS Ethernet adapter LAN). receive direction same signal path used other direction. off-board line interface offers advantage videophone board applicable different lines such ISDN (H.320), (H.323) POTS (H.324, plain telephone system) just exchanging line interface card some control software
Preliminary Data Sheet
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2170
Overview
1.6.5
Videophone with Software Video Compression
videophone using software video compression with 2170 providing fullduplex speakerphone shown figure
ARCOFI
2161 IOM®-2
2170
JADE
7238
Interface 6120
Figure
Videophone with External Line Interface (Software Video Codec)
transmit direction 2161 (ARCOFI provides uncompressed audio data from microphone acoustic echo canceller (PSB 2170). acoustic echo canceller provides echo-free data audio compression device JADE (PSB 7238). JADE offers necessary compression algorithms cover H.320/323/ applications, i.e. ITU-T G.711, G.722, G.723 G.728. compressed data then transmitted host processor interface (e.g. using interface 6120). host processor also captures uncompressed video data through same interface does video compression multiplexing software. multiplexed data stream then passed corresponding line interface (e.g. ISAC-S ISDN, V.34bis modem POTS Ethernet adapter LAN). receive direction same signal path used other direction. only H.324 (POTS) videophones shall supported, JADE (PSB 7238) substituted JADE (PSB 7230), which offers only ITU-T G.723.1 compression needed H.324. combi-design JADE JADE also possible, thus offering both solutions assembly options. JADE data sheet details.
Preliminary Data Sheet 10.99
2170
Overview off-board line interface offers advantage videophone board applicable different lines such ISDN (H.320), (H.323) POTS (H.324, plain telephone system) just exchanging line interface card some control software limited computational power host processor (e.g. Intel Pentium), video quality using software compression usually does reach quality separate video processor. Nevertheless, accepted customer this offers very cost solution videoconferencing.
1.6.6
Full-Duplex Speakerphone Environment
several special provisions operation noisy environments like cars. Most important noise reduction blocks. built transmit path speakerphone. other free module that inserted into path. Figure shows application where provides full-duplex speakerphone mobile communications unit car.
2170
4851
Figure
Full-Duplex Speakerphone Environment
receives (transmits) analog data from (to) mobile communications unit first codec 4851. microphone loudspeaker mobile communications unit muted. Instead them loudspeaker microphone mounted used. They connected directly second channel 4851.
Preliminary Data Sheet
10.99
2170
Overview
Backward Compatibility
2170 Version backwards compatible with 2170 Version with respect Configuration Supply Voltage Signal Levels Start-up Sequence after Reset Register Definition modules with exception speakerphone
speakerphone significantly changed improved. Some registers have become obsolete, others have been added. Therefore, registers speakerphone compatible 2170 Version 1.1. other additional features 2170 Version enabled previously unused bits Hardware Configuration Registers Read/Write Registers additional registers. Furthermore, status bits updated faster which should have impact backwards compatibility.
Preliminary Data Sheet
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2170
Functional Units
Functional Units Functional Units
Functional Units
2170 contains several functional units that combined with almost restrictions perform given task. Figure shows functional units available within ACE.
SSDI/IOM Channel 4851 Channel Noise Reduction DTMF Generator
acoustic side
IOM®-2 Channel
IOM®-2 Channel
4851 Channel
Universal Attenuator
Tone Generator
Speakerphone
line side
Line Echo Canceller Detector Detector Alert Tone Detector
Equalizer
Equalizer
Decoder
DTMF Detector
signal summation:
signal sources: S1,.,S21
Figure
Functional Units Overview
10.99
Preliminary Data Sheet
2170
Functional Units Each unit more signal inputs (denoted Most units have least signal output (denoted input connected signal output addition signals shown figure there also signal (silence), which useful signal summation points. Table lists available signals within according their reference points. Table Signal Signal Summary Description Silence Analog line input (Channel 4851 interface) Analog line output (Channel 4851 interface) Microphone input (Channel 4851 interface) Loudspeaker/Handset output (Channel 4851 interface) Serial interface input, Channel Serial interface output, Channel Serial interface input, Channel Serial interface output, Channel DTMF generator output DTMF generator auxiliary output Speakerphone output (acoustic side) Speakerphone output (line side) reserved Universal attenuator output Line echo canceller output Automatic gain control output (after gain stage) Automatic gain control output (before gain stage) Equalizer output Equalizer output Tone generator output Tone generator output reserved Serial interface input, channel Serial interface output, channel output
10.99
Preliminary Data Sheet
2170
Functional Units following sections describe functional units detail. Figure gives example units combined when hands-free phone conversation progress. Units that needed shown. Unused inputs connected which provides silence (denoted equalizers used improve quality microphone loudspeaker. alert tone detector recognizes alert tone off-hook caller request while decoder then decodes actually transmitted data.
loudspeaker microphone
line line
Equalizer
acoustic side
Equalizer
Speakerphone
line side
Line Echo Canceller
Alert Tone Detector
Decoder
Figure
Functional Units Speakerphone
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Preliminary Data Sheet
2170
Functional Units. Functional Units
Full-Duplex Speakerphone
speakerphone unit (figure attached four signals (microphone, loudspeaker, line line in). input signals (microphone, line preceded signal summation point.
microphone
loudspeaker
line
Speakerphone
line
Figure
Speakerphone Signal Connections
Internally, this unit divided into echo cancellation unit echo suppression unit (figure 13). echo cancellation unit provides attenuation while echo suppression unit provides attenuation total attenuation speakerphone therefore ATT=GC+Gs.
microphone
loudspeaker
Echo Cancellation
Echo Suppression
line
line
Figure
Speakerphone Block Diagram
echo cancellation unit estimates that part signal microphone that originates from loudspeaker. This part then subtracted from signal microphone. This technique allows full-duplex speakerphone. Furthermore, echo cancellation unit built-in noise reduction unit better sound quality line side. echo suppression unit attenuates receive transmit path dependent what path active. Without echo cancellation unit using high attenuation echo suppression unit, echo suppression unit provides half-duplex speakerphone.
Preliminary Data Sheet 10.99
2170
Functional Units echo cancellation unit active cannot provide required attenuation itself, echo suppression unit used provide additional attenuation.
2.1.1
Echo Cancellation Unit
echo cancellation unit operating modes: fullband subband mode. Table shows basic differences modes. Table max. echo length delay Echo Cancellation Modes fullband mode 16-80 0.25-2 subband mode 50-159
selection between modes performed with parameter summarized table different modi described sequel. Table Mode (QU) Encoding Acoustic Echo Cancellation Modes Echo cancellation disabled (half duplex) Subband, Fullband mode (similar 2170 Version 1.1) Fullband mode Subband, reduced filter length (car application) Subband, analog line mode Subband, ISDN mode Subband, enhanced mode
Preliminary Data Sheet
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2170
Functional Units 2.1.1.1 Echo Cancellation (Fullband Mode)
simplified block diagram fullband echo cancellation unit shown figure
microphone
line
Control
NLMS
Filter
loudspeaker
line
Figure
Echo Cancellation Unit (Fullband Mode) Block Diagram
echo cancellation unit consists finite impulse response filter (FIR) that models expected acoustic echo, NLMS based adaptation unit control unit. expected echo subtracted from actual input signal from microphone. model exact echo does exceed length filter, then echo cancelled completely. However, even this ideal state achieved given moment, acoustic echo usually changes over time. Therefore NLMS unit continuously adapts coefficients filter. This adaptation process steered control unit. example, adaptation inhibited long double talk detected control unit. Furthermore control unit informs echo suppression unit about achieved echo return loss. length programmed parameters FBLEN. With parameter echo cancellation unit into different fullband modes (section 2.1.1). fullband mode similar mode provided 2170 Version 1.1. this mode, noise reduction (chapter 2.1.2) cannot enabled. delay added this mode 0.25 fullband mode two, delay shorter than this delay acceptable, delay reduced less than setting ERD. performance fullband mode suffer this reduced mode please note that enabling noise reduction will some additional delay (section 2.1.2).
Preliminary Data Sheet
10.99
2170
Functional Units order detect double talk, remaining speech signal after echo cancellation (signal after summation point figure compared signal expected echo cancellation unit (after signal summation point figure 14). difference energy these signals considered. this energy greater than allowed parameter AECDTM, double talk detected. When double talk detected, attenuation echo cancellation reduced since echo less noticeable anyway possible signal distortion from echo cancellation reduced. parameter AECDTR determines maximal reduction attenuation during double talk. rate fast attenuation reduction gets active after double talk detection inactive after double talk determined parameters AECDTI AECDTD, respectively.
double talk detected double talk
Example:
time
AECDTR
attenuation level
Figure
Echo Cancellation Unit Double Talk Reduction
echo cancellation unit reports current attenuation echo suppression unit. This following reason: echo cancellation does provide enough attenuation, echo suppression used additionally. attenuation echo cancellation unit insufficient when echo cancellation unit well adapted. case significant change characteristics acoustics, attenuation reported echo cancellation unit high until discovers that adapt itself again. addition, double talk reduction effect, then echo suppression unit might attenuate enough avoid echoes. Therefore maximal echo return loss reported echo cancellation unit echo suppression unit programmed parameter AECLIM. fullband mode two, number parameters that adapted every programmed parameter FBADA. maximum number taps that their parameters adapted 256. example number taps used
Preliminary Data Sheet
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2170
Functional Units FBADA 256, parameters lower taps upper taps updated alternately. value FBADA therefore following effects: First, higher FBADA faster thus echo canceller adapted. Second, with increasing FBADA, comutational costs increase. affordable from computational costs (see chapter 3.7), FBADA should maximum value. Table shows registers associated with echo cancellation unit fullband mode. Table Register SCTL SCTL SAELEN SAEAW SAEEL SAEDTR SAEDTL SAEDTI SAEDTD Echo Cancellation Unit Registers Bits Name Comment Determine modes (see table Enable reduced delay fullband mode. Length filter. Length adaption window. mode only) Maximum attenuation reported unit. attenuation reduction during double-talk. Minimum energy detect double talk. fast attenuation reduction gets incremented. fast attenuation reduction gets decremented. FBLEN FBADA AECLIM AECDTR AECD15 AECDTI AECDTD
length filter echo compensation varied from taps (~68 comfort noise (chapter 2.1.4) enabled taps (~80 fullband mode used comfort noise disabled taps (~80 fullband mode used comfort noise disabled taps (~96 fullband mode used same module subband ISDN mode disabled (chapter 3.7).
length adaption window varied from taps ms).
Preliminary Data Sheet
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2170
Functional Units 2.1.1.2 Echo Cancellation (Subband Mode)
simplified block diagram subband echo cancellation unit shown figure signal coming from microphone signal from line side analyzed into several subbands. Then each subband, block diagram figure identical block diagram fullband mode. After echo cancellation each subband, subbands synthesized. Finally additionally fullband mode, subband mode optional Wiener filter (called figure provided.
microphone
Analysis
Synthesis
line
Control
NLMS
Filter
Analysis
loudspeaker
line
Figure
Echo Cancellation Unit (Subband Mode) Block Diagram
subband mode enabled five different submodes. These submodes offer trade-off between maximum echo length functional units that simultaneously (see chapter 3.7). units that cannot simultaneously must disabled before subband echo cancellation unit enabled. After subband echo cancellation unit disabled, parameters affected units must rewritten microcontroller. optional Wiener filter, maximum attenuation programmed with parameter WFATT. Wiener filter enabled, only active while there speech detected near side (microphone). shown figure total attenuation provided speakerphone consists attenuation (provided echo cancellation unit) (provided echo suppression unit). subband mode attenuation further split into (provided adaptive filter) (provided Wiener filter).
Preliminary Data Sheet
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2170
Functional Units already exceeds WFATT good adaptation then Wiener filter deactivated GC=GA. Otherwise WFATT limits attenuation Wiener filter such that GC=GA+GW never exceeds WFATT. Table shows registers associated with subband echo cancellation unit. parameters AECATT, AECLIM, AECDTM, AECDTI AECDTD have same meaning fullband mode. Note that reported echo loss parameter AECLIM cover complete echo cancellation unit including Wiener filter. Table Register SCTL SCTL SAEWFL SAEDTR SAEEL SAEDTL SAEDTI SAEDTD Subband Mode Registers Bits Name WFATT AECATT AECLIM AECDAECDTI AECDTD Comment Determine modes Wiener filter enable (subband only) Wiener filter attenuation limit attenuation reduction during double-talk Upper limit attenuation Minimum energy detect double talk fast attenuation gets incremented. fast attenuation gets decremented.
shown table with control bits different modes acoustic echo cancellation unit selected. subband mode, four different modes provided. With increasing number considered echo length increases does computational effort. Before selecting mode, incompatibilities described chapter must considered.
2.1.2
Noise Reduction
2170 offers noise reduction block built echo cancellation unit. This noise reduction suppresses noise before signal output line side. This makes conversation more pleasant person line side. fullband mode, noise reduction only enabled fullband mode used. noise reduction performed after echo cancellation thus considered additional block after echo cancellation shown figure Note that noise reduction adds about delay signal. SCTL:ERD set, then delay echo cancellation noise reduction still below subband mode, noise suppression performed each subband. Figure shows noise reduction block (called matches echo cancellation unit. noise reduction adds delay signal.
Preliminary Data Sheet 10.99
2170
Functional Units
microphone
Analysis
Synthesis
line
Control
NLMS
Filter
Analysis
loudspeaker
line
Figure
Echo Cancellation with Noise Reduction (Subband Mode)
parameter NRATT determines maximum attenuation provided noise reduction unit frequencies with noise. Note that NRATT determines upper limit. With decreasing level background noise, attenuation noise reduction unit decreases well. subband mode, Wiener filter enabled speech detected microphone, Wiener filter provides attenuation signal from microphone. noise present microphone thus noise reduction unit changes signal coming from microphone, then additional attenuation Wiener filter cause modulations audible line side. Therefore, coupling noise reduction unit Wiener filter provided. case noise present near end, Wiener filter attenuates programmed with parameter SWATT:WFATT. case significant noise present near end, Wiener filter only attenuates much that attenuation noise reduction plus attenuation Wiener filter never exceeds NRATT. This controlled with parameters: parameter NRUP determines noise energy which coupling between noise reduction Wiener filter gets active. parameter NRLOW determines noise energy which coupling gets inactive. This value should lower than NRUP order avoid frequent activation deactivation, when noise energy around level NRUP illustrated figure
Preliminary Data Sheet
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2170
Functional Units Table Register SCTL SNRATT SNRLNL SNRUNL Noise Reduction Registers Bits Name NRATT NRLOW NRUP Comment Enable noise reduction Maximal attenuation frequencies with noise. Lower limit deactivate coupling. Upper limit activate coupling.
background noise level
NRUP NRLOW
start
NR-WF coupling
NR-WF coupling
time
Figure
Coupling with
2.1.3
Echo Suppression
echo suppression unit three states: transmit state receive state idle state transmit state microphone signal drives line output while line input attenuated. receive state loudspeaker signal driven line input while microphone signal attenuated. idle state both signal paths active with evenly distributed attenuation.
Preliminary Data Sheet
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2170
Functional Units
transmit state
microphone loudspeaker
line line
receive state
microphone loudspeaker
line line
idle state
microphone loudspeaker
line line
Figure
Echo Suppression Unit States Operation
Preliminary Data Sheet
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2170
Functional Units Figure shows signal flow graph echo suppression unit more detail.
microphone
AGCX
LGAX
line
SCAS
Attenuation Control
SCLS
loudspeaker
LGAR
AGCR
line
Figure
Echo Suppression Unit Block Diagram
Attenuation Control performs switching between three possible states using attenuation stages GHR. Actually, state switching controlled speech comparators SCAS SCLS speech detectors SDR. gain control units AGCX, AGCR, LGAX, LGAR used achieve proper signal levels each state. blocks programmable. Thus, telephone optimized adjusted particular geometrical acoustical environment. following sections discuss blocks echo suppression unit detail.
Preliminary Data Sheet
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2170
Functional Units 2.1.3.1 Speech Detector
each signal source speech detector (SDX, SDR) available. speech detectors identical programmed individually. Figure shows signal flow graph speech detector.
Signal Preprocessing
LP2S LP2N LP2L
Background Noise Monitor
Figure
Speech Detector Block Diagram
first three units (LIM, LP1, used preprocessing signal while actual speech detection performed background noise monitor. Background Noise Monitor tasks noise monitor differentiate voice signals from background noise, even exceeds voice level, recognize voice signals without delay. Therefore Background Noise Monitor consists Low-Pass Filter (LP2) offset separate branches. Basically works burst-characteristic speech: voice signals consist short peaks with high power (bursts). contrast, background noise regarded approximately stationary from average power. Low-Pass Filter provides different time constants noise (non-detected speech) speech. determines average noise reference level. case background noise level output approximately level input. other branch additional offset added signal, comparator signals noise. speech bursts digital signals arriving comparator offset branch change faster than those LP2-branch. difference exceeds offset OFF,
Preliminary Data Sheet
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Functional Units comparator signals speech. Therefore output background noise monitor digital signal indicating speech noise (0). small fade constant (LP2N) enables fast settling average noise level after speech recognition. However, small time constant LP2N cause rapid charging such high level that after recognizing speech danger unwanted switching back noise exists. recommended choose large rising constant (LP2S) that speech itself charges very slowly. Generally, recommended choose infinite LP2S because then approaching noise level disabled. During continuous speech tones will charged until limitation LP2L reached. Then value frozen until break discharges LP2. This limitation permits transmission continuous tones "music hold". offset stage represents estimated difference between speech signal averaged noise. Signal Preprocessing described preceding chapter, background noise monitor able discriminate between speech noise. very short speech pauses e.g. between words, however, changes immediately non-speech, which equal noise. Therefore peak detection required front Noise Monitor. main task Peak Detector (PD) bridge very short speech pauses during monolog that this time constant long. Furthermore, speech bursts stored that sure speech detection guaranteed. speech recognized noise low-pass must charged faster average noise level. addition, noise edges smoothed. Therefore time constants necessary. peak detector very sensitive spikes, low-pass filters incoming signal containing noise that main spikes eliminated. programmable time constant possible refuse high-energy sibilants noise edges. compress speech signals their amplitudes ease detection speech, signals have companded logarithmically. Hereby, speech detector should influenced system noise which always present should discriminate between speech background noise. limitation logarithmic amplifier programmed parameter LIM. related maximum level. signal exceeding limitation defined getting amplified logarithmically, while very smooth system noise below neglected. should level minimum system noise which always existing; transmit path noise generated telephone circuitry itself receive direction level first which stable without speech signal receive path. Table shows parameters speech detector.
Preliminary Data Sheet
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Functional Units Table LP2S LP2N LP2L Speech Detector Parameters Comment Limitation log. amplifier Level offset detected noise Peak decrement (speech) Peak decrement (noise) Time constant Time constant (speech) Time constant (noise) Maximum value 2000 2000 2000 2000
Parameter bytes Range
input signal speech detector connected either input signal echo suppression unit shown SDX) output associated shown SDR).
Preliminary Data Sheet
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Functional Units 2.1.3.2 Speech Comparators (SC)
echo suppression unit identical speech comparators (SCAS, SCLS). Each comparator programmed individually accommodate different system characteristics acoustic interface line interface. SCAS SCLS identical, following description holds both SCAS SCLS. input signals which microphone/loudspeaker SCAS line in/line SCLS. speech comparator decides whether signal coming only echo from signal outgoing real speech activity. result then interpreted Attenuation Control figure general, works according following equation: then switch state
Therefore, SCAS controls switching transmit state SCLS controls switching receive state. Switching done only exceeds least expected acoustic level enhancement This level enhancement divided into parts: block diagram shown figure
Log. Amp.
Peak Decrement
Log. Amp.
Base Gain
Gain Reserve
Peak Decrement
Figure
Speech Comparator Block Diagram
both inputs, logarithmic amplifiers compress signal range. Hence, only logarithmic levels both paths after signals have been processed, logarithmic levels both paths compared.
Preliminary Data Sheet
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Functional Units main task comparator control echo. internal coupling direct sound mechanical resonances covered external coupling, mainly caused acoustic feedback, controlled GD/PD. example direct sound acoustic feedback illustrated figure
Figure Speech Comparator Acoustic Echoes
base gain corresponds terminal couplings complete telephone. Thus, measured calculated level enhancement between receive transmit inputs control acoustic feedback parameters necessary: represents actual reserve measured Together with Peak Decrement (PD), echo behavior acoustic side modeled: After speech ended there short time during which hard couplings through mechanics resonances direct echo present. Till that time (t), level enhancement must least equal prevent clipping caused these internal couplings. After that time (t), only acoustic feedback present. This coupling, however, reduced attenuation. this general longer delay, smaller echo being valid. This echo behavior taken care decrement rate
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Functional Units
RX-Speech
RX-noise
Figure Speech Comparator Interdependence Parameters
According figure compromise between reserve decrement made: smaller reserve (GD) above level enhancement requires longer time decrease (PD). easy overshout other side intercommunication harder because after speech, level estimated echo exceeded. contrary, with higher reserve (GD*) harder overshout continuous speech tones, enables faster intercommunication because stronger decrement (PD*). pairs coefficients, GDS/PDS when speech detected, GDN/PDN case noise, offer different echo handling speech non-speech. With speech, even very strong resonances present, performance will worsened high needed. Only when speech detected, high reserve prevents clipping. time [ms] after speech ends, parameters comparator switched "noise" values. both sets parameters equal, effect. Table Speech Comparator Parameters Comment Base Gain Gain Reserve (Speech) Peak Decrement (Speech)
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Parameter bytes Range 0.025 dB/ms
Preliminary Data Sheet
2170
Functional Units Table Speech Comparator Parameters Comment Gain Reserve (Noise) Peak Decrement (Noise) Time Switch from speech noise parameters 0.025 dB/ms
Parameter bytes Range
2.1.3.3
Attenuation Control
attenuation control unit performs state switching controlling attenuation stages GHR. receive state, attenuation completely switched GHX. transmit state, attenuation completely switched GHR. idle state, both attenuate G/2. State switching depends signals speech comparator corresponding speech detector. attenuation programmable. attenuation actually provided attenuation stages attenuation determined parameter minus attenuation reported echo cancellation unit GC). Additional (fixed) attenuation transmit receive path also influenced automatic gain control stages AGCX AGCR, respectively. While each state associated with programmed attenuation, time takes reach steady-state attenuation after state switch programmed. time depends programmable decay rate current attenuation formula current state either transmit receive speech either side been detected time then idle state entered. smoothen transition, attenuation incremented (decremented) until evenly distribution both reached. Table summarizes parameters attenuation unit. Table Attenuation Control Parameters Comment return idle state Attenuation Decay Speed idle state) ms/dB
Parameter bytes Range
0.0052 ms/dB Decay Rate (used TSW)
Note: addition, attenuation also influenced Automatic Gain Control stages (AGCX, AGCR) order keep total loop attenuation constant.
Preliminary Data Sheet
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Functional Units Note: programming parameter 0xFF idle mode disabled speakerphone will remain last state. This parameter must before enabling speakerphone. 2.1.3.4 Echo Suppression Status Output
2170 report current state echo suppression unit ease optimization parameter echo suppression unit. this case SPS0 SPS1 pins according table Table SPS0 Encoding SPS1 Echo Suppression Unit State echo suppression operation receive transmit idle
Furthermore controller read current value pins reading register SPSCTL. 2.1.3.5 Loudhearing
speakerphone unit also used controlled loud-hearing. This enabled setting register SCTL. loud-hearing mode enabled, loudspeaker amplifier 4851 (ALS) used instead (figure when appropriate avoid oscillation. this feature, 4851 must programmed allow override. field within control register AFECTL defines value sent 4851 attenuation necessary (see specification 4851). 2.1.3.6 Automatic Gain Control
echo suppression unit identical automatic gain control units AGCX AGCR both referred this section. Whether automatic gain control amplifies attenuates depends whether signal level above below threshold level defined parameter COM. threshold relative maximum PCM-value thus negative. parameters AG_GAIN AG_ATT determine maximal amplification attenuation, respectively. bold line figure gives example steady-state output level function input level.
Preliminary Data Sheet
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Functional Units
input level
max.
Example: AG_GAIN AG_ATT
AG_ATT
output level
AG_GAIN
Figure
Echo Suppression Unit Automatic Gain Control
reasons physiological acceptance, gain automatically reduced case continuous background noise (e.g. ventilators). reduction programmed NOlS parameter. When noise level exceeds threshold determined NOIS, amplification will reduced same amount noise level greater than threshold. regulation speed controlled SPEEDH signal amplitudes above threshold SPEEDL amplitudes below. Usually SPEEDH will chosen least times faster than SPEEDL. additional pass with time constant provided avoid immediate response very short signal bursts. time constant pass should selected longer than order avoid unstable behavior. speech detector detects noise receive path active, AGCX freezes current attenuation last gain setting used. Regulation starts with this value soon detects speech receive path inactive. Likewise, detects noise transmit path active, AGCR freezes current attenuation last gain setting used. Regulation starts with this value soon detects speech transmit path inactive. current gain/attenuation read time (AG_CUR). When been disabled, initial gain used immediately after enabling programmed. Table shows parameters AGC.
Preliminary Data Sheet
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Functional Units Table AG_INIT AG_ATT AG_GAIN AG_CUR SPEEDL SPEEDH NOIS Automatic Gain Control Parameters Comment Initial gain/attenuation Compare level rel. max. PCM-value Attenuation range Gain range Current gain/attenuation Change rate lower levels Change rate higher levels Threshold AGC-reduction background noise pass time constant 95dB 0.25 62.5 dB/s 0.25 62.5 dB/s 0.025
Parameter Bytes Range
Note: There sets parameters, AGCX AGCR. Note: setting AG_GAIN limitation function realized with AGC. 2.1.3.7 Fixed Gain
Each signal path features additional amplifier (LGAX, LGAR) that fixed gain. These amplifiers should used basic amplification order avoid saturation preceding stages. Table shows only parameter this stage. Table 2.1.3.8 Fixed Gain Parameters Comment always active
Parameter Bytes Range
Mode Control
Table shows registers used determine signal sources mode. Table Register SCTL SCTL SCTL SCTL Speakerphone Registers Bits Name Comment Echo suppression unit enable Echo cancellation unit enable Speakerphone loudhearing mode AGCX enable
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Functional Units Table SCTL SCTL SCTL AFECTL SSRC1 SSRC1 SSRC2 SSRC2 Speakerphone Registers AGCR enable input input value loudhearing Input signal (microphone) Input signal (microphone) Input signal (line Input signal (line
2.1.4
Comfort Noise Generator
full duplex speakerphone extended comfort noise generator which enhance performance speakerphone noisy environments. purpose comfort noise reduce signal modulation when echo suppression unit switches attenuation. operation follows: long echo suppression unit transmit state additional noise added outgoing signal. this state there already natural noise transmitted line. addition comfort noise generator estimates noise microphone input when speech detected either three speech detectors (SD, SDX, SDR). Once echo suppression unit switches receive idle state comfort noise generator generates noise similar external noise adds this noise outgoing signal. Figure shows integration comfort noise generator into speakerphone.
Preliminary Data Sheet
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Functional Units
Comfort Noise
AGCX
LGAX
Control NLMS SCAS Control SCLS
LGAR
AGCR
Figure
Comfort Noise Generator Integration into Speakerphone
blocks Comfort Noise removed remaining blocks resemble speakerphone shown figures Therefore comfort noise generator considered optional extension speakerphone. speech detector works speech detectors described section 2.1.3.1. parameters speech detector thus same shown table
comfort noise generator adapts itself currently present noise input signal with respect energy level spectrum. Furthermore possible program constant noise level which always present (even there noise input signal present). comfort noise generator enabled with control register SCTL. Note that order comfort noise generator, noise controlled adaption must enabled well. noise controlled adaptation described next section. There three parameters comfort noise generator: adaptation speed constant noise level CONST which determines noise level that always added. factor which present noise scaled output noise generator. Table shows associated registers.
Preliminary Data Sheet
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Functional Units Table Register SCTL SCCN1 SCCN2 SCCN3 Comfort Noise Generator Registers Bits Name CONST Comment Comfort Noise enable (bit must set) Level Constant Noise Factor Multiplication Adaptation Time Constant
described chapter detail, several modules must disabled before comfort noise generator enabled. Also some parameters disabled modules overwritten noise controlled adaptation. This means that these disabled modules going enabled after comfort noise generator been used, these parameters must again.
2.1.5
Noise Controlled Adaptation
Several quantities that important full-duplex speakerphone depend level background noise. easy example correlation between signal microphone signal loudspeaker case single talk from line side. Obviously, noise present near side, signal microphone only generated acoustic echo signal from loudspeaker thus very similar signal from loudspeaker. case noise near side, similarity signals minor. Since such quantities this correlation depend noise level near side, some parameters must depend noise level order ensure true full-duplex speakerphone quality. This meant with term "noise controlled adaption". noise controlled adaptation enabled setting control register SCTL. adjustments described sequel depend level noise near side. noise level determined follows. case speech detector which described section 2.1.4, indicates that speech present, then energy microphone signal filtered pass called noise level case speech detector indicates speech, then last output pass called noise level time constant pass programmable with parameter shown table
Preliminary Data Sheet
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Functional Units Table Register SCTL SCLPT general Noise Control Adaption Register Bits Name Comment Noise adaptation enable Time constant pass
Preliminary Data Sheet
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Functional Units 2.1.5.1 Correlation Adaptation
control block (figures echo cancellation unit monitors correlation between loudspeaker signal microphone signal. Only when correlation loudspeaker microphone signal exceeds threshold attenuation achieved echo cancellation unit measured. noisy environment correlation will decrease even echo cancellation unit fully adapted. Therefore threshold might exceeded this situation. result echo cancellation unit would report achieved echo return loss enhancement thus echo suppression unit would have provide desired attenuation. avoid this situation threshold adjusted dynamically with noise level Figure shows available parameters adaptation threshold.
CORR LIMIT
Figure
Correlation Adaptation
long noise level less than threshold threshold remains programmed value CORR. This parameter only effect when noise controlled adaption enabled (SCTL:NAD set). noise controlled adaption disabled, default value used instead. With enabled noise controlled adaption, once threshold exceeded, correlation threshold decreases with programmable slope However, threshold will fall below programmable limit LIMIT even noise level increases further. Table shows registers associated with correlation adaptation. Table Register SCCR SCCRN SCCRS SCCRL Correlation Adaptation Registers Bits Name CORR LIMIT Comment Factor Noise Threshold Slope Limit
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Functional Units 2.1.5.2 Double Talk Detection Adaptation
During double talk necessary echo return loss comfortable full duplex conversation reduced. provides parameter SAEDTR:AECDTR this purpose. Double talk detected when difference between signal before after echo cancellation (subtraction point) suddenly decreases amount noisier environment gets smaller amount should Otherwise echo cancellation would fail detect relatively smaller change that indicates double talk detection. Figure shows provisions made adaptive double talk detection.
AECDDTS LIMIT
Figure
Double Talk Detection Adaptation
long noise level less than threshold necessary difference remains programmed value AECDTM. Once threshold exceeded, decreases with programmable slope DTS. However, will fall below programmable limit LIMIT even noise level increases further. Table shows registers associated with double talk detection adaptation. Table Register SAEDTL SCDTN SCDTS SCDTL Double Talk Detection Adaptation Registers Bits Name AECDNTH LIMIT Comment Minimum energy detect double talk. Noise Threshold Slope Limit
Preliminary Data Sheet
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Functional Units 2.1.5.3 Adaptive Attenuation Reduction
noisy environments acceptable reduce total attenuation (chapter 2.1) noise level increases. This fact that noise already presents some kind local talk. Hence increased echo perceived disturbing silent environment. order exploit this, provides attenuation decrease dependent noise level: Asofar ATR, where Asofar attenuation provided echo cancellation echo suppression described chapters 2.1.1 2.1.3. Figure shows attenuation reduction provided
LIMIT
Figure
Adaptive Attenuation Reduction
long noise level less than threshold total attenuation reduced all. Once threshold exceeded, total attenuation decreased more more increasing ATR. sensitivity programmable parameter However, will exceed programmable limit LIMIT even noise level increases further. Table shows registers associated with adaptive attenuation reduction. Table Register SCATTN SCATTS SCATTL Adaptive Attenuation Reduction Registers Bits Name LIMIT Comment Noise Threshold Attenuation Sensitivity Limit
adaptive attenuation reduction influences attenuation provided GHR. Thus attenuation stages adaptive attenuation reduction influence attenuation never drop below
Preliminary Data Sheet
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Functional Units 2.1.5.4 Loudspeaker Gain Adaptation
noisy environments useful automatically increase signal level loudspeaker output with increasing noise level. features such automatic gain adaptation adding additional gain module LGAR described section 2.1.3.7. Figure illustrates additional gain provided
LIMIT
Figure
Loudspeaker Gain Adaptation
long noise level less than threshold there additional gain. Once threshold exceeded, gain increased with programmable sensitivity However, will exceed programmable limit LIMIT even noise level increases further. Table shows registers associated with loudspeaker gain adaptation. Table Register SCLSPN SCLSPS SCLSPL Loudspeaker Gain Adaptation Registers Bits Name LIMIT Comment Noise Threshold Gain Sensitivity Limit
Note: total attenuation programmed speakerphone register SATT1:ATT automatically increased when loudspeaker gain adaptation increases. Therefore, adaptive attenuation reduction (chapter 2.1.5.3) should reduced accordingly.
Preliminary Data Sheet
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Line Echo Cancellation Unit
Functional Units
contains adaptive line echo cancellation unit cancellation near echoes. unit three modes: modes normal mode superior mode consider echo length. superior mode, shadow filter used additionally normal mode order improve echo cancellation quality. third mode extended mode. works basically like superior mode considers line echoes echo length. line echo cancellation unit especially useful front various detectors (DTMF, CPT, etc.). block diagram shown figure
Filter Adaptive Figure
Line Echo Cancellation Unit Block Diagram
Input usually connected line input while input connected outgoing signal. normal mode adaptation process controlled three parameters MIN, MGN. Adaptation takes place only both following conditions hold: With first condition, adaptation weak signals avoided. second condition avoids adaptation during double talk. parameter represents echo loss provided external circuitry. adaptation stops power received signal (I2) exceeds power expected signal (I1-ATT) more than margin MGN.
Preliminary Data Sheet
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Functional Units
Shadow Filter
copy coeff. adapt coeff.
Filter
Figure
Line Echo Cancellation Unit Superior Mode with Shadow
basic idea superior mode shown figure shadow filter left hand side gets coefficients adapted similarly adaptive filter Line Echo Canceller normal mode. cancelling line echo, however, filter right hand side used. When quality this filter excelled quality shadow filter, coefficients shadow filter copied right hand side. More formally, coefficients shadow filter adapted (see unit "adapt coeff" figure similar normal mode, following conditions hold: this case, already difference between external echo loss margin (ATTsuperior ATTnormal MGNnormal) that condition actually same normal mode. parameter should adjusted accordingly. Note that negative. coefficients copied from shadow filter actually used filter (see unit "copy coeff." figure currently adaptation shadow filter progress least following conditions holds:. ATTS ATTA attenuation shadow filter ATTS better than attenuation actually used filter ATTA margin MGN. Note that superior mode, parameter different meaning than normal mode ATTS ATTS last time condition been valid current attenuation ATTS shadow better than time since last update according condition
Preliminary Data Sheet
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Functional Units extended mode works like superior mode considers line echoes echo length. Since computational effort increases with increasing length, parameter offers trade-off between adaptation speed computational costs. With set, shadow parameters adapted every thus adaptation speed superior mode. With cleared, half shadow parameters updated every such that half parameters other half updated alternately. indicated table computational costs decrease does adaptation speed line echo canceller. Table shows registers associated with line echo canceller.
Table Register LECCTL LECCTL
Line Echo Cancellation Unit Registers Bits Name Comment Line echo canceller enable Normal mode Superior mode Extended mode reserved Adaptation stop Adaptation speed Input signal selection Input signal selection Minimal power signal Margin Relevant Mode
LECCTL LECCTL LECCTL LECCTL LECLEV LECATT
extended
Externally provided attenuation
LECMGN
adaptation coefficients stopped setting register LECCTL. This holds three modes Line Echo Canceller. Furthermore superior extended mode, also copying coefficients from shadow disabled.
DTMF Detector
contains DTMF detector that recognizes sixteen standard DTMF tones. Figure shows block diagram DTMF detector. results detector available status dedicated result register. These registers read external controller serial control interface (SCI).
Preliminary Data Sheet
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Functional Units
DTMF Detector
Figure
DTMF Detector Block Diagram
Table show associated registers. Table DDCTL DDCTL DTMF Detector Control Register Name Comment DTMF detector enable Input signal selection
Register Bits
soon valid DTMF tone recognized, status word DTMF tone code updated (table 23). Table DTMF Detector Results Name Comment DTMF code valid DTMF tone code
Register Bits STATUS DDCTL
when DTMF tone currently recognized cleared when DTMF tone recognized detector disabled. code DTMF tone provided register DDCTL. valid when until next incoming DTMF tone. registers DDTW DDLEV contain parameters detection (table 24). Table Register DDTW DDLEV DTMF Detector Parameters Bits Name TWIST Comment Twist DTMF recognition Minimum signal level detect DTMF tones
Call Progress Tone Detector
selected signal monitored continuously call progress tone. detector consists band-pass optional timing checker (figure 34).
Preliminary Data Sheet
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Functional Units
Band-pass
300-640 (Status)
Timing Checker
Figure
Call Progress Tone Detector Block Diagram
detector used modes: cooked. mode, occurrence signal within frequency, time energy limits directly reported. timing checker bypassed therefore does interpret length interval signal. cooked mode, number duration signal bursts interpreted timing checker. signal burst followed called cycle. Cooked mode requires minimum cycles. flag with first burst after programmed number cycles been detected. flag remains until unit disabled speech detected, even conditions anymore. this mode modelled sequence identical bursts separated gaps with identical length. programmed accept range both burst gap. also possible specify maximum aberration consecutive bursts gaps. Figure shows parameters single cycle (burst gap).
tPmax tPmin
tGmin tGmax
Figure
Call Progress Tone Detector- Cooked Mode
status defined follows:
Preliminary Data Sheet
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Functional Units Table Call Progress Tone Detector Results Name Comment tone currently detected [340
Register Bits STATUS
affected reading status word. automatically reset when unit disabled. Table shows control register detector. Table Register CPTCTL CPTCTL CPTCTL CPTMN CPTMN CPTMX CPTMX CPTDT CPTDT CPTTR CPTTR CPTTR Call Progress Tone Detector Registers Bits Name MINB MING MAXB MAXG DIFB DIFG Comment Unit enable Mode (cooked, raw) Input signal selection Minimum time signal burst (tPmin) Minimum time signal (tGmin) Maximum time signal burst (tPmax) Maximum time signal (tGmax Maximum difference between consecutive bursts Maximum difference between consecutive gaps Number cycles (cooked mode), (raw mode) Minimum signal level detect tones Minimal signal-to-noise ratio
condition violated during sequence cycles timing checker reset restarts with next valid burst. Note: cooked mode with first burst after programmed number cycles been detected. CPTTR:NUM then with third signal burst. Note: number cycles must zero mode.
Alert Tone Detector
alert tone detector detect standard alert tones (2130 2750 caller protocols. results detector available status register register ATDCTL0. These registers read external controller serial control interface (SCI).
Preliminary Data Sheet 10.99
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Functional Units
Alert Tone
Detector
Figure Table Register ATDCTL0 ATDCTL0 ATDCTL1 ATDCTL1 ATDCTL1 ATDCTL1
Alert Tone Detector Block Diagram Alert Tone Detector Registers Bits Name Comment Alert Tone Detector Enable Input signal selection Detection dual tones single tones hook mode Maximum deviation (0.5% 1.1%) Minimum signal level detect alert tones
soon valid alert tone recognized, status word code detected combination alert tones updated (table 28). With Hook mode selected, alert tone detected faster. Hook mode assumes that there speech signal present. Table Register STATUS ATDCTL0 Alert Tone Detector Results Bits Name Comment Alert tone detected Alert tone code
2.5.1
Universal Tone Detector
universal tone detector used instead detector detect special tones which covered standard band-pass. Figure shows functional block diagram.
Preliminary Data Sheet
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Functional Units
Programmable Band-pass
Limit Evaluation Logic Limit
Figure
Universal Tone Detector Block Diagram
Initially, input signal filtered programmable band-pass (center frequency band width BW). Both in-band signal (upper path) out-of-band signal determined (lower path) absolute value calculated. Both signals furthermore filtered limiter low-pass. signal samples (absolute values) below programmable limit zero other signal samples diminished LIM. purpose limiter increase noise robustness. After limiter stages both signals filtered fixed pass. evaluation logic block determines when when reset status STATUS:UTD. status will both following conditions hold least time TTONE without breaks exceeding time TB1: in-band signal exceeds programmable level difference in-band out-of-band signal exceeds DELTA status will reset least these conditions violated least time TGAP without breaks exceeding TB2. times help reduce effects sporadic dropouts. Example: TTONE conditions 30ms, then violated then again this case break ignored, because does exceed allowed break time TB1. Therefore status will after Table summarizes associated registers.
Preliminary Data Sheet
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Functional Units Table Register UTDCTL UTDCTL UTDBW UTDCF UTDLIM UTDLEV UTDDLT UTDTMT UTDTMT UTDTMG UTDTMG Universal Tone Detector Registers Bits Name DELTA TTONE TGAP Comment detector enable Input signal selection Bandwidth band-pass Center frequency band-pass Limiter level Minimum signal level (in-band) Minimum difference (in-band, out-of-band) Minimum time status Maximum break time TTONE Minimum time reset status Maximum break time TGAP
result available status register (table30). Table Register STATUS Universal Tone Detector Results Bits Name Comment Tone detected
Note: same position bit. Therefore detector programmable band-pass must same time.
Caller Decoder
caller decoder basically 1200 baud modem (FSK, demodulation only). stream formatted subsequent UART data available data register along with status information (figure 38).
demod.
(Bellcore, V.23)
UART
(Status, Data)
Figure
Caller Decoder Block Diagram
Preliminary Data Sheet
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Functional Units demodulator supports modes according table appropriate mode detected automatically. Table Mode Caller Decoder Modes Mark (Hz) 1200 1300 Space (Hz) 2200 2100 Comment Bellcore V.23
decoder does interpret data received. Each byte received placed into CIDCTL register (table 33). status byte updated (table 32). Table Caller Decoder Status Name Comment byte received Carrier Detected
Register Bits STATUS STATUS
cleared when unit disabled. addition, cleared when CIDCTL0 read. Table Register CIDCTL0 CIDCTL0 CIDCTL0 CIDCTL0 CIDCTL0 CIDCTL1 CIDCTL1 CIDCTL1 Caller Decoder Registers Bits Name DATA NMSS Comment Unit enable Drop tolerance during mark seizure sequence Compatibility mode Input signal selection Last data byte received Number mark/space sequences necessary successful detection carrier. Number mark bits necessary before space first byte after carrier detected. Minimum signal level detection.
When unit enabled, waits programmable number continuous mark bits (CIDCTL1:NMB). These mark bits optionally preceded channel seizure signal consisting series alternating space mark signals. such channel
Preliminary Data Sheet
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Functional Units seizure sequence present must consist least CIDCTL1:NMSS alternating mark space bits. Once programmed number continuous mark bits been received sets carrier detect STATUS:CD. interpretation data, including message type, length checksum completely left controller. unit should disabled soon complete information been received cannot detect transmission itself. There alternative Caller Decoders. With cleared, standard Caller Decoder selected, which compatible 2170 version 1.1. standard Called Decoder requires seizure sequence. With improved Caller Decoder selected, which provides higher twist tolerance, does require seizure sequence, allows select drop tolerance. drop tolerance selected register CIDCTL0. Then, drop outs during mark sequence necessarily cause that detection looses carrier sequence, received mark sequence recognized although there drop outs. same holds seizure sequence. This behavior meets Bellcore test specification. drop tolerance enabled, registers CIDMF1 CIDMF6 have programmed prior this feature. Note that these registers undefined after reset. registers CIDMF1 CIDMF6 must contain possible message formats, which transmitted after mark sequence, these registers must contain other value. Bellcore example, valid message formats 06h, that registers CIDMF1 CIDMF6 contain 04h, 06h, 80h, 82h, 82h. Note: Some caller mechanism require additional external components decoupling. These tasks must handled controller. Note: controller responsible selecting storing parts needed.
DTMF Generator
DTMF generator generate single dual tones with programmable frequency gain. This unit primarily used generate common DTMF tones also used signalling other user defined tones. block diagram shown figure
Preliminary Data Sheet
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Functional Units
generator
ampl1
att1
generator
ampl2
att2
Figure
DTMF Generator Block Diagram
Both generators amplifiers identical. There modes programming generators, cooked mode mode. cooked mode, DTMF tones generated programming single code. mode, frequency each generator/ amplifier programmed individually separate register. unit outputs which provide same signal with individually programmable attenuation. Table shows parameters this unit. Table DGCTL DGCTL DGCTL DGF1 DGF2 DGATT DGATT DTMF Generator Registers Name FRQ1 FRQ2 LEV1 LEV2 ATT1 ATT2 Comment Enable generators Mode (cooked/raw) DTMF code (cooked mode) Frequency generator Frequency generator Level amplifier generator Level amplifier generator Attenuation Attenuation
Register Bits
Note: DGF1 DGF2 undefined when cooked mode used must written.
Analog Interface
There identical interfaces analog side (i.e., analog fronend described chapter 4.3) shown figure These interfaces must connected double codec like 4851.
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Functional Units
Channel
line
Channel
loudspeaker
line
microphone
Figure
Analog Frontend Interface Block Diagram
each signal amplifier provided level adjustment. ingoing signals passed through optional high-pass (HP) part. Furthermore, three signals mixed order generate outgoing signals (S2,S4). Table shows associated registers. Table IFG1 IFG2 IFS1 IFS1 IFS1 IFS1 IFG3 IFG4 IFS2 IFS2 IFS2 IFS2 Analog Frontend Interface Registers Name Comment Gain Gain High-pass Input signal Input signal Input signal Gain Gain High-pass Input signal Input signal Input signal
Register Bits
Digital Interface
There almost identical interfaces digital side (i.e., SSDI/IOM®-2 interface described chapters 4.2) shown figure only difference between these interfaces that only channel supports SSDI mode.
Preliminary Data Sheet 10.99
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Functional Units
Channel (SSDI/IOM®-2 Interface)
ATT1
Channel (IOM®-2 Interface)
S8/S24
ATT2/3
S7/S23
Figure
Digital Interface Block Diagram
Each outgoing signal signals with attenuation signal with programmable attenuation (ATT). attenuator used artificial echo loss. Each input passed through optional high-pass (HP) part. Channel IOM®-2 split into consecutive channels with independent data streams (A-law µ-law). therefore possible either linear channels, channel channel, channel channels three channels. associated registers shown table Table IFS3 IFS3 IFS3 IFS3 IFS4 IFS4 IFS4 IFS4 IFS4 IFS4 Digital Interface Registers Name Comment Input signal Input signal Input signal High-pass Input signal Input signal Input signal High-pass Input signal Input signal
Register Bits
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Functional Units Table IFS4 IFS4 IFG5 IFG5 IFG5 Digital Interface Registers Name ATT1 ATT2 ATT3 Comment Input signal High-pass Attenuation input signal (Channel Attenuation input signal (Channel Attenuation input signal (Channel
Register Bits
2.10
Universal Attenuator
contains universal attenuator that connected signal (e.g. sidetone gain ISDN applications).
Figure
Universal Attenuator Block Diagram
Table shows associated register. Table Universal Attenuator Registers Name Comment Attenuation Input signal
Register Bits
2.11
Automatic Gain Control Unit
addition universal attenuator with programmable fixed gain contains amplifier with automatic gain control (AGC). preceded signal summation point input signals. input signals attenuated.
Preliminary Data Sheet
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Functional Units
Figure
Automatic Gain Control Unit Block Diagram
operation similar AGCX (ACCR) speakerphone. differences follows: NOIS parameter Separate enable/disable control Slightly different coefficient format Furthermore contains comparator that starts stops gain regulation. signal after summation point (S17) filtered peak detector with time constant decay. Then signal compared programmable limit LIM. Regulation takes only place when filtered signal exceeds limit. Table shows associated registers. Table Automatic Gain Control Registers Name AG_INIT SPEEDL SPEEDH AG_ATT AG_GAIN Comment Enable Input signal Input signal Attenuation Initial gain/attenuation Compare level rel. max. PCM-value Change rate lower levels Change rate higher level Attenuation range Gain range Time constant decay rate peak detector Comparator minimal signal level pass time constant
Register Bits AGCCTL AGCCTL AGCCTL AGCATT AGC1 AGC1 AGC2 AGC2 AGC3 AGC3 AGC4 AGC4 AGC5
Preliminary Data Sheet
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Functional Units
2.12
Noise Reduction Unit
Additionally noise reduction block built speakerphone, another noise reduction block available configurable module. useful reducing noise coming receive path from line side.
Noise Reduction
Figure
Noise Reduction Block Diagram
noise reduction unit attenuates frequencies with great ratio noise energy level level speach signal. maximal attenuation noise reduction unit programmed parameter NRATT. There some restrictions simultaneous selection speakerphone. Different trade-offs selected with parameter Table Register NRCTL NRCTL NRCTL NRATT Noise Reduction Registers Bits Name NRATT Comment Noise Reduction Unit Enable Select restriction speakerphone Input signal selection Maximal attenuation noise reduction unit.
2.13
Equalizer
contains identical equalizers which programmed individually. Each equalizer inserted into signal path. main application equalizer correction frequency characteristics microphone, transducer loudspeaker. Each equalizer consists filter followed filter shown figure
Preliminary Data Sheet
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Functional Units
S18/S19
Figure
Equalizer Block Diagram
coefficients A1-A9, B2-B9 belong filter, coefficients D1-D17 belong filter. Table shows registers associated with first equalizer (S18). second equalizer (S19) programmed registers FCFCTL2 FCFCOF2, respectively Table Register FCFCTL1 FCFCTL1 FCFCTL1 Equalizer Registers Bits Name Comment Enable Input signal equalizer Filter coefficient address Filter coefficient data
FCFCOF1
multitude coefficients 2170 uses indirect addressing scheme reading writing individual coefficient. address coefficient given actual value read written register FCFCOF1.
Preliminary Data Sheet
10.99
2170
Functional Units order ease programming automatically increments address after each access FCFCOF1. Note: access out-of-range address automatically resets FCFCTL1:ADR.
2.14
Tone Generator
contains universal tone generator which used tone alerting, call progress tones other audible feedback tones. Figure shows block diagram this unit.
Control Generator TON, TOFF
Sine/Square Wave Beat Generator Generators Gain
Automatic Stop
Figure
Tone Generator Block Diagram
heart this unit four independent sine/square wave generators that generate individually programmable frequencies (F1, F4). Each generator associated amplifier (G1, G4). dynamic behavior tone generator controlled beat generator. beat generator enabled, then output either three tone cadence tone caddence shown figure
Preliminary Data Sheet
10.99
2170
Functional Units
three tone cadence
tone cadence
Figure
Tone Generator Tone Sequences
duration each frequency defined each timeslot either associated frequency generated frequency pair (table 41). Table Timeslot Tone Generator Modes Option Option F1+F4 F2+F4 F3+F4
beat generator disabled, then output continuous signal either F1+F4, F2+F4 silence. control generator used enable beat generator (during TON) disable during TOFF. With automatic stop feature, cadence generation beat generator stops immediately after cadence (either T3). This avoids unpleasant sounds when stopping tone generator unit. Table shows registers associated with tone ringing generator. Table Tone Generator Registers Name Comment Status (Tone Generator on/off) Control generator mode Dual tone enable on/off) Beat generator mode (F1, F1/F2 F1/F2/F3) Stop mode (immediate automatic) Waveform (sine square)
Register Bits STATUS TGCTL TGCTL TGCTL TGCTL TGCTL
Preliminary Data Sheet
10.99
2170
Functional Units Table TGTON TGT1 TGT2 TGT3 TGF1 TGF2 TGF3 TGF4 TGG1 TGG2 TGG3 TGG4 TGGO1 TGGO2 Tone Generator Registers Name Comment TOFF
Register Bits TGTOFF
This unit outputs (S20 S21). signal level these outputs programmed individually preceding gain stages (GO1 GO2).
2.15
Peak Detector
peak detector (figure provides easy means verify minimum maximum signal level signal within however, usually used normal operation. peak detector stores either maximum minimum signal value observed signal register PDDATA since last read access this register. Therefore only possible determine absolute level signal also checked whether offset present. This done first scanning maximum then minimum value. minimum value (approximately) negated maximum value then offset present. peak detector should disabled needed.
Preliminary Data Sheet
10.99
2170
Functional Units
Peak
Detector
Figure
Peak Detector Block Diagram
register PDDATA gives maximum minimum integer depending mode selected example assumed that detection maximum selected. Then with enabling detector with each read access register PDDATA, PDDATA smallest possible value, which negative maximum integer. With each maximum detected signal this maximum provided PDDATA. Table Register PDCTL PDCTL PDCTL PDDATA Peak Detector Registers Bits Name Comment Peak Detector Enable Minimum/Maximum selection Input signal selection Min/Max signal value since last read access
Preliminary Data Sheet
10.99
2170
Miscellaneous
Miscellaneous Miscellaneous
Miscellaneous
Reset Power Down Mode
2170 either reset mode, power down mode active mode. During reset 2170 clears hardware configuration registers stops both internal external activity. With first access read/write register 2170 enters active mode. this mode main oscillator running normal operation takes place. 2170 brought power down mode setting power down (PD). Table CCTL Power Down Name Comment power down mode
Register Bits
power down mode main oscillator stopped. 2170 enters active mode again upon access read/write register. Figure shows state chart modes 2170.
Reset Mode reg. access RST=1 RST=1
CCTRL.PD=1 Active Mode reg. access Power Down Mode
Figure
Operation Modes State Chart
Control Register
outputs (SPS0, SPS1) used either general purpose outputs, speakerphone status outputs status register outputs. This programmed with bits MODE. Table shows associated register.
Preliminary Data Sheet
10.99
2170
Miscellaneous Table SPSCTL SPSCTL SPSCTL SPSCTL Register MODE Output Value SPS0 Output Value SPS1 Mode Operation Position status register window
When used status register outputs, status register position appears SPS0 position POS+1 appears SPS1. This mode operation used debugging purposes direct polling status register bits. cannot observed SP1.
Interrupt
generate interrupt inform host update STATUS register according table interrupt mask register (INTM) used disable enable interrupting capability each STATUS register individually. Table STATUS (old) RDY=0 CIA=0 CD=0 CD=1 TG=1 DTV=0 DTV=1 ATV=0 ATV=1 Interrupt Source Summary STATUS (new) RDY=1 CIA=1 CD=1 CD=0 TG=0 DTV=1 DTV=0 ATV=1 ATV=0 Command completed Caller byte available Carrier detected Carrier lost EN=0 Tone generator active DTMF tone detected DTMF tone lost EN=0 Alert tone detected Alert tone lost EN=0 Reset Command issued CIDCTL0 read EN=01) Carrier lost EN=0 Carrier detected Tone sequence finished EN=0 DTMF tone lost EN=0 DTMF tone detected Alert tone lost EN=0 Alert tone detected lost detected Write Register
CPT/UTD=0 CPT/UTD=1 detected CPT/UTD=1 CPT/UTD=0 lost PPI=0 ABT=0
PPI=1 ABT=1
Event input detected Register DHOLD read Exception (non-maskable)
EN=0 denotes unit disable
Preliminary Data Sheet
10.99
2170
Miscellaneous interrupt internally generated combination these events occurs interrupt masked. interrupts issued immedeately after status register update. status register update event CIA, DTV, ATV, APT, UTD, performed immediately after event occurs that causes set. event clear DTV, ATV, UTD, status register update performed with next update bit, i.e., after event occurs that causes set. event clear status register update performed after update latest. This internal interrupt cleared only when host executes Data Read Access with Interrupt Acknowledge command. this case, internal interrupt cleared when first STATUS register output. event occurs while host reads status register, status register updated after current access terminated interrupt internally generated immediately after access ended.
Abort
detects corrupted configuration (e.g. transient loss power) stops operation initializes read/write registers their reset state. discards commands with exception write command revision register while set. Only after write command revision register (with value) reset reinitialization take place.
Revision Register
contains revision register. This register read only does influence operation way. write revision register clears STATUS register does alter content revision register.
Hardware Configuration
adapted various external hardware configurations special registers: HWCONFIG0 HWCONFIG1. These registers written once during initialization must changed while active mode.
3.6.1
Frame Synchronization
locks itself either externally supplied frame sync signal generates frame sync signal itself. This internal reference frame sync signal called master frame sync (MFSC). Table shows AFECLK MFSC derived bits contained hardware configuration registers. controls whether frame sync taken from external generated internally. enables clock tracking explained sequel section.
Preliminary Data Sheet
10.99
2170
Miscellaneous Table Frame Synchronization Selection AFECLK XTAL XTAL MFSC AFEFSC Application Analog featurephone ISDN stand-alone DECT
3.6.2
Clock Tracking
adjust AFECLK AFEFSC dynamically slightly varying AFECLK AFEFSC derived from main oscillator (XTAL). This mode requires that both AFEFSC nominally running same frequency kHz). enabled with hardware configuration registers. This feature especially useful when signal derived from same clock source AFECLK (ISDN application).
3.6.3
Clock Source
also derive AFECLK from externally provided clock CLK. This enabled with hardware configuration registers. external clock expected 13.824 MHz.
3.6.4
Used Clock Frame Sync Gereration
used clock frame sync required, generate such clock frame sync interface. this feature, must disabled HWCONF3 register (bits CM0) used configuration.
Restrictions Mutual Dependencies Modules
There some restrictions concerning modules that enabled same time (table 48). checked cell indicates that modules (defined column cell) must enabled same time.
Preliminary Data Sheet
10.99
2170
Miscellaneous Table Dependencies Modules
Fullband mode taps) Fullband mode taps)
Universal Tone Detector
Subband (normal) Subband (ISDN) Subband (enhanced) Subband (reduced) taps) taps) Comfort Noise Noise Adaptation DTMF Detector Caller (standard) Caller (improved) Alert Tone Detector Detector Detector Line Echo Canceller Equalizer 1/2, DTMF/Tone Generator
Modules enabled same time. However, deactivation requires proper sequence: First echo cancellation unit must disabled, then DTMF detector.
Some incompatible modules share same internal memory space. this example case incompatible modules both modules going used different times, then following scenario appears: Module programmed prior use. After while, disabled, module programed module enabled. later time, module disabled. Before module enabled,
Preliminary Data Sheet 10.99
Equalizer, DTMF, Tone
Subband (enhanced)
Caller (improved)
Line Echo Canceller
Caller (standard)
Alert Tone Detector
Subband (reduced)
Fullband mode
Subband (normal)
Noise Adaptation
Subband (ISDN)
DTMF Detector
Comfort Noise
Detector
2170
Miscellaneous parameters module must reprogrammed. This reprograming necessary combination listed table Table Reprogram parameters parameter these must reprogrammed
After this
fullband mode DTMF decoder, caller decoder, alert tone detector, which number taps detector, universal tone detector line echo canceller subband mode "ISDN" subband mode "Enhanced" Comfort noise Free noise reduction module with NRCTL:MD=10 detector DTMF detector DTMF decoder, caller decoder, alert tone detector, detector, universal tone detector line echo canceller DTMF decoder, caller decoder, alert tone detector, detector, universal tone detector, line echo canceller, equalizers, tone detectors tone generator DTMF decoder, caller decoder, alert tone detector, detector, universal tone detector line echo canceller DTMF decoder, caller decoder, alert tone detector, detector, universal tone detector line echo canceller Universal tone detector Registers CIDMF1 CIDMF6 decoder (improved)
fullband mode echo cancellation unit, detailed list maximal length under certain restriction found chapter 2.1.1.1. freely configurable noise reduction unit (chapter 2.12) some restrictions stated table detailed description restrictions provided with register description register NRCTL. further restriction occur because resource costs simultaneously applied modules. Each module currently takes some resources. percentage module needs from totally available resources listed table resources applied modules must never exceed 100. amounts listed table valid 34.560 operating frequency. 2170 runs higher lower frequency, resource costs decrease increase accordingly. Thus, necessary restrict length filter echo cancellation unit several other units operating same time.
Preliminary Data Sheet
10.99
2170
Miscellaneous Table Module Detector Caller Decoder Alert Tone Detector DTMF Detector Detector DTMF Generator Equalizer Speakerphone AGCX AGCR Acoustic Echo Cancellation Fullband mode Acoustic Echo Cancellation Fullband mode Acoustic Echo Cancellation Fullband mode Noise Reduction Acoustic Echo Cancellation Subband mode (incl. Noise Reduction Module Noise Controlled Adaption Comfort Noise Line Echo Cancellation Universal Attenuator Digital Interface Analog Interface Clock Tracking Miscellaneous Module Weights Weight 5.03 3.73 9.75 2.45 3.15 6.05 3.24 1.92 2.50 10.93 1.92 1.94 32.25 41.90 51.55 taps taps taps 61.20 70.86 taps taps length. 40.03 42.99 45.96 taps taps taps 48.92 51.88 taps taps length. Adaption window: taps 25.22 5.03 32.19 33.88 35.17 Mode: reduced normal 37.93 39.24 ISDN enhanced 7.70 5.07 7.45 11.50 13.02 21.60 17.04 0.16 1.46 1.46 3.03 2.11 0.53 7.70 always active channel SSDI channel channel normal mode superior mode extended mode, length: taps. Adaption window: taps hook hook Comment
Preliminary Data Sheet
10.99
2170
Miscellaneous
Preliminary Data Sheet
10.99
2170
Interfaces
Interfaces Interfaces
Interfaces
This section describes interfaces supports both IOM®-2 interface with single double clock mode strobed serial data interface (SSDI). However, these interfaces cannot used simultaneously they share some pins. Both interfaces data transfer only cannot used programming slave frame synchronization well data clock inputs. Table lists features alternative interfaces. Table Signals Channels (bidirectional) Code SSDI IOM®-2 Interface IOM®-2 linear bit), A-law, µ-law bit) linear bit) signal (DXST, DRST) SSDI
Synchronization within frame timeslot (programmable)
IOM®-2 Interface
data stream partitioned into packets called frames. Each frame divided into fixed number timeslots. Each timeslot used transfer bits. Figure shows commonly used terminal mode (three channels ch0, with four timeslots each). first timeslot figure denoted number second (B2)
DD/DU
Figure
IOM®-2 Interface Frame Structure
signal used indicate start frame. Figure shows example valid FSC-signals (FSC, which both indicate same clock cycle first clock cycle frame (T1).
Preliminary Data Sheet 10.99
2170
Interfaces
FSC*
Figure
SSDI/IOM®-2 Interface Frame Start
supports both single clock mode double clock mode. single clock mode, rate equal clock rate. Bits shifted with rising edge sampled falling edge. double clock mode, clock runs twice rate. Therefore each there clock cycles. Bits shifted with rising edge first clock cycle sampled with falling edge second clock cycle. Figure shows timing single clock mode figure shows timing double clock mode.
DU/DX
DD/DR
Figure
IOM®-2 Interface Single Clock Mode
Preliminary Data Sheet
10.99
2170
Interfaces
DU/DX
DD/DR
Figure
IOM®-2 Interface Double Clock Mode
supports three channels simultaneously data transfer. only channels used, then both coding (PCM A-law, µ-law linear) data direction (DD/DU assignment transmit/receive) programmed individually. 2170 supports third channel simply splitting second channel into channels.Therefore following restrictions occur channel this case: Channel well three must coding (both either A-law µ-law) Channel three even timeslot Channel following timeslot enabled channel splitting, SDCHN2:CS must SDCHN2:PCM cleared. selection SDCHN2:PCD holds then both channels. Table shows registers used configuration IOM®-2 interface. Table SDCONF SDCONF SDCONF SDCHN1 SDCHN1 SDCHN1 SDCHN1 SDCHN1 SDCHN2 SDCHN2 SDCHN2 SDCHN2 IOM®-2 Interface Registers Name Comment Interface enable Selection clock mode (double/single clock) Number timeslots within frame Channel enable First timeslot (channel Data Direction (channel code linear (channel code (A-law µ-law, channel Channel enable Channel split (into contiguous channels) First timeslot (channel Data Direction (channel
Register Bits
Preliminary Data Sheet
10.99
2170
Interfaces Table SDCHN2 SDCHN2 IOM®-2 Interface Registers Name Comment code linear (channel code (A-law µ-law, channel
Register Bits
A-law µ-law mode, only bits transferred therefore only timeslot needed channel. linear mode, bits needed single channel. this mode, consecutive timeslots used data transfer. Bits transferred within first timeslot bits transferred within next timeslot. first timeslot must have even number. Figure shows example single channel linear mode occupying timeslots Each frame consists timeslots single clock mode used.
DD/DU
Figure
IOM®-2 Interface Channel Structure
this rate data shifted with rising edge clock sampled falling edge. data clock runs (six timeslots with each within µs).
Preliminary Data Sheet
10.99
2170
Interfaces
SSDI Interface
Interfaces
SSDI interface intended seamless connection low-cost burst mode controllers (e.g. 27251) supports single channel each direction. data stream partitioned into frames. Within each frame value sent received 2170. start frame indicated rising edge FSC. Data always latched falling edge output rising edge DCL. SSDI transmitter receiver operating independently each other except that both same signal.
4.2.1
SSDI Interface Transmitter
2170 indicates outgoing data signal activating DXST clocks. signal DXST activated with same rising edge that used send first (Bit data. DXST deactivated with first rising edge after last been transferred. 2170 drives signal only when DXST activated. Figure shows timing transmitter.
DXST
DU/DX
Figure
SSDI Interface Transmitter Timing
4.2.2
SSDI Interface Receiver
Valid data indicated active DRST pulse. Each DRST pulse must last exactly clocks. there more than DRST puls within single frame 2170 programmed with parameter listen n-th pulse with ranging from order detect first pulse properly, DRST must active rising edge FSC. figure 2170 listening third DRST pulse (n=3).
Preliminary Data Sheet
10.99
2170
Interfaces
DRST active pulse (n=3)
Figure
SSDI Interface Active Pulse Selection
Figure shows timing SSDI receiver.
DRST
DD/DR
Figure
SSDI Interface Receiver Timing
Table shows registers used configuration SSDI interface. Table SDCHN1 SSDI Interface Register Name Comment Number active DRST strobe
Register Bits
Preliminary Data Sheet
10.99
2170
Interfaces
Analog Front Interface
Interfaces
uses four wire interface similar IOM®-2 interface exchange information with analog front (PSB 4851). main difference that timeslots channel assignments fixed shown figure master this interface provides AFEFS well AFECLK.
AFEFS AFEDD AFEDU
Channel
Channel
Channel
unused
Figure
Analog Front Interface Frame Structure
Voice data transferred linear coding bidirectional channels auxiliary channel used transfer current setting loudspeaker amplifier remaining bits fixed zero. other direction transfers override value from 4851. additional override determines currently transmitted value should override AOAR:LSC1) setting. AOAR:LSC setting affected C3:ALS override. Table shows source control gain amplifier. Table AOPR:OVRE Control Amplifier C3:OV Gain amplifier AOAR:LSC AOAR:LSC C3:ALS
Furthermore interface enabled disabled according table Table Register AFECTL
Analog Front Interface Register Bits Name Comment Interface enable
specification 4851
Preliminary Data Sheet
10.99
2170
Interfaces
AFECLK
AFEFS
Figure
Analog Front Interface Frame Start
Figure shows synchronization frame AFEFS. first clock frame (T1) indicated AFEFS switching from high before falling edge AFEFS remain high during subsequent cycles T32. Please also chapter 3.6.2 additional information frame synchronization.
AFECLK
AFEDU
AFEDD
Figure
Analog Front Interface Data Transfer
data shifted with rising edge AFECLK sampled falling edge AFECLK (figure 60). AOPR:OVRE set, channel used 4851. values C3:ALS) transferred first. data clock (AFECLK) rate fixed 6.912 MHz. Table shows clock cycles used three channels. Table Clock Cycles T1-T16 T17-T32 T33-T40 T41-T864 Analog Front Interface Clock Cycles AFEDD (driven data data data AFEDU (driven 4851) data data data tristate
Preliminary Data Sheet
10.99
2170
Interfaces
Serial Control Interface
Interfaces
serial control interface (SCI) uses four lines: SDR, SDX, SCLK Data transferred lines rate given SCLK. falling edge indicates beginning access. Data sampled rising edge SCLK shifted falling edge SCLK. Each access must terminated rising edge accesses divided into four classes: Configuration Read/Write Register Read/Write Status/Data Read Status/Data Read with Interrupt Acknowledge power down mode, read access status register does deliver valid data with exception (RDY=0). After status been read access either terminated extended read data from register read/write access only performed when ready. status register provides this information. access starts with transfer bits over line SDR. This first word specifies access class, access type (read write) and, necessary, register accessed. access types terminate after first word: configuration register write register read. configuration register written, first word also includes data access terminated. After access register read, access type data read necessary obtain register data. However, data valid only when STATUS:RDY=1. With second word, accesses beside configuration register write register read deliver status register from line SDX. After second word, access status register read terminates while other accesses transfer data with third word terminate then. Figures show timing diagrams different access classes types
Preliminary Data Sheet
10.99
2170
Interfaces
SCLK
c15,.,c0: s15,.,s0: ,.,d0:
command word configuration register read: status register data read:
Figure
Configuration Register Read Access
Configuration registers even adresses positions d7-d0 while configuration registers adresses positions d15-d8.
SCLK
c15,.,c0:
command word configuration register write: register read:
Figure
Configuration Register Write Access Register Read Command
Preliminary Data Sheet
10.99
2170
Interfaces
SCLK
c15,.,c0: s15,.,s0: command word status register read status register:
Figure
Status Register Read Access
SCLK
c15,.,c0: s15,.,s0: d15,.,d0:
command word data read: status register: data read:
Figure
Data Read Access
Preliminary Data Sheet
10.99
2170
Interfaces
SCLK
c15,.,c0: s15,.,s0: ,.,d0:
command word register write: status register: data written
Figure
Register Write Access
commands external signal deactivated long chip selected low). detailed discussion about behavior interrupt signal please Chapter 3.3. Table shows formats different command words. other command words reserved. Note that interrupts only acknowledged (cleared) command read status/data with interrupt acknowledge issued. Table Command Words Register Access
Read Status Register Data Read Access (interrupt acknowledge) Read Status Register Data Read Access1) Read Register1) Write Register Read Configuration Reg. Write Configuration Reg.
DATA
Does acknowledge interrupt.
case configuration register write, determines what configuration register written (table 58):
Preliminary Data Sheet
10.99
2170
Interfaces Table Address Field Configuration Register Write Register HWCONFIG HWCONFIG HWCONFIG HWCONFIG
case configuration register read, determines what pair configuration registers read (table 59): Table Address Field Configuration Register Read
Register pair HWCONFIG HWCONFIG HWCONFIG HWCONFIG
Note: Reading register except status register hardware configuration register requires least accesses. first access register read command (figure 62). With this access register address transferred After that access data read accesses (figure must executed. first data read access with STATUS:RDY=1 delivers value register.
Preliminary Data Sheet
10.99
2170
Interfaces
General Purpose Parallel Port
Interfaces
provides general purpose parallel port (GP0 GP15 general purpose parallel port modes: static mode multiplex mode. both modes, generate interrupt specific input pins specific signal edges. Each input masked individually. events that generated interrupt collected hold register. Table shows registers mode selection. Table Register HWCONFIG1 General Purpose Parallel Port Mode Registers Name Comment Mode selection (static/multiplex)
4.5.1
Static Mode
static mode pins general purpose parallel port interface have identical functionality. configured output input. Pins configured outputs provide static signal programmed controller. Pins configured inputs monitoring signal continuously without latching. controller always reads current value. Table shows registers used static mode. Table DOUT3 DDIR Static Mode Registers Output signals (for pins configured outputs) Input signals (for pins configured inputs) direction
Register bits Comment
4.5.2
Multiplex Mode
multiplex mode, multiplexes either four output registers three output register input GP0-GP11. this, GP12-GP15 used distinguish four timeslots. Each timeslot duration approximately timeslots separated approximately which none signals GP12-GP15 active. multiplexes three output registers GP0-GP11 timeslots timeslot direction pins programmed. input pins, signal latched with falling edge GP12 Table shows registers used multiplex mode. This mode useful scanning keys controlling seven segment displays.
Preliminary Data Sheet
10.99
2170
Interfaces Table DOUT0 DOUT1 DOUT2 DOUT3 DDIR Multiplex Mode Registers Output signals GP0-GP11 while GP15=1 Output signals GP0-GP11 while GP14=1 Output signals GP0-GP11 while GP13=1 Output signals (for pins configured outputs) while GP12=1 Input signals (for pins configured inputs) falling edge GP12 direction during GP12=1
Register bits Comment
Figure shows timing diagram multiplex mode.
MA15
MA14
MA13
MA12
MA0-MA
DOUT0
DOUT1
DOUT2
DIN/DOUT3
DOUT0
Figure
General Purpose Parallel Port Multiplex Mode
Note: either mode voltage (GP0 GP15) must exceed VDD.
4.5.3
Interrupt Generation
each configured input, compares current value previous value. static mode, previous value value (static mode). multiplex mode, previous value value sampled during previous input timeslot. both modes, exact sampling point cannot defined. reliable detection specific value, therefore necessary that value must stable least (static mode) (multiplex mode).
Preliminary Data Sheet
10.99
2170
Interfaces each input programmed detect following changes individually (table 63). Table DMASK1 Interrupt Mask Definition Parallel Port DMASK2 Prev. Value Cur. Value Remark disabled rising edge falling edge both edges
Whenever input meets specified condition then sets corresponding within register DHOLD also STATUS register. Therefore register DHOLD collects input pins that have programmed condition while STATUS register collects events pin. change STATUS:PPI also trigger external interrupt depending mask register INTM. STATUS:IPP reset when register DHOLD read controller. register DHOLD also cleared this time (i.e. when read). Note: edge detection stopped writing register DHOLD. Writing other value DHOLD starts edge detection according programmed masks. Edge detection must started after wake-up disabled default.
Preliminary Data Sheet
10.99
2170
Detailed Register Description
Detailed Register Description
single status register (read only) array data registers (read/write). purpose status register inform external microcontroller important status changes provide handshake mechanism data register reading writing. generates interrupt, status register contains reason interrupt.
Status Register
Ready
Ready last command any) still progress. last command been executed.
Abort exception during operation exception caused abort operation currently progress. cleared writing revision register. other command accepted while set.
Caller Available data caller caller byte available
Carrier Detect carrier detected Carrier detected
Call Progress Tone Currently call progress tone detected pause detected (raw mode) Currently call progress tone detected
Universal Tone Detected Currently tone being detetced
Preliminary Data Sheet
10.99
2170
Detailed Register Description Currently tone being detected DTMF Tone Valid DTMF code available DTMF code available DDCTL Alert Tone Valid alert tone code available alert tone code available ATDCTL0 Tone Generator Status Tone Generator running Tone Generator running Parallel Port Interrupt unmasked change input ports parallel port least unmasked input changed parallel port
Hardware Configuration Registers
HWCONFIG Hardware Configuration Register
PPSDI PPINT
PPSDX
PPSDX Push/Pull open-drain characteristic push/pull characteristic PPINT Push/Pull open-drain characteristic push/pull characteristic PPSDI Push/Pull interface pins have open-drain characteristic pins have push/pull characteristic
Preliminary Data Sheet
10.99
2170
Detailed Register Description Clock Source AFECLK derived from main oscillator AFECLK derived from input Power Down (read only) active mode power down mode
Preliminary Data Sheet
10.99
2170
Detailed Register Description HWCONFIG Hardware Configuration Register
XTAL
SSDI
General Purpose Parallel Port
Description reserved static mode multiplex mode reserved
Clock Tracking AFECLK tracking disabled AFECLK tracking enabled
Master Frame Sync Selection AFEFSC
XTAL
XTAL Frequency
Factor reserved
Description 34.560 31.104 27.648 reserved
factor needed calculate clock frequency AFECLK.
SSDI
SSDI Interface Selection IOM®-2 Interface SSDI Interface
Preliminary Data Sheet
10.99
2170
Detailed Register Description HWCONFIG Hardware Configuration Register
ESDX ESDR
ESDX
Edge Select transmitted with rising edge transmitted with falling edge
ESDR
Edge Select latched with falling edge latched with rising edge
Preliminary Data Sheet
10.99
2170
Detailed Register Description HWCONFIG Hardware Configuration Register
Clock Master Clock generation AFECLK AFEFS disabled Clock generation AFECLK AFEFS enabled
Clock Master (AFECLK) 1.536 (AFECLK)
Preliminary Data Sheet
10.99
2170
Detailed Register Description Detailed Register Description
CCTL INAFECTL IFS1 IFG1 IFG2 IFS2 IFG3 IFG4 SDCONF SDCHN1 IFS3 SDCHN2 IFS4 IFG5 DGCTL DGF1 DGF2 DGATT ATDCTL0 ATDCTL1 CIDCTL0 CIDCTL1 IFS5 IFG6 CPTCTL CPTTR CPTMN CPTMX CPTDT LECCTL LECLEV LECATT LECMGN DDCTL DDTW DDLEV FCFCTL1 FCFCOF1 FCFCTL2
Revision. Chip Control Interrupt Mask Register Analog Front Interface Control. Interface Select Interface Gain Interface Gain Interface Select Interface Gain Interface Gain Serial Data Interface Configuration Serial Data Interface Channel Interface Select Serial Data Interface Channel Interface Select Interface Gain Universal Attenuator. DTMF Generator Control. DTMF Generator Frequency DTMF Generator Frequency DTMF Generator Level. DTMF Generator Attenuation Alert Tone Detection Alert Tone Detection Caller Control Caller Control Interface Select Interface Gain Call Progress Tone Control Call Progress Tone Thresholds. Minimum Times. Maximum Times. Delta Times Line Echo Cancellation Control Minimal Signal Level Line Echo Cancellation Externally Provided Attenuation Margin Double Talk Detection. DTMF Detecto
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