This errata describes corrections Revision MPC850 Family User's Manual

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MPC850R1UMAD Rev. 1.6, 4/2004 Errata MPC850 Family User's Manual, Rev.
This errata describes corrections Revision MPC850 Family User's Manual (Order MPC850UM, Rev. MPC850 versatile, one-chip integrated microprocessor peripheral combination. MPC850 includes high-performance embedded PowerPCcore communications processor module (CPM).
Document Revision History
Table Document Revision History
Rev. Substantive Change(s) Added errata items from Section (page 1-2), Section 27.7 (page 27-9), Section 27.21 (page 27-3), Section 31.4.1.2 (page 31-9), Section 34.1 (page 34-2), Section 35.2.1 (page 35-4), Appendix (page F-2). Added errata item Section 18.6.3 (page 18-13). Added errata items Section 21.2.1 (page 21-9), Section (page 22-1), Section 22.16 (22-14), Section 31.4.1.2 (page 31-9), Section B.3.1 (page B-4).
Table provides revision history this document.
Document Errata
Changes MPC850DSL part Table 1-1, change `Time-slot assigner, SMC2, supported.' following: Time-slot assigner supported.
section page numbers errata items added since last errata addendum boldfaced. Section/Page
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Section, Page 11.1.3.1, 11-3 following note: NOTE loss lock detection does have specification detection threshold. Therefore, should used solely debug tool production systems. Characterization threshold value over temperature operating voltages shown that threshold triggered when clock clock phase differences more. 11.3.1.1, 11-9 Figure 11-8, change field description (boot burst enable) field description CLES (core little-endian swap). following description Table 11-3: Changes
Table 11-3. Hard Reset Configuration Word Field Descriptions
Bits
Name
Description Boot burst enable boot device does support bursting. boot device does support bursting. Core little-endian swap. Defines core access operation following reset. endian Little endian
CLES
14.2.2.3, 14-8
Replace Table 14-2 with following:
Table 14-2. Capacitor Values Based PLPRCR[MF]
Range Minimum Capacitance Maximum Capacitance [(MF 590] Unit [(MF 425]
15.4.1,15-9
Figure 16-6, BR0, following footnote: Since base address value unknown reset, program before programming ensure proper operation.
15.4.2, 15-11
Replace text after Figure 16-7 with following: reset, specific default values read-only, shown Figure 15-8. After reset, becomes R/W.
15.8.4, 15-55 18.6.3, 18-13 21.2.1, 21-9 21.2.1, 21-9 22-1 22.16, 22-14
Remove Section 15.8.4.1, "Address Incrementing External Synchronous Bursting Masters." Remove Table 18-10 well sentence before sentence after. MODE field (bits 28-31) Table 21-2, V.14 microcode supported. Thereby, mode 0111 should reserved. MODE field (bits 28-31) Table 21-2, DDCMP microcode supported. Thereby, mode 1001 should reserved. last sentence last paragraph should removed. field (bit Table 22-9, selection second sentence paragraph (making reference V.14 applications) should removed.
Errata MPC850 Family User's Manual, Rev.
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Section, Page 27.7, 27-9 Changes superscript number after PADDR1_H, PADDR1_M, PADDR1_L, TADDR_H, TADDR_M, TADDR_L. corresponding footnote Table 27-1 with following statement: address should written little endian, Motorola's big-endian format, that physical address 112233445566 should written PADDR_L 6655, PADDR_M 4433, PADDR_H 2211. TADDR should written same PADDR. 27.21, 27-23 31.4.1.2, 31-9 step change last sentence read, "Then write 0x000E TxBD[Data. last sentence Example change order string following: first j_klmn_r_stuv last last sentence Example change order string following: first 34.1, 34-2 r_stuv_ghij_klmn last Inside second bullet, footnote sentence that states: power reset, port pins defined particular state until CLKOUT present clocks. 34.3, 34-8 34.5.1.2, 34-18 Table 34-6, RTS2 PB18, PBPAR[DDn] PBDIR[DRn] Table 34-19, description bits 3-15, following footnote definition setting (The corresponding signal output): PD10 will function open drain. 35.2.1, 35-4 B.3.1, Appendix Appendix Global
first bullet should reflect second bullet should reference
Table B-1, making reference Profibus (seventeenth row) should removed. Table B-1, column showing that Mbps MHz. Figure F-1, line over block SMC2 show that supported. following table provided clarify/correct power-on reset value many MPC850 registers lists whether each register affected HRESET and/or SRESET. `don't care' either bits, nibbles, entire register. single zero indicates entire register reset zeros. isolates bits nibble register. don't care POR, this register affected HRESET SRESET, indicates that value will remain same what before reset occurred. applicable, indicates that this register value.
Legend:
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Errata MPC850 Family User's Manual, Rev.
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Section, Page
Table
Register SIUMCR SYPCR SWSR SIPEND SIMASK SIEL SIVEC Value 01200000 FFFFFF07 0000xxxx 0000xxxx 0000xxxx (xx11)(11xx)xxxxxx XXXX0000 ??00??00 XXXXX(??00)0(000?) 00000FF4 XXXXXX(xx00)0 Affected HRESET Affected SRESET
Changes
TESR SDCR PBR0 POR0 PBR1 POR1 PBR2 POR2 PBR3 POR3 PBR4 POR4 PBR5 POR5 PBR6 POR6 PBR7 POR7 PGCRA PGCRBf PSCR PIPR
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Table (continued)
Register Value XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) (xx00)0(x000)0(xxx0)X(00xx)X xx001000 xx001000 0200 00(000x)(000x) 0(000?)(?000)(0??0)0000 ???0(0100)000 Affected HRESET Affected SRESET
MAMR MBMR MSTAT MPTPR TBSCR TBREFA TBREFB RTCSC RTSEC RTCAL PISCR PITC PITR SCCR PLPRCR
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Section, Page Changes
Table (continued)
Register TBSCRK TBREFAK TBREFBK RTCSCK RTCK RTSECK Value FFFF Affected HRESET Affected SRESET
RTCALK PISCRK PITCK SCCRK PLPRCRK RSRK I2MOD I2ADD I2BRG I2COM I2CER I2CMR SDAR SDSR SDMR IDSR1 IDMR1 IDSR2 IDMR2 CIVR CICR CIPR CIMR CISR PADIR PAPAR
Errata MPC850 Family User's Manual, Rev.
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Table (continued)
Register PAODR PADAT PCDIR PCPAR PCSO PCDAT PCINT Value FFFF FFFF FFFF FFFF Affected HRESET Affected SRESET
PDDIR PDPAR PDDAT TGCR TMR1 TMR2 TRR1 TRR2 TCR1 TCR2 TCN1 TCN2 TMR3 TMR4 TRR3 TRR4 TCR3 TCR4 TCN3 TCN4 TER1 TER2 TER3 TER4 CPCR RCCR
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Errata MPC850 Family User's Manual, Rev.
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Section, Page Changes
Table (continued)
Register RCTR1 RCTR2 RCTR3 RCTR4 RTER RTMR BRGC1 Value 7E7E 7E7E 7E7E Affected HRESET Affected SRESET
BRGC2 BRGC3 BRGC4 GSMR_L1 GSMR_H1 PSMR1 TODR1 DSR1 SCCE1 SCCM1 SCCS1 GSMR_L2 GSMR_H2 PSMR2 TODR2 DSR2 SCCE2 SCCM2 SCCS2 GSMR_L3 GSMR_H3 PSMR3 TODR3 DSR3 SCCE3 SCCM3
Errata MPC850 Family User's Manual, Rev.
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Section, Page Changes
Table (continued)
Register SCCS3 GSMR_L4 GSMR_H4 PSMR4 TODR4 DSR4 SCCE4 Value 7E7E xxx(xx00)0000 xxx(xx00)0000 Affected HRESET Affected SRESET
SCCM4 SCCS4 SMCMR1 SMCE1 SMCM1 SMCMR2 SMCE2 SMCM2 SPMODE SPIE SPIM SPCOM PIPC PTPR PBDIR PBPAR PBODR PBDAT SIMODE SIGMR SISTR SICMR SICR SIRP
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MPC850R1UMAD
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This errata describes corrections Revision MPC850 Family User's Manual

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