AK4584 24Bit 96kHz Audio CODEC with DIT/DIR AK45842496kHz24b

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AK4584 24Bit 96kHz Audio CODEC with DIT/DIR AK45842496kHz24b

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[AK4584]
AK4584
24Bit 96kHz Audio CODEC with DIT/DIR
AK45842496kHz24bit CODECADC AK458424192kHz(DIT) (DIR)AC-3/MPEGNon-PCM ADCAK4584PGA DVD-R, CD-R
*AC-3Dolby Laboratories
24bit 96kHz Single-end Input S/(N+D): 90dB Dynamic Range, S/N: 100dB Digital offset cancellation Input with +18dB gain 0.5dB step Input DATT with -72dB format: justified 24bit 192kHz 24bit times Digital Filter Ripple: ±0.005dB, Attenuation: 75dB Single-end Output S/(N+D): 94dB Dynamic Range, S/N: 104dB De-emphasis 32kHz, 44.1kHz, 48kHz sampling Digital Attenuator with soft-transition Soft Mute Zero Detect Function format: justified, justified Outputs 192kHz 3-Channel Transmission Outputs Through outputs Output) Bits Channel Status Buffer
MS0118-J-01
2001/11
[AK4584]
Inputs 24bit 192kHz Supports AES3, IEC60958, S/PDIF, EIAJ CP1201 Jitter Analog Lock Range: 192kHz Clock Source: X'tal Channels Receiver Inputs Detect Function Non-PCM Stream Detection DTS-CD Stream Detection Validity Flag Detection Sampling Frequency Detection Unlock Parity Error Detection bits Channel Status Buffer Burst Preamble Buffer Non-PCM Stream Support External Audio Clock Input Master Clock Input 256fs, 384fs, 512fs, 768fs 44.1kHz 48kHz) 256fs, 384fs 88.2kHz 96kHz) 128fs, 192fs 176.4kHz 192kHz) Support Master Slave Mode Serial I/F: 4-wire serial operation Power Supply 44pin LQFP Package 70°C
MS0118-J-01
2001/11
[AK4584]
INT0 INT1
OPS1-0 TX2E TX1E
AVDD AVSS DVDD DVSS
IPS1-0
R_LRCK R_BICK R_DATA R_MCLK
T_LRCK T_BICK T_DATA T_MCLK
TX3E
A_LRCK
D_LRCK
LOUT
IPGA
DATT
A_BICK A_DATA A_MCLK
Audio Interface
D_BICK D_DATA D_MCLK
LOUT ROUT LRCK BICK SDTO SDTI TVDD
DATT SMUTE
ROUT LRCK BICK SDTO
PVDD PVSS VREF
SDTI
X'tal
MCLK Selector
Divider
MCKI
MCKO1
VCOM MCKO1 MCKO2 DMCK XTALE
Block Diagram
MCKO2
Control Register
CDTO CDTI CCLK
MS0118-J-01
2001/11
[AK4584]
AK4584VQ AKD4584 +70°C AK4584 44pin LQFP (0.8mm pitch)
TEST1
PVDD
AVDD
PVSS
TEST2 INT0 INT1 CDTI CDTO CCLK XTALE XTI/MCKI TEST3 DMCK DVDD DVSS TVDD ROUT LOUT VCOM LRCK BICK SDTI SDTO MCKO2 MCKO1
AK4584VQ
View
MS0118-J-01
AVSS
VREF
2001/11
[AK4584]
Name TEST2 INT0 INT1 CDTI CDTO CCLK TEST3 XTALE DVDD DVSS TVDD MCKI DMCK Function Test (Internal pull-down pin) Receiver Input with 0.2Vpp Internal bonding pin, Fixed "AVSS") Receiver Input with 0.2Vpp Power-Down Mode "H": Power "L": Power down reset initialize control register. Interrupt Interrupt Control Data Input Control Data Output Control Data Clock Chip Select Test (Fixed AVSS) Transmitter Output Transmitter Output X'tal Enable Enable, Disable Transmitter Output Digital Power Supply Pin, 4.75 5.25V Digital Ground Output Buffer Power Supply Pin, 5.25V X'tal Output X'tal Input External Master Clock Input MCKO1 Disable MCKO1 output, MCKO1 output
MS0118-J-01
2001/11
[AK4584]
MCKO1 MCKO2 SDTO SDTI BICK LRCK VCOM LOUT ROUT AVSS AVDD VREF PVDD PVSS TEST1
Master Clock Output Master Clock Output Audio Serial Data Output Audio Serial Data Input Audio Serial Data Clock Input Output Channel Clock Master Slave Mode Master Mode, Slave Mode Zero Input Detect Common Voltage Output Pin, AVDD/2 Bias voltage inputs outputs. Analog Output Analog Output Analog Ground Analog Power Supply Pin, 4.75 5.25V Voltage Reference Input Pin, AVDD Used voltage reference DAC. VREF connected externally filtered AVDD. Analog Input Analog Input Power Supply Pin, 4.75 5.25V External Resistor resistor should connected PVSS externally. Ground Receiver Input with 0.2Vpp Test (Internal pull-down pin) Receiver Input with 0.2Vpp
Note: input pins except pull-down pins should left floating.
MS0118-J-01
2001/11
[AK4584]
(AVSS, DVSS, PVSS=0V; Note Parameter Power Supplies: Analog Digital Output Buffer |AVSS DVSS| (Note |AVSS PVSS| (Note Input Current, Except Supplies Analog Input Voltage (VREF, LIN, pins) Digital Input Voltage (Except RX1-4, BICK, LRCK pins) Digital Input Voltage (RX1-4 pins) Digital Input Voltage (BICK, LRCK pins) Ambient Temperature (powered applied) Storage Temperature Symbol AVDD DVDD PVDD TVDD GND1 GND2 VINA VIND1 VIND2 VIND3 Tstg -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 AVDD+0.3 DVDD+0.3 PVDD+0.3 TVDD+0.3 Units
Note: Note: AVSSDVSS, PVSS
(AVSS, DVSS, PVSS=0V; Note Parameter Power Supplies Analog (Note Digital Output Buffer Voltage Reference (Note Symbol AVDD DVDD PVDD TVDD VREF 4.75 4.75 4.75 5.25 AVDD AVDD DVDD AVDD Units
Note: Note: AVDD, DVDD, PVDD, TVDD Note: VREFAVDD
MS0118-J-01
2001/11
[AK4584]
(Ta=25°C; AVDD, DVDD, PVDD, TVDD=5.0V; AVSS=DVSS=PVSS=0V; VREF=AVDD; fs=44.1kHz, 96kHz, 192kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=10Hz 20kHz fs=44.1kHz, 10Hz 40kHz fs=96kHz; 10Hz 80kHz fs=192kHz; unless otherwise specified) Parameter Units Input Characteristics: Input Voltage (Note fs=44.1kHz, AIN=0.6 AVDD fs=96kHz, AIN=0.62 AVDD Input Resistance Step Size Gain Control Range Analog Input Characteristics: IPGA=0dB Resolution Bits S/(N+D) (-0.5dBFS) fs=44.1kHz fs=96kHz (-60dBFS) fs=44.1kHz, A-weighted fs=96kHz fs=44.1kHz, A-weighted fs=96kHz Interchannel Isolation Interchannel Gain Mismatch Gain Drift ppm/°C Power Supply Rejection (Note Analog Output Characteristics: Resolution Bits S/(N+D) (0dBFS) fs=44.1kHz fs=96kHz fs=192kHz (-60dBFS) fs=44.1kHz, A-weighted fs=96kHz fs=192kHz fs=44.1kHz, A-weighted fs=96kHz fs=192kHz Interchannel Isolation Interchannel Gain Mismatch Gain Drift ppm/°C Output Voltage (Note Load Resistance Load Capacitance Power Supply Rejection (Note Note: IPGA=0dB(0dB) Note: VREFAVDD, DVDD, PVDD, TVDD1kHz, 50mVpp Note: VREFVout VREF
MS0118-J-01
2001/11
[AK4584]
Parameter Power Supplies Power Supply Current Normal Operation (PDN "H") AVDD PVDD (fs=44.1kHz) DVDD+TVDD (fs=44.1kHz) (fs=96kHz) Power-down mode (PDN "L") (Note AVDD PVDD DVDD+TVDD
Units
Note: DVDDDVSS
S/PDIF RECEIVER
(Ta=25°C; AVDD, DVDD, PVDD=4.75 5.25V; TVDD=2.7 5.25V) Parameter Symbol Input Resistance Input Voltage Input Hysteresis Input Sample Frequency Units mVpp
MS0118-J-01
2001/11
[AK4584]
(Ta=-10 70°C; AVDD, DVDD, PVDD=4.75 5.25V; TVDD=2.7 5.25V; fs=44.1kHz; DEM=OFF) Parameter Symbol Digital Filter (Decimation LPF): Passband (Note ±0.005dB 19.76 -0.02dB 20.02 -0.06dB 20.20 -6.0dB 22.05 Stopband 24.34 Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note Group Delay Distortion Digital Filter (HPF): Frequency Response (Note -3dB -0.5dB -0.1dB Digital Filter: Passband (Note ±0.01dB 20.0 -6.0dB 22.05 Stopband 24.1 Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note Digital Filter SMF: Frequency Response: 20kHz -0.1 40kHz (Note -0.2 80kHz (Note -1.0 Units 1/fs 1/fs
Note: PB=20.02kHz (@-0.02dB)0.454 fs1kHz Note: 24ADC DAC24DAC Note: fs=96kHz Note: fs=192kHz
MS0118-J-01
2001/11
[AK4584]
(Ta=-10 70°C; AVDD, DVDD, PVDD=4.75 5.25V; TVDD=2.7 5.25V) Parameter Symbol High-Level Input Voltage (Except pin) (XTI pin) 70%DVDD Low-Level Input Voltage (Except pin) (XTI pin) Input Voltage Coupling (XTI pin, Note 40%DVDD High-Level Output Voltage (Except TX1-3, pins Iout=-400µA) TVDD-0.5 (TX1-3 Iout=-400µA) DVDD-0.5 (DZF Iout=-400µA) AVDD-0.5 Low-Level Output Voltage (Iout=400µA) Output Voltage Level (Note Input Leakage Current Note: XTI(Figure Note: Figure 30%DVDD Units
MS0118-J-01
2001/11
[AK4584]
(Ta=-10 70°C; AVDD, DVDD, PVDD=4.75 5.25V, TVDD=2.7 5.25V; CL=20pF) Parameter Symbol Master Clock Timing Crystal Resonator External Clock Frequency Frequency Pulse Width Pulse Width High Frequency Duty Cycle (Note Frequency Duty Cycle 11.2896 11.2896 0.4/fCLK 0.4/fCLK 11.2896 5.6448 88.2 176.4 24.576 36.864 Units
fCLK tCLKL tCLKH fMCK dMCK fMCK dMCK fPLL
MCKO1 Output MCKO2 Output
24.576 18.432
Clock Recover Frequency LRCK Frequency Normal Speed Mode (DFS0="0", DFS1="0") Double Speed Mode (DFS0="1", DFS1="0") Quad Speed Mode (DFS0="0", DFS1="1") Duty Cycle Slave mode Master mode Audio Interface Timing Slave mode BICK Period BICK Pulse Width Pulse Width High LRCK Edge BICK (Note BICK LRCK Edge (Note LRCK SDTO (MSB) (Except mode) BICK SDTO SDTI Hold Time SDTI Setup Time Master mode BICK Frequency BICK Duty BICK LRCK BICK SDTO SDTI Hold Time SDTI Setup Time
tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS
64fs
Note: Duty Note: LRCKBICK""
MS0118-J-01
2001/11
[AK4584]
Parameter Control Interface Timing CCLK Period CCLK Pulse Width Pulse Width High CDTI Setup Time CDTI Hold Time Time CCLK CCLK CDTO Delay CDTO Hi-Z Reset Timing Pulse Width RSTADN SDTO valid (Note (Note
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ tPDV
Units 1/fs
Note: AK4584PDN Note: RSTADNLRCK""
MS0118-J-01
2001/11
[AK4584]
1/fCLK MCLK tCLKH 1/fs LRCK tBCK BICK tBCKH fMCK tBCKL tCLKL
MCKO dMCK dMCK
Clock Timing
50%TVDD
MS0118-J-01
2001/11
[AK4584]
LRCK tBLR tLRB BICK tLRS tBSD
SDTO tSDS tSDH
50%TVDD
SDTI
Audio Interface Timing (Slave mode)
LRCK
50%TVDD
tMBLR
dBCK 50%TVDD
BICK
tBSD
SDTO tSDS tSDH
50%TVDD
SDTI
Audio Interface Timing (Master mode)
MS0118-J-01
2001/11
[AK4584]
tCSS tCCKL tCCKH CCLK tCDS CDTI tCDH Hi-Z
CDTO
WRITE/READ Command Input Timing
tCSW tCSH CCLK
CDTI Hi-Z
CDTO
WRITE Data Input Timing
MS0118-J-01
2001/11
[AK4584]
CCLK
CDTI tDCD CDTO Hi-Z 50%TVDD
READ Data Output Timing
tCSW tCSH CCLK
CDTI tCCZ Hi-Z
CDTO
50%TVDD
READ Data Output Timing
MS0118-J-01
2001/11
[AK4584]
tPDV
SDTO
50%TVDD
Power Down Reset Timing
MS0118-J-01
2001/11
[AK4584]
DAC, SDTOADC, SDTI, DIRDITADC, SDTI1 DIR, DIT(DAC1-0 etc) (08H)
IPGA DATT
DAC1-0
DATT SMUTE
SDTI
PCM1-0
SDTO
DIT1-0
DIT1-0
Figure Connection Input Source Output Source
AK4584PLLX'tal() CM1-0(Table 1)Mode 2PLLUnlockX'tal Mode 3X'talRX Mode 3PLLX'talXTALE="L" XTL1-0="11"Mode 0X'talCM1-0"01" CM1-008H Mode UNLOCK X'tal Clock Source X'tal X'tal X'tal (Power-up), (Power-down) XTALE="L"XTL1-0="11"OFFON Table Clock Operation Mode Select
Default
MS0118-J-01
2001/11
[AK4584]
AK45842 X'talPLL (MCKO1 MCKO2)fsOCKS1-0(Table 2)X'tal (MCKO1 MCKO2)11/2(Table MCKO1DMCK DMCK="H""L"()DMCK="L"PLL fsTable 2Mode 096kHz OCKS1-0"01" Mode OCKS1 OCKS0 MCKO1 512fs 256fs 128fs 64fs MCKO2 256fs 128fs 64fs 32fs 48kHz 96kHz 192kHz 192kHz
Default
Table Master Clock Output Frequency Select (PLL Mode) X'tal MCKO1 MCKO2 11.2896MHz 11.2896MHz 5.6448MHz 12.288MHz 12.288MHz 6.144MHz 24.576MHZ 24.576MHz 12.288MHz Table Master Clock Output Frequency Select (X'tal Mode) ADC(AK5394)DAC(AK4394)AK4584 AK4584 AK5394, AK4394 AK5394 AK4394 MCKO2 MCKO1 256fs 512fs 128fs 256fs 64fs 128fs Table Clock Select AK5394 AK4394
MS0118-J-01
2001/11
[AK4584]
(MCLK)XTIXTOX'talXTO XTICMOS AC40%DVDD PLLX'tal ICKS1-0(Table 5)DFS1-0 24(Table 6)4ADC X'tal(XTI/XTODVSS) DVDDCMOS40%DVDD LRCK (PDN="H"PWVRN"H") (MCLK, BICK, LRCK) (PDN "L"PWVRN"L") X'tal (MCLK)PLL MCLK Normal Double Quad ICKS1 ICKS0 (DFS1-0 "00") (DFS1-0 "01") (DFS1-0 "10") 256fs 384s 512fs 256fs 128fs 768fs 384fs 192fs Table Master Clock Input Frequency Select (X'tal Mode) DFS1 DFS0 Sampling Rate Default
Mode
Default
Table Sampling Speed MCLK Double 128fs 192fs 256fs 384fs
MCLK Normal 256fs 384fs 512fs 768fs MCLK Normal 256fs 384fs 512fs 768fs
fs=44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
fs=88.2kHz 22.5792MHz 33.8688MHz
MCLK Quad 64fs 96fs 128fs 192fs
fs=176.4kHz 22.5792MHz 33.8688MHz
MCLK MCLK Double Quad fs=48kHz fs=96kHz 12.288MHz 128fs 64fs 18.432MHz 192fs 96fs 24.576MHz 256fs 24.576MHz 128fs 36.864MHz 384fs 36.864MHz 192fs Table Master Clock Frequencies example
fs=192kHz 24.576MHz 36.864MHz
*11.2896MHz24.576MHz *24.576MHz
MS0118-J-01
2001/11
[AK4584]
X'tal
AK4584
Figure X'tal mode Note: (typ. 40pF)
External Clock AK4584
External Clock
AK4584
Figure External Clock mode Figure External Clock Mode (Input CMOS Level) (Input 40%DVDD) Note: DVDD XTI/XTO
AK4584
Figure mode
192kHz
PLL32kHz192kHz20ms X'tal(32k, 44.1k, 48k, 88.2k, 96k, 176.4k, 192k)
MS0118-J-01
2001/11
[AK4584]
AK45844(RX1-4)200mVpp IPS1 IPS0 Input Data Table Recovery Data Select
Default
TX1-2RXTX3SDTI A/DIEC60958RX TX1-2OPS1-0TX3DIT1-0 TX1-3TX1E, TX2E, TX3E C5byte(CT0="0") bit20-23(Audio Channel)TCH"1"Sub frame 1"1000"()Sub frame 2"0100"()TCH"0" "0000"() UUDIT2UDIT"0""0"UDIT "1"UDITPLL PLLU"0" OPS1 OPS0 Output Data Table Output Data Select TX1/2
Default
DIT1
DIT0 Input Source SDTI Table Output Data Select
Default
Note: V-bit1
MS0118-J-01
2001/11
[AK4584]
0.1uF Coax
AK4584
Figure Consumer Input Circuit (Coaxial Input) Note CoaxialRX50mV Note PCAK4584PVSS Optical Receiver Optical Fiber
AK4584
Figure Consumer Input Circuit (Optical Input) Coaxial AK4584TX0.5V+/-20%Figure 7T11:1 DVSS Figure External Resistor Network cable
MS0118-J-01
2001/11
[AK4584]
XTL1-0 X'tal FS3-0X'tal XTALE="L"XTL1-0="11" FS3-0FS30"0000" XTL1 XTL0 X'tal Frequency 11.2896MHz 12.288MHz 24.576MHz Table Reference X'tal Frequency
Default
XTL1-0="11" Register Output 44.1kHz Reserved 48kHz 32kHz 88.2kHz 96kHz 176.4kHz 192kHz Table Information Clock comparison
XTL1-0="11" Consumer Mode Mode (Note Byte3 Byte0 Byte4 Bit3,2,1,0 Bit7,6 Bit6,5,4,3 0000 0000 0001 (others) 0000 0010 0000 0011 0000 (1000) 1010 (1010) 0010 (1100) 1011 (1110) 0011
Note When consumer mode, Byte3 Bit3-0 copied FS3-0. (CS12="0")1 CS12"1"2 Byte0 Bit3,4,5 0X100 0X100 Table Consumer Mode Pre-emphasis Byte0 Bit2,3,4 Table Mode Pre-emphasis
MS0118-J-01
2001/11
[AK4584]
INT1-0"H"8 UNOCK: PLL"H" PAR: Non-Linear
AUTO:
DTSCD: DTS-CD AUDION:Non-Audio PEM: FS3-01"H" FS3-0C-bitfs-bitX'tal(Table 12)1
(1)(8)ORINT INT(0EH)INT0 1024/fs(EFH1-0)"H"PAR FS"1"0EH INT0UNLOCK, PARINT1AUTO, DTSCD, AUDION, VDIR PLLOFFINT1-0"L" Register DTSCD AUDION VDIR Table Error Handling Don't Care) SDTO Previous Data Output Output Output Output Output Output
UNLOCK
AUTO
Output Output Output Output Output Output Output Output
Note Table 15SDTODIR
MS0118-J-01
2001/11
[AK4584]
Error (UNLOCK, PAR,.) INT0
(Error)
Hold Time (max: 4096/fs)
INT1 Register (PAR, Register (others) Command MCKO,BICK,LRCK (UNLOCK) MCKO,BICK,LRCK (except UNLOCK) SDTO (UNLOCK) SDTO (PAR error) SDTO (others) Previous Data
Hold Time
Hold
Reset
READ
Free (fs: around 20kHz)
Normal Operation Figure INT0/1 Timing
MS0118-J-01
2001/11
[AK4584]
Initialize Read
INT0/1
Release Muting
Mute Output
Read Each Error Handling
INT0/1
Figure Error Handling Sequence Example
Non-PCM/DTS-CD
AK4584Non-PCMDolby "AC-3 Data Stream IEC60958 Interface" 32bit ModeNon-PCMAUTO"1" 96bit sync code0x0000, 0x0000, 0x0000, 0x0000, 0xF872 0x4E1F4096 sync codesync codeAUTO"0" sync code2(Pc, Pd)DTS-CD DTS-CD"1"4096sync code sync codeDTS-CD"0"
MS0118-J-01
2001/11
[AK4584]
5(Table 16)DIF2-0MSB2's SDTOBICK SDTIBICK LRCKBICKLRCKBICK fs64fs 20(Mode0-1)LSBMode2-44 AuxFigure SDTIMode2, 20LSB"0"
sub-frame IEC60958
Aux.
preamble
AK4584 Audio Data (SDTO, First)
Figure Structure Mode DIF2 DIF1 DIF0 SDTO SDTI 24bit, justified 16bit, justified 24bit, justified 20bit, justified 24bit, justified 24bit, justified 24bit, Compatible 24bit, Compatible 24bit, justified 24bit, justified Table Audio Data Format LRCK BICK 32fs 40fs 48fs 48fs 48fs
Default
MS0118-J-01
2001/11
[AK4584]
LRCK
BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i)
Don't Care Don't Care
SDTO-23:MSB, 0:LSB SDTI-15:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care
Don't Care
SDTO-23:MSB, 0:LSB SDTI-19:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care
Don't Care
23:MSB, 0:LSB Data Data
Figure Mode Timing
MS0118-J-01
2001/11
[AK4584]
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care Don't Care
23:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care 23:MSB, 0:LSB
Don't Care
Data
Data
Figure Mode Timing
MS0118-J-01
2001/11
[AK4584]
AK4584AK4584MCKO, BICK, LRCKAK4584 AK4584MCKO BICK, LRCKDSP DSPMCKOBICK, LRCK MCKO1/2 BICK, LRCK MCKO1 Output BICK Input Slave Mode MCKO2 Output LRCK Input MCKO1 Output BICK Output Master Mode MCKO2 Output LRCK Output Table Master mode/Slave mode
AK4584/XTALE MCKO1DMCK Don't Care default "01" XTALE CM1-0 MCKO1/2 MCKO1 MCKO2 MCKO1 Output1) MCKO2 Output1) MCKO1 MCKO2 MCKO1 Output1) MCKO2 Output1) MCKO1 Output2) MCKO2 Output2) BICK, LRCK BICK Input LRCK Input DIR, CODEC Power Down
BICK LRCK BICK Input LRCK Input BICK Output LRCK Output
Power Down
Normal Operation
Table Clock Operation Note DIRX'tal Note CM1-0MCKO Note: XTALE="L"ACPDN"L" XTI"L"
ADCDCHPFHPFfcfs=44.1kHz0.9Hz
MS0118-J-01
2001/11
[AK4584]
ADC370.5dB2ch(IPGA)128 ()(ATT: IATT) MSB"1"IPGA"0"IATT IPGAS/N(Table (To)fs To=256/fs2048/fsIPGA IPGAIPGA (L/R)IPGA (ZCEI)ON/OFF IATT8031 Input Gain Setting +6dB fs=44.1kHz, A-weight 100dB 98dB Table PGA+ADC ZTM1 ZTM0 256/fs 512/fs 512/fs 1024/fs 1024/fs 2048/fs 2048/fs 4096/fs Table Zero Crossing Timeout
+18dB 90dB
Default
IIR3(32kHz, 44.1kHz, 48kHz)(50/15µs) DEM1-0(Table 21)24 DEM1 DEM0 Mode
44.1kHz Default 48kHz 32kHz Table De-emphasis Control
AK4584MUTE0.5dB256(ATT) DAC0dB-127dB
MS0118-J-01
2001/11
[AK4584]
DACSMUTE SMUTE"H"1024LRCKDAC- ("0") SMUTE"L"- -1024LRCK0dB 1024LRCK
SMUTE 1024/fs Attenuation 1024/fs
LOUT ROUT
8192/fs
Figure 1024LRCK(1024/fs) ("0") (GD) 1024LRCK 8192"0"DZF"H" "0"DZF"L"
MS0118-J-01
2001/11
[AK4584]
AK4584DACL/R L/R8192 "0"DZF"H""0"DZF"L" DZFEDZF"L" PDN"L"DZF"L"PDN(PDN="L" "H")DZF"L" "H"PWVRN"0"DZF"L" RSTDAN"0"DZF"H"4/fs 5/fsLSI RSTDAN"1"6/fs 7/fsDZF"H""L" RSTDAN"0"5/fsRSTDAN"1" PWDAN"0"DZF"H"4/fs 5/fsLSI PWDAN"1"6/fs 7/fsDZF"H""L" PWDAN"0"5/fsPWDAN"1"LSI PDN="H"PWDAN="1"RSTDAN="1"1/fs 8192
AK4584PDN(Table 22)PDN"L" PWDITN PWVRN PWADN PWDAN CM1-0 Function Power-down Power-down VREF Power-down Power-down Power-down X'tal Power-down Power-down Table Reset Power Down Register Initialization
MS0118-J-01
2001/11
[AK4584]
4I/F CSN, CCLK, CDTI, CDTOI/FChip address(2bits, C1/0, "00")Read/Write(1bit)Register address(MSB first, 5bits)Control data(MSB first, 8bits) CCLK"""" CSN"" CCLK5MHz(max) "H""L""00""00" PDN="L"
CCLK
CDTI Write CDTO
Hi-Z
CDTI Read CDTO
Hi-Z Chip Address (Fixed "00") READ WRITE ("1" WRITE, READ) Register Address Control Data
Hi-Z
Figure Control Timing
MS0118-J-01
2001/11
[AK4584]
Addr Register Name Power Down Control Reset Control Clock Format Control Deem Volume Control IPGA Control IPGA Control OATT Control OATT Control In/Out Source Control Clock Mode Control Control Control INT0 Mask INT1 Mask Receiver Status Receiver Status Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte MSDTO IPGL7 IPGR7 ATTL7 ATTR7 OCKS1 MAT0 MAT1 AUTO CR15 CR23 CR31 CR39 CT15 CT23 CT31 CT39 PC15 PD15 SMUTE IPGL6 IPGR6 ATTL6 ATTR6 OCKS0 CS12 MDTS0 MDTS1 DTSCD CR14 CR22 CR30 CR38 CT14 CT22 CT30 CT38 PC14 PD14 DZFE IPGL5 IPGR5 ATTL5 ATTR5 DAC1 ICKS1 OPS1 TX3E MAN0 MAN1 AUDION CR13 CR21 CR29 CR37 CT13 CT21 CT29 CT37 PC13 PD13 TEST DIF2 ZCEI IPGL4 IPGR4 ATTL4 ATTR4 DAC0 ICKS0 OPS0 TX2E VDIR CR12 CR20 CR28 CR36 CT12 CT20 CT28 CT36 PC12 PD12 PWDITN DIF1 ZTM1 IPGL3 IPGR3 ATTL3 ATTR3 PCM1 IPS1 TX1E MPE0 MPE1 CR11 CR19 CR27 CR35 CT11 CT19 CT27 CT35 PC11 PD11 PWVRN DIF0 ZTM0 IPGL2 IPGR2 ATTL2 ATTR2 PCM0 IPS0 UDIT MUL0 MUL1 UNLOCK CR10 CR18 CR26 CR34 CT10 CT18 CT26 CT34 PC10 PD10 PWADN RSTADN DFS1 DEM1 IPGL1 IPGR1 ATTL1 ATTR1 DIT1 XTL1 EFH1 VDIT MPR0 MPR1 CR17 CR25 CR33 CT17 CT25 CT33 PWDAN RSTDAN DFS0 DEM0 IPGL0 IPGR0 ATTL0 ATTR0 DIT0 XTL0 EFH0 MFS0 MFS1 CR16 CR24 CR32 CT16 CT24 CT32
resets registers their default values.
PDN"L""H" AK4584 RSTADN, RSTDAN"1"Reset Control Register (01H) ADCDAC LRCKBICK RSTADNRSTDAN"0"ADC DACLRCKBICK
MS0118-J-01
2001/11
[AK4584]
Addr Register Name Power Down Control Default TEST PWDITN PWVRN PWADN PWDAN
PWDAN: Power Down Power down Power "0"DACLOUT/ROUTHi-ZATT "FFH" (06H, 07H) PWADN: Power Down Power down Power "0"ADCSDTO"L"PGA"00H" PGA(04H, 05H)516LRCK"0" PWVRN: VREF Power Down Power down Power PWDITN: Power Down Power down Power "0"DITTX1, TEST: TEST
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name Reset Control Default
RSTADN
RSTDAN
RSTDAN: Reset Reset Normal Operation "0"DACLOUT/ROUTVCOM ATT"FFH" (06H, 07H) RSTADN: Reset Reset Normal Operation "0"ADC SDTO"L" PGA"00H" PGA(04H, 05H)516LRCK"0"
Addr
Register Name Clock Format Control Default
DIF2
DIF1
DIF0
DFS1
DFS0
DFS1-0: Sampling Speed Control (see Table "00" DIF2-0: Audio Data Interface Modes (see Table "010"(ADC, DAC24bit)
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name Deem Volume Control Default
MSDTO
SMUTE
DZFE
ZCEI
ZTM1
ZTM0
DEM1
DEM0
DEM1-0: De-emphasis Response (see Table "01"(OFF) ZTM1-0: Zero Crossing Time-out Period Select (see Table "10"(1024/fs) ZCEI: IPGA Zero Crossing Enable Input gain changes occur immediately Input gain changes occur only zero-crossing after timeout. "1"() DZFE: Data Zero Detect Enable Disable Enable DZFE"0"DZF"L" "0"() SMUTE: Input Soft Mute Control Normal operation outputs soft-muted MSDTO: SDTO Mute Control Disable Enable MSDTO"1"SDTOSDTO"L" "0"()
Addr
Register Name IPGA Control IPGA Control Default
IPGL7 IPGR7
IPGL6 IPGR6
IPGL5 IPGR5
IPGL4 IPGR4
IPGL3 IPGR3
IPGL2 IPGR2
IPGL1 IPGR1
IPGL0 IPGR0
IPGL/R7-0: Input Gain Level (see Table "7FH" (0dB) 7FH128ATT ATT8032 ATT128ATT 803212712680317775fs PDN"L""00H"PDN"H""7FH"8031 PWADN="0""00H"PWADN="1" 516"0" RSTADN="0""00H"RSTADN="1" 516"0"
MS0118-J-01
2001/11
[AK4584]
Data
(DATT) 8031 7775 7519 4191 3999 3871 2079 1983 1919 1023
Gain (dB) +17.5 +1.0 +0.5 -0.28 -0.57 -5.65 -6.06 -6.34 -11.74 -12.15 -12.43 -17.90 -18.32 -18.61 -24.20 -24.64 -24.94 -30.82 -31.29 -31.61 -38.18 -38.73 -39.11 -47.73 -48.55 -49.15 -58.10 -60.03 -62.53 -66.05 -72.07 MUTE
Step (dB) 0.28 0.29 0.51 0.41 0.28 0.52 0.41 0.28 0.53 0.42 0.29 0.54 0.43 0.30 0.58 0.46 0.32 0.67 0.54 0.38 0.99 0.83 0.60 1.58 1.94 2.50 3.52 6.02
IPGA 0.5dB step
IATT 1288032 DATT DATT =2^m Data3-bits Data4-bits
Table IPGA Code Table
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name OATT Control OATT Control Default
ATTL7 ATTR7
ATTL6 ATTR6
ATTL5 ATTR5
ATTL4 ATTR4
ATTL3 ATTR3
ATTL2 ATTR2
ATTL1 ATTR1
ATTL0 ATTR0
ATTL/R7-0: OATT Level (see Table "FFH" (0dB) ATTL/R7-07425FFH(0dB)00H(MUTE) 7424/fs(168ms@fs=44.1kHz) PDN"L"ATTL/R7-0FFH PWDAN="0""FFH"PWDAN="1" RSTDAN="0""FFH"RSTDAN="1" ATTL/R7-0 Attenuation -0.5dB -1.0dB -1.5dB -126.5dB -127dB MUTE Table OATT Code Table
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name In/Out Source Control Default
DAC1
DAC0
PCM1
PCM0
DIT1
DIT0
DIT1-0:
Input Selector (see Table "00""10"(TX1/2)
PCM1-0: Input Selector SDTO (see Table "00" PCM1 PCM0 Input Source SDTI Table Input Selector SDTO
Default
DAC1-0: Input Selector (see Table "00" DAC1 DAC0 Input Source SDTI Table Input Selector
Default
Addr
Register Name Clock Mode Control Default
OCKS1
OCKS0
ICKS1
ICKS0
XTL1
XTL0
XTL1-0: X'tal Frequency Select (see Table "00" CM1-0: Master Clock Operation Mode Select (see Table "01" ICKS1-0: Master Clock Input Frequency Select X'tal Mode (see Table "00" OCKS1-0: Master Clock Output Frequency Select Mode (see Table "01"
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name Control Default
CS12
OPS1
OPS0
IPS1
IPS0
EFH1
EFH0
EFH1-0: Interrupt Hold Count Select (Table "01" Table 27LRCKDIRLRCK1/fs EFH1 EFH0 Hold Count 512LRCK 1024LRCK 2048LRCK 4096LRCK Table Hold Count Select
Default
IPS1-0:
Input Recovery Data Select (see Table "00"
OPS1-0: Output Through Data Select TX1/2 (see Table "00" CS12: Channel Status Select Channel Channel C-bit, AUDION, PEM,
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name Control Default
TX3E
TX2E
TX1E
UDIT
VDIT
TCH: Channel Number Select Don't care (bit20-23 0000) Stereo (bit20-23 1000 channel, bit20-23 0100 channel) DIT(C-bitbit20-23)"0" (CT0="0")17HCT20-23 VDIT: V-bit Control Valid Invalid UDIT: U-bit Control U-bit fixed "0". Recovered U-bit used DIT. (Loop mode U-bit) DIRU-bit"0""1" TX1E: Output Enable Disable, outputs "L". Enable TX2E: Output Enable Disable, outputs "L". Enable TX3E: Output Enable Disable, outputs "L". Enable
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name INT0 Mask Default
MAT0
MDTS0
MAN0
MPE0
MUL0
MPR0
MFS0
MFS0: Mask Enable Mask disable Mask enable MPR0: Mask Enable Mask disable Mask enable MUL0: Mask Enable UNLOCK Mask disable Mask enable MPE0: Mask Enable Mask disable Mask enable MV0: Mask Enable VDIR Mask disable Mask enable MAN0: Mask Enable AUDION Mask disable Mask enable MDTS0: Mask Enable DTSCD Mask disable Mask enable MAT0: Mask Enable AUTO Mask disable Mask enable
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name INT1 Mask Default
MAT1
MDTS1
MAN1
MPE1
MUL1
MPR1
MFS1
MFS1: Mask Enable Mask disable Mask enable MPR1: Mask Enable Mask disable Mask enable MUL1: Mask Enable UNLOCK Mask disable Mask enable MPE1: Mask Enable Mask disable Mask enable MV1: Mask Enable VDIR Mask disable Mask enable MAN1: Mask Enable AUDION Mask disable Mask enable MDTS1: Mask Enable DTSCD Mask disable Mask enable MAT1: Mask Enable AUTO Mask disable Mask enable
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name Receiver Status Default
AUTO
DTSCD
AUDION
VDIR
UNLOCK
Sampling Frequency Status change Change 0FHFS3-0"1"0EH PAR: Parity Error Bi-phase Error Status error Error PAR"1" UNLOCK: Lock Status Lock Unlock PEM: Pre-emphasis Output VDIR: Validity Valid Invalid AUDION: Audio Output Audio audio DTSCD: DTS-CD Auto Detect detect Detect AUTO: Non-PCM Auto Detect detect Detect
MS0118-J-01
2001/11
[AK4584]
Addr
Register Name Receiver Status Default
FS3-0:
Sampling Frequency Detection (see Table "0000"
Addr
Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default
CR15 CR23 CR31 CR39
CR14 CR22 CR30 CR38
CR13 CR21 CR29 CR37
CR12 CR20 CR28 CR36
CR11 CR19 CR27 CR35
CR10 CR18 CR26 CR34
CR17 CR25 CR33
CR16 CR24 CR32
Initialized
CR39-0:
Receiver Channel Status Byte
Addr
Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default
CT15 CT23 CT31 CT39
CT14 CT22 CT30 CT38
CT13 CT21 CT29 CT37
CT12 CT20 CT28 CT36
CT11 CT19 CT27 CT35
CT10 CT18 CT26 CT34
CT17 CT25 CT33
CT16 CT24 CT32
CT39-0: Transmitter Channel Status Byte (CT0="0")CT20-23
Addr
Register Name Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Default
PC15 PD15
PC14 PD14
PC13 PD13
PC12 PD12
PC11 PD11
PC10 PD10
Initialized
PC15-0: PD15-0:
Burst Preamble Byte Burst Preamble Byte
MS0118-J-01
2001/11
[AK4584]
Figure 18(AKD4584) TVDD 3.0V, XTALE "H", DMCK
S/PDIF sources
Shield 0.1µ Shield TEST2 TEST1 PVSS PVDD
Analog
0.1µ VREF AVDD AVSS ROUT LOUT VCOM
MUTE MUTE
Shield
0.1µ
2.2µ
Control
INT0 INT1
AK4584
LRCK BICK SDTI SDTO MCKO2 XTI/MCKI MCKO1 DMCK
CDTI CDTO CCLK XTALE TEST3 DVDD TVDD DVSS
Audio
0.1µ 0.1µ
S/PDIF
Digital
11.2896MHz 24.576MHzC AK4584AGND, DGND LOUT/ROUT TEST1, TEST2, NCRX(PVSS) (TEST1, R13k 1%PVSS Figure Typical Connection Diagram
MS0118-J-01
2001/11
[AK4584]
AVDD, DVDD, PVDD AVDD, DVDD, PVDD TVDDICI/FAVSS, DVSS, PVSS VREFAVSS VREFAVDD AVSS 0.1µF VCOM 2.2µF0.1µF AVSS VCOM VREFVCOM 10k(typ) (AVDD/2)0.6 VREF Vpp(typ)DC fc=1/(2RC)AK4584AVSSAVDD 2'sDC(ADCDC) AK458464fs64fs AK458464fs (RC) (AVDD/2)0.6x VREF Vpp(typ) 2's7FFFFFH(@24bit) ()(SCF) XTIXTO XTIXTOCC (typ. 40pF) XTOXTIDVDD XTICMOSXTALE"L"PDN "L"XTI"L"DVDD ACXTI40%DVDD XTALEPDNXTI XTIXTOXTOXTIDVSS
MS0118-J-01
2001/11
[AK4584]
44pin LQFP (Unit: 12.80 0.30 10.00
1.70max
12.80 0.30
0.80
10.00
0.37 0.10
0.17 0.05
0.15
0.60 0.20
Material Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Solder free) plate
MS0118-J-01
2001/11
[AK4584]
AK4584VQ XXXXXXX
XXXXXXX Date Code Identifier digits)
MS0118-J-01
2001/11

AK4584 24Bit 96kHz Audio CODEC with DIT/DIR AK45842496kHz24b

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