Freescale Semiconductor, Inc. Introduction Introduction.1 Mo
|
|
|
Top Searches for this datasheet
DSP56321RMAD/D Rev. 7/2003 DSP56321 Reference Manual
Freescale Semiconductor, Inc.
Introduction
Introduction.1 Modified Signal Definitions.1 Operating Mode Register (OMR) Layout Definition.2 Control Register (BCR) Layout Definition.3 GPIO Signal Names Address.5 Receive Register (SRX) Description Updated Programming Sheets.5
This document provides updated information revision DSP56321 Reference Manual (DSP56321RM/D). updates include following: Modified signal definitions some external control, HI08, ESSI, SCI, timer signals Operating Mode Register (OMR) layout definitions Control Register (BCR) layout definitions Updated GPIO signal names Updated address Updated Receive Register (SRX) description Updated Programming sheets OMR, BCR, Address Attribute Registers (AAR[3-0]), Timer Registers (TLR, TCPR, TCR)
Modified Signal Definitions
Change Description
Change HA10 HA10 Change title third column State During Reset, Stop, Wait Change Signal Description following: Transfer Acknowledge-If DSP56321 master there external activity, DSP56321 master, input ignored. input data transfer acknowledge (DTACK) function that extend external cycle indefinitely. number wait states .infinity) added wait states inserted control register (BCR) keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. correct operation, must Operating Mode Register (OMR) synchronize signal with internal clock. current cycle completes clock period after deasserted. number wait states determined input BCR, whichever longer. sets minimum number wait states external `cycles. order functionality, must programmed least wait state. zero wait state access cannot extended deassertion. Change signal State During Reset, Stop, Wait Reset: Output (deasserted) State during Stop/Wait depends setting: Output, deasserted Maintains last state (that asserted, remains asserted) Change signal State During Reset, Stop, Wait Ignored input
Area Change
Figure 2-1, Table 2-8,
What's New?
Rev. adds following update: Section updates listed address Host Data Register (HDR).
More Information This Product, www.freescale.com
Operating Mode Register (OMR) Layout Definition
Area Change
Table 2-10, 2-10
Change Description
Change title third column State During Reset1,2. note that states: Note: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, keeper circuit maintains last output level even internal driver tri-stated. Change note note Change State During Reset signals Ignored input. Change signal description PB14 Port B14-When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. Delete Stop column Change title third column State During Reset Change State During Reset signals Ignored input. Note: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, keeper circuit maintains last output level even internal driver tri-stated. Change note note
Freescale Semiconductor, Inc.
Table 2-11, 2-11 2-12 Table 2-12, 2-13 2-14 Table 2-13, 2-15 Table 2-14, 2-16
Operating Mode Register (OMR) Layout Definition
Area Change
Figure 4-2, 4-10
Change Description
Replace with following figure:
Stack Control/Status (SCS)
MSW[2-1]
Extended Operating Mode (EOM)
Chip Operating Mode (COM)
CDP[1-0] MSW0
Reset:
After reset, these bits reflect corresponding value mode input (that MODD, MODC, MODB, MODA, respectively). Reserved bit. Read zero; write zero future compatibility
Figure 4-2. Operating Mode Register (OMR)
Area Change
Table 4-3, 4-11
Change Description
Replace first table following rows:
22-21 MSW[2-1]
Reserved. Write future compatibility. Memory Switch Mode Bits Used with (MSW0), three bits configure internal memory sizes Program, X-data, Y-data memory. Table details. Notes: ensure proper operation, place instructions after instruction that changes bits. ensure proper operation, change bits while Instruction Cache enabled (SR[CE] set).
More Information This Product, www.freescale.com
Control Register (BCR) Layout Definition
Area Change
Table 4-3, 4-11
Change Description
change contents following:
Reserved. Write future compatibility.
Area Change
Table 4-3, 4-11
Change Description
change contents following:
Freescale Semiconductor, Inc.
Synchronize Select Selects synchronization method input Port pin-TA (Transfer Acknowledge). correct operation used, must synchronize signal with internal clock.
Area Change
Table 4-3, 4-11
Change Description
change contents following:
MSW0
Memory Switch Mode Used with bits 22-21 (MSW[2-1]). bits 22-21 details.
Control Register (BCR) Layout Definition
Area Change
Figure 4-5, 4-20
Change Description
Replace with following figure:
BDFW4
BDFW3
BDFW2
BDFW1
BDFW0
BA3W2
BA3W1
BA3W0
BA2W2
BA2W1
BA2W0
BA1W4
BA1W3
BA1W2
BA1W1
BA1W0
BA0W4
BA0W3
BA0W2
BA0W1
BA0W0
Reserved bit. Read zero; write zero future compatibility
Figure 4-5. Control Register (BCR)
Area Change
Table 4-7, 4-20
Change Description
change contents following:
Reserved. Write future compatibility.
Area Change
Table 4-7, 4-20 4-21
Change Description
bits 20-0, change contents following:
More Information This Product, www.freescale.com
Control Register (BCR) Layout Definition
20-16
BDFW[4-0]
11111 Default Area Wait State Control wait states) Defines number wait states (one through inserted into each external access area that defined registers. access type this area SRAM only. These bits should programmed zero since SRAM memory access requires least wait state. When three through seven wait states selected, additional wait state inserted access. When selecting eight more wait states, additional wait states inserted access. These trailing wait states increase data hold time memory release time increase memory access time.
15-13
BA3W[2-0]
Freescale Semiconductor, Inc.
wait states)
Area Wait State Control Defines number wait states (1-7) inserted each external SRAM access Area Area area defined AAR3. Note: program value these bits zero since SRAM memory access requires least wait state.
When three through seven wait states selected, additional wait state inserted access. This trailing wait state increases data hold time memory release time does increase memory access time. 12-10 BA2W[2-0] wait states) Area Wait State Control Defines number wait states (1-7) inserted into each external SRAM access Area Area area defined AAR2. Note: program value these bits zero, since SRAM memory access requires least wait state.
When three through seven wait states selected, additional wait state inserted access. This trailing wait state increases data hold time memory release time does increase memory access time. BA1W[4-0] 11111 Area Wait State Control wait states) Defines number wait states (1-31) inserted into each external SRAM access Area Area area defined AAR1. Note: program value these bits zero, since SRAM memory access requires least wait state.
When three through seven wait states selected, additional wait state inserted access. When selecting eight more wait states, additional wait states inserted access. These trailing wait states increase data hold time memory release time increase memory access time.
More Information This Product, www.freescale.com
GPIO Signal Names
BA0W[4-0]
11111 Area Wait State Control wait states) Defines number wait states (1-31) inserted each external SRAM access Area Area area defined AAR0. Note: program value these bits zero, since SRAM memory access requires least wait state.
When selecting three through seven wait states, additional wait state inserted access. When selecting eight more wait states, additional wait states inserted access. These trailing wait states increase data hold time memory release time increase memory access time.
Freescale Semiconductor, Inc.
GPIO Signal Names
Area Change
Figure 6-2, Figure 6-5, Change HRW. Change RXD, TXD, SCLK, PE0, PE1, RXD, TXD, SCLK, PE0, PE1, PE2, respectively.
Change Description
Address
Area Change
Figure 7-9, 7-16
Change Description
Replace with following figure:
Figure 7-9. Host Data Register (HDR) (X:$FFFFC9)
Receive Register (SRX) Description
Area Change
Section 9.6.4.1, 9-24
Change Description
Change beginning fourth paragraph from Synchronous mode" Asynchronous mode".
Updated Programming Sheets
Table B-1, DSP56321 User's Manual, change Timers rows following:
Timers Figure B-20, Timer Prescaler Load Register (TPLR) Figure B-21, Timer Control/Status Register (TCSR) Figure B-22, Timer Load, Compare, Count Registers (TLR, TCPR, TCR) B-32 B-33 B-34
following examples replace Figure B-14), Figure B-19), Figure B-20), Figure B-22 B34).
More Information This Product, www.freescale.com
Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Central Processor
Asynchronous Arbitration Enable, Synchronization disabled Synchronization enabled Address Attribute Priority Disable, Priority mechanism enabled Priority mechanism disabled Stack Extension Select, Mapped memory Mapped memory Stack Extension Underflow Flag, stack underflow Stack underflow Stack Extension Overflow Flag, stack overflow Stack overflow Stack Extension Wrap Flag, stack extension wrap Stack extension wrap (sticky bit) Stack Extension Enable, Stack extension disabled Stack extension enabled Memory Switch Configuration, Bits 22-21, Refer memory configurations Chapter Chip Operating Mode, Bits Refer operating modes table Chapter External Disable, Enables external Disables external Stop Delay Mode, Delay 128K clock cycles Delay clock cycless Core-DMA Priority, Bits CPD[1:0] Description Compare SR[CP] active channel priority higher priority than core same priority core lower priority than core Cache Burst Mode Enable, Burst Mode disabled Burst Mode enabled Synchronize Select, synchronized Synchronized Release Timing, Fast Release mode Slow Release mode
Freescale Semiconductor, Inc.
Bits 22-21
MSW2 MSW1
CPD1 CPD0 MSW0
Operating Mode Register Reset $00030X; latched from mode pins reset
Reserved, Program
Figure B-2. Operating Mode Register (OMR)
More Information This Product, www.freescale.com
Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Interface Unit
NOTE: bits read/write control bits.
Freescale Semiconductor, Inc.
Request Hold, asserted only attempted pending access always asserted
Default Area Wait Control, Bits 20-16 Area Wait Control, Bits 15-13 Area Wait Control, Bits 12-10 Area Wait Control, Bits Area Wait Control, Bits These read/write control bits define number wait states inserted into each external SRAM access designated area. value these bits should programmed zero.
Bits Name BDFW[4-0] BA3W[2-0] BA2W[2-0] BA1W[4-0] BA0W[4-0] Wait States 0-31 0-31 0-31
State, master master
20-16 15-13 12-10
BA0W[4-0]
BDFW[4-0]
BA3W[2-0]
BA2W[2-0]
BA1W[4-0]
Control Register (BCR) Reset $1FFFFF
X:$FFFFFB Read/Write
Reserved, Program
Figure B-7. Control Register (BCR)
More Information This Product, www.freescale.com
Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Interface Unit
Packing Enable, Disable internal packing/unpacking logic Enable internal packing/unpacking logic Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses
Freescale Semiconductor, Inc.
Address Compare, Bits 23-12 BAC[11-0] address compare external address order decide whether assert Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses Program Memory Enable, Disable logic during external program space accesses Enable logic during external program space accesses Address Attribute Polarity, signal active signal active high Access Type, Bits
BAT[1-0] Encoding Reserved SRAM access Reserved Reserved
Number Address Bits Compare, Bits 11-8 BNC[3-0] number bits (from bits) that compared external address (Combinations BNC[3-0] 1111, 1110, 1101 reserved.)
BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BPAC
BYEN BXEN BPEN BAAP BAT1 BAT0
Address Attribute Registers (AAR3) Address Attribute Registers (AAR2) Address Attribute Registers (AAR1) Address Attribute Registers (AAR0) Reset $000000
X:$FFFFF6 Read/Write X:$FFFFF7 Read/Write X:$FFFFF8 Read/Write X:$FFFFF9 Read/Write
Reserved, Program Figure B-8. Address Attribute Registers (AAR[3-0])
More Information This Product, www.freescale.com
Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Timers
Timer Reload Value
Freescale Semiconductor, Inc.
Timer Load Register (TLR[0-2]) Reset $xxxxxx, value indeterminate after reset
TLR0-X:$FFFF8E Write Only TLR1-X:$FFFF8A Write Only TLR2-X:$FFFF86 Write Only
Value Compared Counter Value
Timer Compare Register (TCPR[0-2]) Reset $xxxxxx, value indeterminate after reset
TCPR0-X:$FFFF8D Read/Write TCPR1-X:$FFFF89 Read/Write TCPR2-X:$FFFF85 Read/Write
Timer Count Value
Timer Count Register (TCR[0-2]) Reset $000000
TCR0-X:$FFFF8C Read Only TCR1-X:$FFFF88 Read Only TCR2-X:$FFFF84 Read Only
Figure B-22. Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
More Information This Product, www.freescale.com
Updated Programming Sheets
Freescale Semiconductor, Inc.
More Information This Product, www.freescale.com
Updated Programming Sheets
Freescale Semiconductor, Inc.
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
REACH
EUROPE Locations Listed: Motorola Literature Distribution P.O. 5405 Denver, Colorado 80217 1-800-521-6274 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre King Street Industrial Estate, N.T., Hong Kong 852-26668334 HOME PAGE:
Information this document provided solely enable system software implementers Motorola products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters that provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part.
MOTOROLA Stylized Logo registered U.S. Patent Trademark Office.EOnCE digital trademarks Motorola, Inc. other product service names property their respective owners. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Motorola, Inc. 2001, 2003
DSP56321RMAD/D, REV.
More Information This Product, www.freescale.com
Other recent searches
ZFSC-8375 - ZFSC-8375 ZFSC-8375 Datasheet
S2L1 - S2L1 S2L1 Datasheet
REJ03B0102-0100 - REJ03B0102-0100 REJ03B0102-0100 Datasheet
MJE18206 - MJE18206 MJE18206 Datasheet
LXE18300X - LXE18300X LXE18300X Datasheet
EDS1232AATA - EDS1232AATA EDS1232AATA Datasheet
CPH3438 - CPH3438 CPH3438 Datasheet
CDP1879 - CDP1879 CDP1879 Datasheet
CDP1879C1 - CDP1879C1 CDP1879C1 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
