MPC86XADS Version-A January 2003 MPC86XADS User's Manual
|
|
|
Top Searches for this datasheet
User's Manual
MPC86XADS Version-A January 2003
MPC86XADS
User's Manual
Motorola, Inc., 2003
More Information This Product, www.freescale.com
Important Notice Users While every effort been made ensure accuracy information this document, Motorola assumes liability party loss damage caused errors omissions statements kind this document, updates, supplements, special editions, whether such errors omissions statements resulting from negligence, accident, other cause. Motorola further assumes liability arising application information, product, system described herein: liability incidental consequential damages arising from this document. Motorola disclaims warranties regarding information contained herein, whether expressed, implied, statutory, including implied warranties merchantability fitness particular purpose. Motorola makes representation that interconnection products manner described herein will infringe existing future patent rights, descriptions contained herein imply granting license make, sell equipment constructed accordance with this description.
Trademarks This document includes these trademarks: Motorola Motorola logo registered trademarks Motorola, Inc. Windows registered trademark Microsoft Corporation U.S. other countries. Intel registered trademark Intel Corporation. Motorola, Inc., Equal Opportunity Affirmative Action Employer.
electronic copy this book, visit Motorola's site http://e-www.motorola.com/ Motorola, Inc., 2002; Rights Reserved
More Information This Product, www.freescale.com
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
CHAPTER General Information Introduction MPC86x Family Support Abbreviations' List Related Documentation SPECIFICATIONS MPC86xADS Features MPC86xADS Goals CHAPTER Hardware Preparation Installation INTRODUCTION UNPACKING INSTRUCTIONS HARDWARE PREPARATION MPCs' Replacing .ADI Port Address Selection. Clock Source Selection VDDL Source Selection (J3) Debug Mode Indication Source Selection AMode Split, mux, single multy Fast-Ethernet source Control, Expansion connector. RS232 SMC2 enable operating single phy. (J4) INSTALLATION INSTRUCTIONS Host Controlled Operation Stand Alone Operation Debug Port Power Supply Connection P21: +12V Power Supply Connection Installation Host computer MPC86xADS Connection Debug Port Connector. Terminal MPC86xADS RS-232 Connection Memory Installation CHAPTER OPERATING INSTRUCTIONS INTRODUCTION CONTROLS INDICATORS ABORT Switch SOFT RESET Switch HARD RESET Switches Software Options Switch AFast-Ethernet configuration. Bridges Ethernet 10Base-T. LD21 LD20 RS232 Port LD19 RS232 Port LD22 Ethernet Indicator Ethernet Indicator
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Ethernet JABB Indicator Ethernet CLSN Indicator Ethernet Indicator Ethernet Indicator Indicator LD13 Indicator LD23 FLASH LD17 DRAM LD15 SDRAM LD14 PCMCIA LD17 Fast-Ethernet Full Duplex Fast-Ethernet Link Activity LD10 Fast-Ethernet Collision LD11 Fast-Ethernet Link speed LD12 ATM25Mhz RX-LED ATM25Mhz TX-LED MEMORY Registers' Programming Memory Controller Registers Programming CHAPTER Functional Description Reset Reset Configuration Regular Power Reset Manual Soft Reset Manual Hard Reset Internal Sources Reset Configuration Local Interrupter Clock Generator Buffering Chip Select Generator DRAM DRAM Operation DRAM Performance Figures Refresh Control Variable Bus-Width Control Flash Memory SIMM Synchronous Dram SDRAM Programming SDRAM Initializing Procedure SDRAM Refresh .Communication Ports Ethernet Port Infra-Red Port Infra-Red Port Rate Range Selection RS232 Ports RS-232 Ports' Signal Description
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Utopia Operation Interface ATM25 ATM155 Serial A(Over E1/T1) Fast Ethernet. PCMCIA Port PCMCIA Power Control Board Control Status Register BCSR BCSR Disable Protection Logic BCSR0 Hard Reset Configuration Register BCSR1 Board Control Register BCSR2 Board Control Status Register BCSR3 Board Control Status Register BCSR4 Board Control Status Register BCSR5 Board Control Status Register Debug Port Controller MPC86xADS Debug Port Controller Target System Debug Port Connection Target System Requirements Debug Port Control Status Register Standard MPCXXX Debug Port Connector Description VFLS(0:1) HRESET* SRESET* DSDI Debug-port Serial Data DSCK Debug-port Serial Clock DSDO Debug-port Serial Data Power 3.3V CHAPTER Support Information Interconnect Signals 10BaseT Ethernet Port Connector PA2, RS232 Ports' Connectors T1/E1 RJ45 Connector. ATM25 RJ45 Connector. ATM155 multymode optical connector. Port Connector MPC86XADS's Serial Ports' Expansion Connector P11, P14, P16, Mictor, Logic Analyser connectors. External Debug Port Controller Input Interconnect. 100BaseT Ethernet Port Connector Power Connector Power Connector P13A Power Jack connector 2.1mm. Mach's System Programming (ISP)
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
connector populated. JTAG connector Altera programing. Expansion Connector ADD, Data control PCMCIA Port. PCMCIA Port Connector MPC86xADS Part List APPENDIX Schematics. 1-20. APPENDIX Programmable Logic Equations Debug Port Controller .129 Board Control Status Register .149 BCSR5 Fast-Ethernet Control Logic. .187 Block called nux_862/6 .188 APPENDIX Signal description APPENDIX Installation
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
TABLE 1-1. MPC86xADS Specifications TABLE 2-1. Address Selection TABLE 2-2. Fast-Ethernet configuration. TABLE 3-1. Fast-Ethernet configuration. TABLE 3-2. Memory MP86xADS Mode, TABLE 3-3. Memory Compatible Mode TABLE 3-4. REGISTERS' PROGRAMMING TABLE 3-5. Memory Controller Initializations 50Mhz with DRAM-EDO TABLE 3-6. Memory Controller Initializations 50Mhz with DRAM-EDO TABLE 3-7. UPMA Initializations 60nsec DRAMs 50MHz TABLE 3-8. UPMA Initializations 60nsec DRAMs 50MHz TABLE 3-9. Memory Controller Initializations 20Mhz TABLE 3-10. UPMA Initializations 60nsec DRAMs 20MHz TABLE 3-11. UPMB Initializations KS643232C-TC60 upto 32MHz TABLE 3-12. UPMB Initializations KS643232C-TC60, 32+MHz 50MHz TABLE 4-1. MPC86xADS Chip Selects' Assignment TABLE 4-2. Regular DRAM Performance Figures TABLE 4-3. DRAM Performance Figures TABLE 4-4. DRAM ADDRESS CONNECTIONS TABLE 4-5. Flash Memory Performance Figures TABLE 4-6. SDRAM refer MPC8xx Pins TABLE 4-7. SDRAM Connected TABLE 4-8. Estimated SDRAM Performance Figures TABLE 4-9. SDRAM's Mode Register Programming TABLE 4-10. BCSR0 Description TABLE 4-11. BCSR1 Description TABLE 4-12. PCCVCC(0:1) Encoding TABLE 4-13. PCCVPP(0:1) Encoding TABLE 4-14. BCSR2 Description TABLE 4-15. Flash Presence Detect (4:1) Encoding TABLE 4-16. DRAM Presence Detect (2:1) Encoding TABLE 4-17. DRAM Presence Detect (4:3) Encoding TABLE 4-18. BCSR3 Description TABLE 4-19. FLASH Presence Detect (7:5) Encoding TABLE 4-20. BCSR4 Description TABLE 4-21. BCSR5 Description TABLE 4-22. Debug Port Control Status Register TABLE 4-23. DSCK Frequency Select TABLE 4-24. Off-board Application Maximum Current Consumption TABLE 5-1. Ethernet Port Interconnect Signals TABLE 5-2. PA2, Interconnect Signals TABLE 5-3. T1/E1 RJ45 Connector. TABLE 5-4. ATM25 RJ45 Connector. TABLE 5-5. Port Interconnect Signals TABLE 5-6. MPC86XADS's Interconnect Signals TABLE 5-7. Interconnect Signals
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
TABLE 5-8. TABLE 5-9. TABLE 5-10. TABLE 5-11. TABLE 5-12. TABLE 5-13. TABLE 5-14. TABLE 5-15. TABLE 5-16. TABLE 5-17. TABLE 5-18. TABLE 5-19. TABLE 5-20. TABLE 5-21. Interconnect Signals Interconnect Signals Interconnect Signals Interconnect Signals Interconnect Signals Interconnect Signals Ethernet Port Interconnect Signals Interconnect Signals Interconnect Signals Connector Interconnect Signals JTAG connector Altera programing. MPC86XADS's Interconnect Signals PCMCIA Connector Interconnect Signals MPC86xADS Part List
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE 2-10 FIGURE 2-11 FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE 4-10 APPENDIX APPENDIX MPC86xADS Block Diagram MPC86xADS Side Part Location diagram VIEW Configuration Dip-Switch VFLS Selection. SMC2 Multyphy Host Controlled Operation Scheme Stand Alone Configuration P13: Power Connector P12: +12V Power Connector Port Connector Connectoe. connector connected board PA7, RS-232 Serial Port Connectors Memory SIMM Installation Description Refresh Scheme DRAM Address Lines' Switching Scheme Flash Memory SIMM Architecture SDRAM Connection Scheme RS232 Serial Ports' Connector UTOPIA Buses interfaces control PCMCIA Port Configuration Debug Port Controller Block Diagram Standard Debug Port Connector MPC86xADS Power Scheme Port Connector .195 Physical Location jumper .198 Configuration Options .198 board SBus .199
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
General Information
General Information
Introduction
This document operation guide MPC86xADS board. contain following parts: XPC855T MPC855T, XPC857T MPC857T, XPC8860X MPC860X, XPC862X MPC862X, XPC866X MPC866X. contains operational, functional general information about ADS. MPC86xADS meant serve platform development around MPC86X family processors. Using on-board resources associated debugger, developer able download code, breakpoints, display memory registers connect proprietary expansion connectors, incorporated desired system with MPC86x processor. This board compatible with MPC8xxFADS point view. This board could also used demonstration tool, i.e., application burnedA into flash memory exhibitions etc.`.
MPC86x Family Support
MPC86xADS supports following MPC8xx family members: XPC855T MPC855T XPC857T MPC857T XPC8860DE MPC860DE XPC860DP MPC860DP XPC860EN MPC860EN XPC860P MPC860P XPC860SR MPC860SR XPC860T MPC860T XPC862DT MPC862DT XPC862SR MPC862SR XPC862T MPC862T XPC859X MPC859X XPC866X MPC866X
Either off-board.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
General Information
Abbreviations' List
MPC86xADS, subject this document. User Programmable Machine GPCM General Purpose Chip-select Machine General Purpose Line (associated with UPM) Infra-Red BCSR Board Control Status Register. Zero Input Force Ball Grid Array SIMM Single In-line Memory Module
Related Documentation
MPC86x User's Manuals. Board Specification.
phy. 10/100BaseT 80225 phy. Infineon E1/T1 PEB2256 Framer. A155Mhz uPD98404 A25Mhz IDT77V107
Motorola 10BaseT MC68160
SPECIFICATIONS
TABLE 1-1. MPC86xADS Specifications
CHARACTERISTICS SPECIFICATIONS +5Vdc (typical), (maximum) +12Vdc @1A. MPC86x running upto Speed GigaBytes MByte, bits wide expandable MBytes MByte, bits wide SIMM, Optional Support MByte, SIMM MBytes, SDRAM. 30OC -25OC 85OC (non-condensing) 9.173" (233 6.3" (160 0.063" (1.6
MPC86xADS specifications given TABLE 1-1.
Power requirements other boards attached) Microprocessor Addressing Total address range: Flash Memory Dynamic optional populated. Synchronous DRAM Operating temperature Storage temperature Relative humidity Dimensions: Length Width Thickness
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
General Information
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
General Information
MPC86xADS Features
Compatible with MPC86xADS Board. MPC862/866, running upto frequency, mounted socket. MByte, Unbuffered, Synchronous Dram On-Board. MByte 60nsec delay DRAM SIMM. Support MByte Dram SIMM, with Automatic Dram SIMM identification. Data-Bus Width Support. DRAM will populated board. optional. MByte Flash SIMM. Support upto MByte, Programmable, with Automatic Flash SIMM identification. change 8MByte. Dual RS232 port with Low-Power Option each port. T1/E1 connected TDMB using infineon PEB2256 framer serial just T1/E1. Fast Ethernet connected PCMCIA port Port-D using LSI-Logic 80225.
AMode operate Utopia Split also work multy singe phy.
ATM25 connected PCMCIA Port Port-D split mode, only Port-D mode using IDT77V106. ATM155 connected PCMCIA Port Port-D split mode, only Port-D mode using uPD98404 device. Memory Disable Option each local memory slaves. Board Control Status Register BCSR, Controlling Board's Operation. Programmable Hard-Reset Configuration BCSR. only PCMCIA Socket With Full Buffering, Power Control Port Disable Option. Complies with PCMCIA 2.1+ Standard. Module Enable Indications. 10-Base-T Port On-Board, with Stand-By Mode. IrDA (4MBps) Port with Stand-By Mode. Dual RS232 port with Low-Power Option each port. Board Debug Port Controller also I/F. MPC86xADS Serving Debug Station Target System option. Optional Hard-Reset Configuration Burned FlashA. External Tools' Identification Capability, BCSR.
Available only supported also MPC86x.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
General Information
Expansion connectors includes ports signals order control external peripherals. Soft HardA Reset Push Button ABORT Push Button SingleB Supply. Reverse Over Voltage Protection Power Inputs. 3.3V VDDL/VDDH older version then MPC866. 1.8V VDDL 3.3V HDDH MPC866, done jumper. Power Indications Each Power Bus. External switches selections Fast Ethernet options MPC86x.
Hard reset applied depressing BOTH Soft Reset ABORT buttons. Unless supply required PCMCIA card programmable Flash SIMM.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
General Information
FIGURE MPC86xADS Block Diagram
Logic Analyser Connectors
ADD/DATA
Reset, Clocks Interrupts MPC862/866
VDDL Power
SDRAM MBytes
Debug Port Connector Debug Port Controller (ADI I/F) IrDA
3.3V 1.8V
Buffered ADD/DATA
FLASH Upto 8MByte
Populated
10BaseT Ethernet
PORTS
Control
BCSR
RS232 PORT2
Expansion Connectors Expansion Connectors
BCSR Control
PCMCIA Control Buffering
E1/T1 Framer Fast Ethernet
Switch Logic
Ports
Data/ADD
Utopia
ATM25
Data/ADD
Utopia
ATM155
MPC86xADS Goals
MPC86xADS meant become general platform development around MPC86x family. Using on-board resources associated debugger, developer able load code, breakpoints, display memory registers connect proprietary expansion connectors, incorporated system with MPC. This board could also used demonstration tool, i.e., application programmedA into flash memory exhibitions etc.
More Information This Product, www.freescale.com
Release
ATM155M ATM25M PORT E1/T1 PORP PORT-Optic RJ45 RJ45
PCMCIA PORT
RS232 PORT1
DRAM Upto Mbyte
ETHERNET 10BaseT PORT
Fast Ethernet PORT RJ45
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
Hardware Preparation Installation
INTRODUCTION
This chapter provides unpacking instructions, hardware preparation, installation instructions MPC86xADS.
UNPACKING INSTRUCTIONS
NOTE shipping carton damaged upon receipt, request carrier's agent present during unpacking inspection equipment.
Unpack equipment from shipping carton. Refer packing list verify that items present. Save packing material storing reshipping equipment.
CAUTION AVOID TOUCHING AREAS INTEGRATED CIRCUITRY; STATIC DISCHARGE DAMAGE CIRCUITS.
HARDWARE PREPARATION
select desired configuration ensure proper operation MPC86xADS board, changes Dip-Switch settings jumpers required before installation. location switches, LEDs, DipSwitches, jumpers connectors illustrated FIGURE 1-2. board been factory tested shipped with Switch settings described following paragraphs. Parameters changed following conditions: port address Clock Source Internal Logic Supply Source Debug Mode Indication Source AMode Split, mux, single multy phy. Fast Ethenet source Port, PortD/PCMCIA-Port. PCMCIA Enable. port connected Expansion Connector. RS232 Port-(1) SMC2 enable with conjunction with Asingle phy.
Either off-board.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
FIGURE MPC86xADS Side Part Location diagram
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
MPCs' Replacing
Before replacing user should turn power. When replacing with another should noticed where MPCs' pin. same direction one. MPC866 thickness 2.5mm while other MPC86x thickness 1.7mm. board socket with clamshell inorder that socket will both devices board been supplied with spacer between socket cover (shell) device. MPC86x that MPC866 spacer between device socket cover.
FIGURE
VIEW
Port Address Selection
MPC86xADS have eight possible slave addresses port, enabling eight MPC86xADS boards connected same board host computer. selection slave address done setting switches Dip-Switch SW1. Switch stands mostsignificant address switch stands least-significant bit. switch 'ON' state, stands logical'1'. FIGURE shown configured address'0'.
FIGURE Configuration Dip-Switch
ADR2 ADR1 ADR0 Generator EXTCLK TABLE 2-1. describes switch settings each slave address: ADR2 ADR1 ADR0 32.678 Crystal Resonator
TABLE 2-1. Address Selection
ADDRESS Switch Switch Switch
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
TABLE 2-1. Address Selection
ADDRESS Switch Switch Switch
Clock Source Selection
Switch selects clock source MPC. When the'ON' position while powered-up, on-board 32.768 crystal resonator becomes clock source multiplication factor becomes 1:513. When switch the'OFF' position while powered-up, on-board 4MHz clock generator becomes clock source while multiplication factor becomes 1:5. Note: device other then MPC866, should 'ON'
VDDL Source Selection (J3)
This board MPC866 derivative MPC862 derivative. MPC866 VDDL should 1.8V connect pins 1-2. MPC862 derivative VDDL should 3.3V. connect pins 2-3.
Debug Mode Indication Source Selection
Jumper selects between VFLS(0:1) signals signal indication debug mode state. Since with MPC86xs, each these signals alternate function, necessary switch between sources, favor alternate function being used. When jumper positioned between pins VFLS(0:1) selected towards debug-port controller. When jumper placed between positions J1(2) signal selected.
FIGURE VFLS Selection
VFLS(0:1) Selected
Selected
AMode Split, mux, single multy Fast-Ethernet source Control, Expansion connector.
According SW3(2,3,4) user select Fast-Ethernet Asource function. table
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
bellow show configuration options.
TABLE 2-2. Fast-Ethernet configuration.
Switch Switch Switch Define Fast-Ethernet Fast-Ethernet PORT-D Expansion Connector Expansion Connector AMUX AMUX PORTPCMCIA Expansion Connector Define PCMCIA ASPLIT Expansion Connector PCMCIA Expansion Connector
Note: Inorder work single user should config unused address wanted different address, ATM25 config address address 0x2000008, ATM155 address register 0x2000129. Then drive RxAdd(1)-PB17 RxAdd(0)-PB16 TxAdd(1)-PB21 TxAdd(0)-PB20 wanted address, driving them constantly.
RS232 SMC2 enable operating single phy. (J4)
Jumper selects between Amulty enable RS232 port Pins PB21 PB20 have multiple functions RS232-1 ATXADD1 TXADD0 board. allow work with Asingle SMC2 board this ability too. connect between drive address pins Aphy's 0b00011 user work with single phy, select which writing address register this address. connect allow operation with multy phy, RS232 SMC2 should enable appropriate BCSR register. Note: AADD that used board only RXADD0, RXADD1, TXADD0 TXADD1.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
FIGURE SMC2 Multyphy.
SMC2 Selected
Multyphy Selected
INSTALLATION INSTRUCTIONS
Because board shipped with DRAM around base that there DRAM user should change BR2, BR3, valid should (bit 0x000000C1 should 0xFC800a00, this configuration will SDRAM 0x3000000 8MByte. When MPC86xADS been configured desired user, installed according required working environment follows: Host Controlled Operation Debug Port. Stand-Alone
Host Controlled Operation
this configuration MPC86xADS controlled host computer through debug port. This configuration allows extensive debugging using on-host debugger.
FIGURE Host Controlled Operation Scheme
Wire Flat Cable
paralel port
Host Computer
Power Supply
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
Stand Alone Operation
this mode, controlled host ADI/Debug port. connect host other ports, e.g., RS232 port, port, Ethernet port, etc.`. Operating this mode requires application program programmed into board`s Flash memory (while with host controlled operation, memory required all).
Debug Port.
this mode operation user control board through external tool connected computer parallel port. board work work host mode controlled debug pins through connector.
FIGURE Stand Alone Configuration
Host Computer
Power Supply
Power Supply Connection
MPC86xADS requires max, power supply operation. Connect power supply connector P13A shown below:
FIGURE P13: Power Connector
terminal block power connector with power plug. plug designed accept wires. recommended wires. provide solid ground, terminals supplied. recommended connect both wires common power supply, while connected with single wire.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
P13A Connector that should with power supply which supplied with board box. Plug power supply P13A. NOTE Since hardware applications connected MPC86xADS Expansion connectors' P21, power consumption should taken into consideration when power supply connected MPC86xADS. other words when adding into expansion connectors remember that additional will have more power consumption then
P21: +12V Power Supply Connection
MPC86xADS requires max, power supply PCMCIA channel Flash programming capability programmable Flash SIMM. MPC86xADS work properly without +12V power supply, there need program either programmable PCMCIA flash card programmable Flash SIMM. Connect +12V power supply connector shown below:
FIGURE P12: +12V Power Connector
+12V
terminal block power connector with power plug. plug designed accept wires. recommended wires.
Installation Host computer MPC86xADS Connection
installation various host computers, refer APPENDIX MPC86xADS interface connector, pin, male, type connector. connection between MPC86xADS host computer line flat cable, supplied with board. Connector. FIGURE below shows configuration connector.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
FIGURE Port Connector
N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ D_C~ HST_ACK ADS_SRESET ADS_HRESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK N.C. N.C. N.C. N.C.
NOTE: connected power supply, used MPC86xADS.
Debug Port Connector.
Through this connector user control board like done from connector. Today most control this connector through command converter that connected from other side parallel port.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
FIGURE Connectoe. Vfls0 Hreset V3.3 Sreset Dsck Vfls1 Dsdi Dsdo
FIGURE connector connected board
Computer
paralel port
Vfls0 Hreset V3.3
MPC86xADS
Sreset Dsck Vfls1 Dsdi Dsdo
Terminal MPC86xADS RS-232 Connection
serial (RS232) terminal other RS232 equipment, connected RS-232 connectors P2B. RS-232 connectors pin, female, Stacked D-type connector shown FIGURE 2-10. connectors arranged manner that allows connection with serial port Personal Computer. flat cable.
FIGURE 2-10 PA7, RS-232 Serial Port Connectors
N.C.
NOTE: line (pin connected MPC86xADS.
Memory Installation
Dynamic Memory SIMM, will populated only socket will soldered. Flash Memory SIMM.
MPC86xADS types memory SIMM:
install memory SIMM, should taken package, diagonally socket error made here, since Flash socket contacts, while DRAM socket then twisted vertical position until metal lock clips locked. FIGURE 2-11 "Memory SIMM Installation" below.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Hardware Preparation Installation
CAUTION
memory SIMMs have alignment nibble near their pin. important align memory correctly before twisted, otherwise damage might inflicted both memory SIMM socket.
FIGURE 2-11 Memory SIMM Installation
Memory SIMM
Metal Lock Clip
SIMM Socket
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
OPERATING INSTRUCTIONS
INTRODUCTION
This chapter provides necessary information MPC86xADS host-controlled stand-alone configurations. This includes controls indicators, memory details, software initialization board.
CONTROLS INDICATORS
ABORT Switch
MPC86xADS following switches indicators. ABORT switch normally used abort program execution, this issuing level interrupt MPC. stand alone mode, responsibility user provide means handling interrupt, since there resident debugger with MPC86xADS. ABORT switch signal debouncing, disabled software.
SOFT RESET Switch
SOFT RESET switch performs Soft reset internal modules, maintaining MPC's configuration (clocks chip-selects) Dram SDram contents. switch signal debouncing, possible disable software. Soft Reset Sequence, Soft Reset Configuration sampled becomes valid.
HARD RESET Switches
When BOTH switches depressed simultaneously, HARD reset generated MPC. When HARD reset, configuration lost, including data stored DRAM SDRAM re-initialized. Hard Reset sequence, Hard Reset Configuration stored BCSR0 becomes valid.
Software Options Switch
SW7is 4-switches Dip-Switch. This switch connected over EXTOLI(0:3) lines which available BCSR, options manually selected, according state.
FIGURE Description
EXTOLI0 Pulled EXTOLI1 Pulled EXTOLI2 Pulled EXTOLI3 Pulled EXTOLI0 Driven EXTOLI1 Driven EXTOLI2 Driven EXTOLI3 Driven
AFast-Ethernet configuration.
Table desires configuring board order MPC866/862 operation. user know MPC86x configure Aor/and Fast ethernet (MPC866 MPC862 both Aand Fast Ethernet) board configure many options over portD PCMCIA Port like AMux, ASplit, Single multy Fast ethernet connect external through
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
Expansion Connectors. (2,3,4) select these options. Note: Before changing position SW3(2,3,4) user should turn power. When switches option(0) position user PCMCIA Ports through Expansion Connectors. Option(2,3) select ATM-Mux through Port-D PCMCIA through PCMCIA Port. Option(4), select Asplit. options(6,7) select PortD PCMCIA PCMCIA Expansion Connector. NOTE: case board with PHYs ATM25 A155, selection Single Multy user should configure following Pins outputs, drive Port-B(16,17 ARx-Add) Port-B(19,20, ATX-ADD) wanted address like internal default address wanted phys. other left default address. TABLE 3-1. Fast-Ethernet configuration.
Option#
Switch
Switch
Switch
PORT-D Expansion Connector Expansion Connector AMUX AMUX
PORT-PCMCIA Expansion Connector Define PCMCIA Fast-Ethernet ASPLIT
Define Fast-Ethernet Fast-Ethernet
Expansion Connector PCMCIA Expansion Connector
Bridges
There bridges MPC86xADS. They meant assist general measurements logicanalyzer connection.
Warning
When connecting bridge, only INSULATED clips. Failure doing might result permanent damage MPC86xADS.
Ethernet 10Base-T. LD21
When yellow lit, indicates that ethernet port transceiver MC68160 EEST, active. When dark, indicates that EEST power down mode, enabling associated pins off-board expansion connectors.
LD20
When yellow lit, indicates that Infra-Red transceiver TFDS6000, active enables communication that medium. When dark, transceiver shutdown mode, enabling associated pins off-board expansion connectors.
RS232 Port LD19
When yellow RS232 Port lit, designates, that RS232 transceiver connected PA2, active communication that medium allowed. When darkened, designates that transceiver
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
shutdown mode, associated pins used off-board expansion connectors.
RS232 Port LD22
When yellow RS232 Port lit, designates that RS232 transceiver connected PB2, active communication that medium allowed. When darkened, designates, that transceiver shutdown mode, associated pins used off-board expansion connectors.
Ethernet Indicator
green Ethernet Receive indicator blinks whenever EEST receiving data from Ethernet port.
Ethernet Indicator
green Ethernet Receive indicator blinks whenever EEST transmitting data Ethernet port.
Ethernet JABB Indicator
Ethernet Jabber indicator JABB, lights whenever jabber condition detected ethernet port.
Ethernet CLSN Indicator
Ethernet Collision indicator CLSN, blinks whenever collision condition detected ethernet port, i.e., simultaneous receive transmit.
Ethernet Indicator
Ethernet Polarity indicator PLR, lights whenever wires connected receiver input ethernet port reversed. EEST, remains while EEST automatically corrected reversed wires.
Ethernet Indicator
yellow Ethernet Twisted Pair Link Integrity indicator LIL, lights indicate good link integrity port. when link integrity fails.
Indicator LD13 Indicator LD23
yellow led, indicates presence supply P13.
When green LD23 lit, indicates that debug mode, i.e., VFLS0 VFLS1 which ever selected J1).
FLASH LD17
When yellow FLASH lit, indicates that FLASH SIMM enabled BCSR1 register. I.e., access done CS0~ address space will flash memory. When dark, flash disabled CS0~ used off-board expansion connectors.
DRAM LD15
When yellow DRAM lit, indicates DRAM SIMM enabled BCSR1. Therefore, access made CS2~ CS3~) will DRAM. When dark, indicates that either DRAM disabled BCSR1, enabling CS2~ CS3~ off-board expansion connectors.
SDRAM LD14
When yellow SDRAM lit, indicates SDRAM enabled BCSR1. Therefore, access made CS4~ (will SDRAM. When dark, indicates that either SDRAM disabled BCSR1, enabling CS4~ off-board expansion connectors.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
PCMCIA LD17
Address strobe buffers driven towards PCMCIA card Data buffers driven from PCMCIA card whenever CE1A~ CE2A~ signals asserted. Card status lines driven towards from PCMCIA card.
When yellow PCMCIA lit, indicates following:
When dark, indicates that above buffers tri-stated pins associated with PCMCIA channel used off-board expansion connectors.
Fast-Ethernet Full Duplex Fast-Ethernet Link Activity LD10 Fast-Ethernet Collision LD11 Fast-Ethernet Link speed LD12 ATM25Mhz RX-LED ATM25Mhz TX-LED
function this indicate Full Duplex Detect.
function this indicate occurrence Link Activity.
function this indicate Full Duplex Detect.
function this indicate Full Duplex Detect. This indicates when light that there receive ATM25 twisted pair lines.
This indicates when light that there transmit ATM25 twisted pair lines.
MEMORY
accesses MPC86xADS's memory slaves controlled MPC's memory controller. Therefore, memory programmable desire user. After Hard Reset performed debug station, debugger checks existence, size, delay type DRAM FLASH memory SIMMs mounted board initializes chip-selects accordingly. SDRAM, DRAM FLASH memory respond types memory access i.e., user supervisory, program data DMA. following paragraph there description memory options: Compatible Mode MPC86xADS Mode. Compatible Mode using DRAM 8MByte SDRAM. this Mode programmable registers remain same, (all memory same MPC8xxFADS board) except Mask register bits, that will changed according SDRAM size 0xFF80. MPC86xADS Mode where DRAM used. this case SDRAM will mapped differently, TABLE 3-2. "Memory MP86xADS Mode," page TABLE 3-3. "Memory Compatible Mode" page following programmable changes should made order work board MPC86xADS Mode: Programming Base Address bits DRAM should valid (L-bit should cleared). Programming Mask Register bits SDRAM should changed according SDRAM size, where bits masked. 8MByte SDRAM, Mask bits 0xFC80 should
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-2. Memory MP86xADS Mode,
ADDESS RANGE 00000000 007FFFFFa Memory Type SDRAM 8MByte Device Type Port Size 02000000 020FFFFF Communicatio ports: CS5, ATM25, ATM155, Framer, BCSR5,6 ATM25 ATM155 T1/E1 Framer, Control register BCSR(0:4)b BCSR0 BCSR1 BCSR2 BCSR3 BCSR4 Empty Space Internal MAPd Empty Space Flash SIMM MCM29F020 MCM29F040 SM732A1000A MCM29F080 SM732A2000 SDRAMa Empty Space (for 8MByte)
02000000 020000FF 02000100 020001FF 02000200 020002FF 02000300 020003FF 02100000 02107FFF 02100000 02107FE3 2100004 02107FE7 2100008 02107FEB 210000C 02107FEF 2100010 02107FF3 02108000 021FFFFF 02200000 02207FFF 02208000 027FFFFF 02800000 029FFFFF 02A00000 02BFFFFF 02C00000 02FFFFFF 03000000 037FFFFF 03400000 FFFFFFFF
0x007F_FFFF, 0x0300_0000 0x037F_FFFF both mapped SDRAM (8MByte). device appears repeatedly multiples size. E.g., BCSR0 appears memory locations 2100000, 2100020, 2100040., while BCSR1 appears 2100004, 2100024, 2100044.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
Only upper (D0-D15) fact used. Refer relevant User's Manual complete description internal memory map.
TABLE 3-3. Memory Compatible Mode
ADDESS RANGE 00000000 003FFFFF 00400000 007FFFFF 00800000 00FFFFFF Memory Type DRAM SIMM MB321Bxa08 Device Type MB322Bxa08 MC324Cxa00 MB328Cxa00 Port Size Comunication ports: CS5, ATM25, ATM155, Framer, BCSR ATM25 ATM155 T1/E1 Framer, Control register BCSR(0:4)b BCSR0 BCSR1 BCSR2 BCSR3 BCSR4 Empty Space Internal MAPd Empty Space Flash SIMM MCM29F020 MCM29F040 SM732A1000A MCM29F080 SM732A2000 SDRAM 8MByte) (for
01000000 01FFFFFF 02000000 020FFFFF
02000000 020000FF 02000100 020001FF 02000200 020002FF 02000300 020003FF 02100000 02107FFF 02100000 02107FE3 2100004 02107FE7 2100008 02107FEB 210000C 02107FEF 2100010 02107FF3 02108000 021FFFFF 02200000 02207FFF 02208000 027FFFFF 02800000 029FFFFF 02A00000 02BFFFFF 02C00000 02FFFFFF 03000000 037FFFFF 03400000 FFFFFFFF
Empty Space
[B,T]
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
device appears repeatedly multiples size. E.g., BCSR0 appears memory locations 2100000, 2100020, 2100040., while BCSR1 appears 2100004, 2100024, 2100044. Only upper (D0-D15) fact used. Refer relevant User's Manual complete description internal memory map.
Registers' Programming
DRAM Controller SDRAM Controller Chip Select generator. UART terminal host computer connection. Ethernet controller. Infra-Red Port Controller General Purpose signals. Acontroller. T1/E1 (TDM) controller.
provides following functions MPC86xADS:
Fast Ethernet Controller. internal registers must programmed after Hard reset described following paragraphs. addresses programming values hexadecimal base.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
better understanding following initialization refer MPC86x User's Manual more information.
TABLE 3-4. REGISTERS' PROGRAMMING
Register SIUMCR Init Value[hex] 01012440 Description Internal arbitration, External master arbitration priority External arbitration priority PCMCIA channel pins PCMCIA, Debug Port JTAG port pins, FRZ/IRQ6~ FRZ, debug register locked, parity non-CS regions, DP(0:3)/ IRQ(3:6)~ pins DP(0:3), reservation disabled, SPKROUT Tri-stated, BS_A(0:3)~ WE(0:3)~ driven just their dedicated pins, GPL_B5~ enabled, GPL_A/ B(2:3)~ function GPLs. Software watchdog timer count FFFF, Bus-monitor timing Bus-monitor Enabled, watch-dog Freeze, watch-dog disabled, watch-dog enabled) causes NMI, enabled) prescaler. interrupt level, reference match indications cleared, interrupts disabled, freeze, time-base disabled. Interrupt request level 32768 source, second interrupt disabled, Alarm interrupt disabled, Real-time clock FREEZE, Real-time clock enabled. level interrupt request, Periodic interrupt disabled, clear status, interrupt disabled, FREEZE, periodic timer disabled.
SYPCR
FFFFFF88
TBSCR RTCSC PISCR
00C2 00C2 0082
Memory Controller Registers Programming
memory controller MPC86xADS initialized operation. I.e., registers' programming based timing calculation except refresh timer which initialized 16.67Mhz, lowest frequency which wake Since made wake-up 25MHzA well, initialization efficient, since there many wait-states inserted. Therefore, additional initialization provided support efficient 25MHz operation. reason initializing 50Mhz allow proper (although efficient) operation through available clock frequencies.
only parameter which initialized start-up frequency, refresh rate, which would have been inadequate initialized 50Mhz while board running lower frequency. Therefore, best bandwidth availability, refresh rate should adapted current system clock frequency.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
Warning
availability problems with supported memory components, below initialization were tested with parts. Therefore, below initialization liable CHANGE, throughout testing period.
TABLE 3-5. Memory Controller Initialization 50Mhz with DRAM-EDO
Register Device Type Flash supported. MCM29F020-90 MCM29F040-90 SM732A1000A-9 MCM29F080-90 SM732A2000-9 MCM29F020-12 MCM29F040-12 SM732A1000A-12 MCM29F080-12 SM732A2000-12 Dram Supported SIMMs BCSR SIMMs Init Value [hex] 02800001 FFE00D34 FFC00D34 FF800D34 FFE00D44 FFC00D44 FF800D44 02100001 FFFF8110 00000081 FFC00800 FF000800 00400081 01000081 FFC00800 FF000800 Description Base 2800000, port size, parity, GPCM 2MByte block size, types access, early negate, w.s., Timing relax 4MByte block size, types access, early negate, w.s., Timing relax 8MByte block size, types access, early negate, w.s., Timing relax 2MByte block size, types access, early negate, w.s., Timing relax 4MByte block size, types access, early negate, w.s., Timing relax 8MByte block size, types access, early negate, w.s., Timing relax Base 2100000, port size, parity, GPCM KByte block size, types access, early negate, w.s. Base port size, parity, UPMA 4MByte block size, types access, initial address multiplexing according AMA. 16MByte block size, types access, initial address multiplexing according AMA. Base 400000, port size, parity, UPMA Base 1000000, port size, parity, UPMA 4MByte block size, types access, initial address multiplexing according 16MByte block size, types access, initial address multiplexing according AMA.
MCM36100/200-60/70 MCM36400/800-60/70 MT8/16D432/832X-6/7
MCM36200-60/70 MCM36800-60/70 MT16D832X-6/7
MCM36200-60/70 MCM36800-60/70 MT16D832X-6/7
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-5. Memory Controller Initialization 50Mhz with DRAM-EDO
Register Compatibl Mode Compatibl Mode MPC86x Mode K4S643232-TC60 Device Type K4S643232-TC60 Init Value [hex] 030000C1 Description Base 3000000,
FFC00A00
MByte block size, types access, initial address multiplexing according AMB. Base 0x0,
0x000000C1
MPC86x Mode MPTPR MAMR Comm peripheral Comm peripheral Dram Supported SIMMs
0xFC800800
MByte block size, types access, initial address multiplexing according AMB.
0x02000401 0xFFF009A6 0400 40A21114a 60A21114b C0A21114c Divide (decimal) refresh clock divided C0c, periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided 60c, periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided C0c, periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided 60c, periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4enabled, loop read, loop write, beats refresh burst.
MB321BT08TASN60
MB322BT08TASN60
20A21114a 30A21114b 60A21114c
MB324CT00TBSN60
40B21114a 60B21114b C0B21114c
MB328CT00TBSN60
20B21114a 30B21114b 60B21114c
MBMR
KS643232C-TC60
D0802114c 80802114d
Assuming 16.67 BRGCLK. Assuming 25MHz BRGCLK
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
50MHz BRGCLK Assuming 32MHz BRGCLK.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-6. Memory Controller Initialization 50Mhz with DRAM-EDO
Register Device Type Flash supported. MCM29F020-90 MCM29F040-90 SM732A1000A-9 MCM29F080-90 SM732A2000-9 MCM29F020-12 MCM29F040-12 SM732A1000A-12 MCM29F080-12 SM732A2000-12 Dram Supported SIMMs BCSR SIMMs Init Value [hex] 02800001 FFE00D34 FFC00D34 FF800D34 FFE00D44 FFC00D44 FF800D44 02100001 FFFF8110 00000089 FFC00800 FF000800 00400089 01000089 FFC00800 FF000800 030000C1 Invalid bank Invalid bank 4MByte block size, types access, initial address multiplexing according 16MByte block size, types access, initial address multiplexing according AMA. Base 3000000, Description Base 2800000, port size, parity, GPCM 2MByte block size, types access, early negate, w.s., Timing relax 4MByte block size, types access, early negate, w.s., Timing relax 8MByte block size, types access, early negate, w.s., Timing relax 2MByte block size, types access, early negate, w.s., Timing relax 4MByte block size, types access, early negate, w.s., Timing relax 8MByte block size, types access, early negate, w.s., Timing relax Base 2100000, port size, parity, GPCM KByte block size, types access, early negate, w.s. Invalid bank Invalid bank
MCM36100/200-60/70 MCM36400/800-60/70 MT8/16D432/832X-6/7
MCM36200-60/70 MCM36800-60/70 MT16D832X-6/7
MCM36200-60/70 MCM36800-60/70 MT16D832X-6/7
Compatibl Mode Compatibl Mode
K4S643232-TC60
FFC00A00
MByte block size, types access, initial address multiplexing according AMB.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-6. Memory Controller Initialization 50Mhz with DRAM-EDO
Register MPC86x Mode MPC86x Mode Comm peripheral Comm peripheral Dram Supported SIMMs Device Type K4S643232-TC60 Init Value [hex] Description Base 0x0,
0x000000C1
0xFC800800
MByte block size, types access, initial address multiplexing according AMB.
0x02000401 0xFFF009A6 0400 40A21114a 60A21114b C0A21114c Divide (decimal) refresh clock divided C0c, periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided 60c, periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided C0c, periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided 60c, periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4enabled, loop read, loop write, beats refresh burst.
MPTPR MAMR
MB321BT08TASN60
MB322BT08TASN60
20A21114a 30A21114b 60A21114c
MB324CT00TBSN60
40B21114a 60B21114b C0B21114c
MB328CT00TBSN60
20B21114a 30B21114b 60B21114c
MBMR
KS643232C-TC60
D0802114c 80802114d
Assuming 16.67 BRGCLK. Assuming 25MHz BRGCLK 50MHz BRGCLK Assuming 32MHz BRGCLK.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-7. UPMA Initializations 60nsec DRAMs 50MHz
Cycle Type Offset Contents Offset Single Read 8FFFEC24 0FFFEC04 0CFFEC04 00FFEC04 00FFEC00 37FFEC47 Burst Read 8FFFEC24 0FFFEC04 08FFEC04 00FFEC0C 03FFEC00 00FFEC44 00FFCC08 0CFFCC44 00FFEC0C 03FFEC00 00FFEC44 00FFCC00 3FFFC847 Single Write 8FAFCC24 0FAFCC04 0CAFCC00 11BFCC47 Burst Write 8FAFCC24 0FAFCC04 0CAFCC00 03AFCC4C 0CAFCC00 03AFCC4C 0CAFCC00 03AFCC4C 0CAFCC00 33BFCC4F Refresh C0FFCC84 00FFCC04 07FFCC04 3FFFCC06 FFFFCC85 FFFFCC05 Exception 33FFCC07
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-8. UPMA Initializations 60nsec DRAMs 50MHz
Cycle Type Offset Contents Offset Single Read 8FFBEC24 0FF3EC04 0CF3EC04 00F3EC04 00F3EC00 37F7EC47 Burst Read 8FFFEC24 0FFBEC04 0CF3EC04 00F3EC0C 0CF3EC00 00F3EC4C 0CF3EC00 00F3EC4C 0CF3EC00 00F3EC44 03F3EC00 3FF7EC47 Single Write 8FFFCC24 0FEFCC04 0CAFCC00 11BFCC47 Burst Write 8FFFCC24 0FEFCC04 0CAFCC00 03AFCC4C 0CAFCC00 03AFCC4C 0CAFCC00 03AFCC4C 0CAFCC00 33BFCC4F Refresh C0FFCC84 00FFCC04 07FFCC04 3FFFCC06 FFFFCC85 FFFFCC05 Exception 33FFCC07
TABLE 3-9. Memory Controller Initializations 20Mhz
Register Device Type Flash supported. SIMMs Init Value [hex] 02800001 Description Base 2800000, port size, parity, GPCM
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-9. Memory Controller Initializations 20Mhz
Register Device Type MCM29F020-90 MCM29F040-90 SM732A1000A-9 MCM29F080-90 SM732A2000-9 MCM29F020-12 MCM29F040-12 SM732A1000A-12 MCM29F080-12 SM732A2000-12 Dram Supported SIMMs BCSR Init Value [hex] FFE00D20 FFC00D20 FF800920 FFE00D30 FFC00D30 FF800930 02100001 FFFF8110 00000081 FFC00800 FF000800 00400081 01000081 FFC00800 FF000800 030000C1 Description 2MByte block size, types access, early negate, w.s. 4MByte block size, types access, early negate, w.s. 8MByte block size, types access, early negate, w.s., Timing relax 2MByte block size, types access, early negate, w.s. 4MByte block size, types access, early negate, w.s. 8MByte block size, types access, early negate, w.s. Base 2100000, port size, parity, GPCM KByte block size, types access, early negate, w.s. Base port size, parity, UPMA 4MByte block size, types access, initial address multiplexing according AMA. 16MByte block size, types access, initial address multiplexing according AMA. Base 400000, port size, parity, UPMA Base 1000000, port size, parity, UPMA 4MByte block size, types access, initial address multiplexing according 16MByte block size, types access, initial address multiplexing according AMA. Base 3000000,
MB321/2BT08TASN60 MB324/8CT00TBSN60
BR3a
MB322BT08TASN60 MB328CT00TBSN60
MB322BT08TASN60 MB328CT00TBSN60
Compatibl Mode Compatibl Mode MPC86x Mode MPC86x Mode
K4S643232-TC60
FFC00A00
MByte block size, types access, initial address multiplexing according AMB. Base 0x0,
K4S643232-TC60
0x000000C1
0xFC800A00
MByte block size, types access, initial address multiplexing according AMB.
Comm peripheral
0x02000401
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-9. Memory Controller Initializations 20Mhz
Register MPTPR MAMR Device Type Comm peripheral Dram Supported SIMMs Init Value [hex] 0xFFF009A6 0400 60A21114 Divide (decimal) refresh clock divided periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 disabled data sampling edge flexibility, loop read, loop write, beats refresh burst. refresh clock divided periodic timer enabled, type address multiplexing scheme, cycle disable timer, GPL4 enabled, loop read, loop write, beats refresh burst. Description
MB321BT08TASN60
MB322BT08TASN60
30A21114
MB324CT00TBSN60
60B21114
MB328CT00TBSN60
30B21114
MBMR
KS643232C-TC60
42802114b
initialized MB321xx MB324xx DRAM SIMMs. Assuming 16.67MHz BRGCLK
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-10. UPMA Initializations 60nsec DRAMs 20MHz
Cycle Type Offset Contents Offset Single Read 8FFFCC04 08FFCC00 33FFCC47 Burst Read 8FFFCC04 08FFCC08 08FFCC08 08FFCC08 08FFCC00 3FFFCC47 Single Write 8FEFCC00 39BFCC47 Burst Write 8FEFCC00 09AFCC48 09AFCC48 09AFCC48 39BFCC47 Refresh 80FFCC84 17FFCC04 FFFFCC86 FFFFCC05 Exception 33FFCC07
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-11. UPMB Initialization KS643232C-TC60 upto 32MHz
Cycle Type Offset Contents Offset Single Read 0126CC04 0FB98C00 1FF74C45 1FE77C34a EFAABC34 1FA57C35 Burst Read 0026FC04 10ADFC00 F0AFFC00 F1AFFC00 EFBBBC00 1FF77C45 Single Write 0E26BC04 01B93C00 1FF77C45 Burst Write 0E26BC00 10AD7C00 F0AFFC00 F0AFFC00 E1BBBC04 1FF77C45 Refresh 1FF5FC84 FFFFFC04 FFFFFC84 FFFFFC05 Exception 7FFFFC07
initialization. Uses Free space.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
OPERATING INSTRUCTIONS
TABLE 3-12. UPMB Initialization KS643232C-TC60, 32+MHz 50MHz
Cycle Type Offset Contents Offset Single Read 1F07FC04 EEAEFC04 11ADFC04 EFBBBC00 1FF77C47 1FF77C34a EFEABC34 1FB57C35 Burst Read 1F07FC04 EEAEFC04 10ADFC04 F0AFFC00 F0AFFC00 F1AFFC00 EFBBBC00 1FF77C47 Single Write 1F27FC04 EEAEBC00 01B93C04 1FF77C47 Burst Write 1F07FC04 EEAEBC00 10AD7C00 F0AFFC00 F0AFFC00 E1BBBC04 1FF77C47 Refresh 1FF5FC84 FFFFFC04 FFFFFC04 FFFFFC04 FFFFFC84 FFFFFC07 Exception 7FFFFC07
initialization, Uses free space.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
Functional Description
this chapter various modules combining MPC86xADS described their design details.
Reset Reset Configuration
Regular Power Reset Manual Soft-Reset Manual Hard-Reset Internal Sources. (See appropriate Spec U/M)
There several reset sources ADS:
Regular Power Reset
regular power reset operates, using device DALAS DS1818. reference voltage this device MAIN VDDH while reset line asserted, HRESET* line. When HRESET~ asserted MPC, Hard-Reset configuration made available MPC, BCSR0. "Hard Reset Configuration" page TABLE 4-10. "BCSR0 Description" page
Manual Soft Reset
support application development around debug port resident debuggers, soft reset pushbutton provided. (SW6) Depressing that button, asserts SRESET* MPC, generating SOFT RESET sequence. When SRESET~ line asserted MPC, Soft-Reset configuration made available MPC, debug-port controller. "Soft Reset Configuration" page
Manual Hard Reset
support application development around debug port, Hard-Reset push-button providedA. When Soft Reset push-button (SW6) depressed conjunction with ABORT push-button (SW5), HRESET* line asserted, generating HARD RESET sequence. button sharing economy board space saving does effect way, functionality.
Internal Sources
Since HRESET* SRESET* lines open-drain on-board reset logic drives these lines with open-drain gates, correct operation internal reset sources facilitated. rule, internal reset source asserts HRESET* SRESET* minimum time system clocks. beyond scope this document describe these sources, however Debug-Port Soft Hard Resets which part development systemB, regarded such.
Reset Configuration
During reset device samples state some external pins determine operation modes configuration. There kinds reset levels each level having configuration sampled: Power Reset configuration Hard Reset configuration Soft Reset Configuration. dedicated button. therefore mentioned.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description Power Reset Configuration
Just before PORESET* negated external logic, power-on reset configuration which include MODCK(1:2) pins sampled. These pins determine clock operation mode MPC. clock modes supported MPC86xADS: operation on-board clock generator. this mode MODCK(1:2) driven with'11' duringA power reset. 1:513 operation on-board clock generator. this mode MODCK(1:2) driven with'00'. during power-on reset.
Hard Reset Configuration
During HARD reset sequence, when RSTCONF* asserted, data state sampled acquire MPC's hard reset configuration. reset configuration word driven BCSR0 register, defaults which during power-on reset. BCSR0 drives half configuration word, i.e., data bits D(0:15) which reserved bits designated RSRVxx. hard-reset configuration changedB, BCSR0 written with values, which become valid after HARD reset applied MPC. ADS, RSTCONF* line always driven during HARD reset, i.e., possible with MPC's internal HARD reset configuration defaults. system parameters which BCSR0 defaults during power-on reset driven hard-reset, listed below: Arbitration: internal arbitration selected. Interrupt Prefix: internal default interrupt prefix 0xFFF00000. overridden provide interrupt prefix address which located within DRAM. Boot Disable: Boot enabled. Boot Port Size: boot port size selected. Initial Internal Space Base: Immediately after HARD reset, internal space located $FF000000. Debug pins configuration: PCMCIA port pins become PCMCIA port pins. Debug port pins configuration. Debug port pins JTAG port. External Division Factor: internal external clocks' frequencies ratio selected.
Soft Reset Configuration
rising edge SRESET* used configure development port. Before negation SRESET*, DSCKD sampled determine debug-mode enable disable. After SRESET* negated, debug mode enabled, DSCK sampled again debug-mode entry non-entry. DSDI used determine debug port clock mode sampled after negation SRESET*. Soft Reset configuration provided debug-port controller I/F. Option given enter debug mode directly only after exception.
Local Interrupter
only external interrupt which applied interrupt controller ABORT (NMI), MODCK lines fact driven longer HRESET~ line. With respect ADS's power-on defaults. Where they exist. DSCK configured hard-reset reside JTAG port.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
which generated push-button. When this button depressed, input asserted. purpose this type interrupt, support resident debuggers made available ADS. other interrupts MPC, generated internally MPC's peripherals debug port. support external (off-board) generation NMI, IRQ0* line which routed input, driven open-drain gate. This allows external also drive this line. external indeed does compulsory that IRQ0* driven open-drain open-collector) gate.
Clock Generator
5MHz Clock generator connected CLK4IN input. mode. (SW1 OFF) 32.768 crystal resonator EXTAL-XTAL pair MPC, 1:513 initial multiplication factor. (SW1
There ways clock MPC86xADS when using other device then MPC866:
selection between above modes done using Dip-switch (SW1 with dual functionality: responsible combination driven MODCK lines during power-on reset connection appropriate capacitor between MPC's VDDSYN lines match PLL's multiplication factor. When mode selected, capacitor 5.6nF connected, while when 1:513 mode selected 0.56µF capacitor connected parallel digital switch (U52). capacitors' values calculated support wider range multiplication factors possible. When mode above selected, output clock generator gated from EXTCLK input driven to'0' constantly that jitter-free system clock generated. On-board logic clocked 20Mhz Clock Oscylator. This clock generator used, that on-board logic always clocked, even when removed from socket. MPC866 device there this switch selecting digital switch connect above capacitors PLL. select other then MPC866 select MPC866.
Buffering
meant serve also hardware development platform, necessary buffer from local bus, MPC's capacitive drive capability wasted internally remains available user's off-board applications expansion connectors. Buffers provided address strobe lines while transceivers provided data. Since capacitive load over dram's address lines mightA exceed dram address lines separately buffered. done with 74LCX buffers which 3.3V operated tolerant. This type buffers reduces noise board reduced transitions' amplitude. further reduce noise reflections, series resistors placed over dram's address strobe lines. data transceivers open only there access validB board address during Hard Reset configurationD. That data conflicts avoided case off-board memory read, provided that mapped address valid board. users' responsibility avoid such errors.
Depended dram SIMM's internal structure. address which covered Chip-Select region. Except SDRAM, which Unbuffered. allow configuration word stored Flash memory become active.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
Chip Select Generator
memory controller used chip-select generator access on-boardA memories, saving board's area reducing cost, power consumption increasing flexibility. enhance off-board application development, memory modules (including BCSRx) disabled BCSR1B favor external memory connected expansion connectors. That way, line used off-board expansion connectors, while associated local memory disabled. When region disabled BCSR1, local data transceivers open during access that region, avoiding possibleC contention over data lines. MPC's chip-selects assignment various memories registers shown TABLE 4-1. "MPC86xADS Chip Selects' Assignment" below:
TABLE 4-1. MPC86xADS Chip Selects' Assignment
Chip Select: CS0* CS1* CS2* CS3* CS4* CS5* CS(6-7)* Assignment Flash Memory BCSR DRAM Bank DRAM Bank SDRAM Communication Peripherals Unused, user available
exists.
DRAM
DRAM supplied with board. user DRAM DRAM SIMM.The MPC86xADS able operate with MBytes 60nsec delay Dram SIMM. Support given powered Dram SIMM configured upto with nsec 70nsec delay. dram configurations supported Board Control Status Register (BCSR), i.e., DRAM size 32M) delay nsec) read from BCSR2 associated registers (including UPM) programmed accordingly. Dram timing control performed UPMA (and dual-bank SIMM) region(s), i.e., signals' generation, during normalD access well during refresh cycles necessary address multiplexingE performed using UPMA. CS2* CS3* signals buffered from DRAM each split overcome capacitive load over Dram SIMM lines. DRAM module enabled disabled time writing DRAMEN~ BCSR1. TABLE Phriphrials off-board. further. After BCSR removed from local memory map, there access re-apply power ADS. During read cycles. Normal i.e.: Single Read, Single Write, Burst Read Burst Write. Taking into account support narrower widths.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
4-11. "BCSR1 Description" page Note: DRAM populated board user populate DRAM order expand memory which MPC8xxFADS.
DRAM Operation
enhance evaluation capabilities, support given Dram with 16-bit 32-bit data width. That users tailor dram configuration, best their application requirements. When DRAM mode, half used, i.e., memory portion that connected data lines D(16:31). configure DRAM data width operation, following steps should taken: Dram_Half_Word BCSR1 Half-Word. TABLE 4-11. "BCSR1 Description" page Port Size bits BR2~ (and BR3~ 2-bank DRAM simm) should bits. bits register should nominal single-bank DRAM simm volume nominal dual-bank DRAM simm volume.
Dual-Bank DRAM simm being used: Base-Address bits register should DRAM_BASE Nominal_Volume, that contiguous block DRAM desired. bits register, should Nominal_Volume.
above executed running code, than this code should reside DRAM while executing, otherwise, erratic behavior likely demonstrated, resulting system crash.
DRAM Performance Figures
projected performance figures dram shown TABLE 4-2. "Regular DRAM Performance
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
Figures" page TABLE 4-3. "EDO DRAM Performance Figures" page
TABLE 4-2. Regular DRAM Performance Figures
Number System Clock Cycles System Clock Frequency [MHz] DRAM Delay [nsec] Single Read Single Write 6,2,3,2 4,2,2,2 6,3,2,3 4,2,2,2 3,2,2,2 3,1,2,2 4,2,2,2 3,2,2,2
Burst Read Burst Write Refresh
Four-beat refresh burst. including arbitration overhead.
TABLE 4-3. DRAM Performance Figures
Number System Clock Cycles System Clock Frequency [MHz] DRAM Delay [nsec] Single Read Single Write Burst Read Burst Write Refresh 6,2,2,2 4,2,2,2 6,3,2,2 4,2,2,2 3,1,1,1 2,1,1,1 4,1,2,2 3,2,2,2
Four-beat refresh burst. including arbitration overhead.
Refresh Control
refresh dram before refresh, which controlled UPMA well. refresh logic clocked MPC's clock which influenced MPC's low-power divider.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
FIGURE Refresh Scheme
Clock
DRAM BANKS seen FIGURE "Refresh Scheme" above, clock twice divided: once (Periodic Timer Prescaler) again another prescaler PTA, dedicated each UPM. there more than dram banks, than refresh cycles performed consecutive banks, therefore, refresh should made faster. formula calculation given below: Refresh_Period Number_Of_Rows_To_Refresh T_BRG MPTPR Number_Of_Banks
Where: Periodic Timer filed MAMR. value 2'nd divider. Refresh_Period time (usually msec) required refresh dram bank using looping capability, possible perform more than refresh cycle refresh burst fact upto 16). Number_Of_Rows_To_Refresh: number rows dram bank T_BRG: cycle time clock MPTPR: value periodic timer prescaler Number_Of_Banks: number dram banks refresh. Refresh_Period msec Number_Of_Rows_To_Refresh 1024 T_BRG nsec (system clock Mhz) MPTPR arbitrarily chosen Number_Of_Banks that SIMM
take example MCM36200 SIMM which following data:
assign figures formula value should decimal hex.
Variable Bus-Width Control
Since port's width determines address lines' connection scheme, i.e., number address lines required byte-selection varies 16-bit port 32-bit port) according port's width, necessary change address connections memory port width changed. E.g.: certain memory initially configured 32-bit port, list significant address line which connected that memory's line should MPC's A29. Now, that port reconfigured 16-bit port, address line becomes A30. linearA address scheme maintained, address lines connected that memory shifted bit, this obviously involves extensive multiplexing (passive active). linear addressing
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
scheme must, than only minimal multiplexing required support variable port width. TABLE 4-4. "DRAM ADDRESS CONNECTIONS" below, ADS's dram address connection scheme presented:
TABLE 4-4. DRAM ADDRESS CONNECTIONS
Width Depth Dram BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA30 Depth BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA30
seen from table above, most address lines remain fixed while only lines (the shaded cells) need switching. switching scheme shown FIGURE "DRAM Address Lines' Switching Scheme" page switches that figure implemented active multiplexers controlled BCSR1/Dram_Half_Word* bit.
Consequent addresses lead adjacent memory cells
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
FIGURE DRAM Address Lines' Switching Scheme
DRAM BA(21:29) A(0:8)
BA20 BA30
BA19 BA30
Flash Memory SIMM
MPC86xADS provided with 2Mbyte nsec flash memory SIMM MCM29020 Motorola. Support given also 4MBytes MCM29F040, MBytes MCM29F080, MBytes SM73218 MBytes SM73228 Smart Technology. Motorola SIMMs internally composed banks Am29F040 compatible devices, while Smart SIMMs arranged banks four 28F008 devices Intel. flash SIMM resides SIMM socket. minimize MPC's chip-select lines, only chip-select line (CS0~) used select flash whole, while distributing chip-select lines among internal banks done on-board programmable logic, according Presence-Detect lines Flash SIMM inserted ADS.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
FIGURE Flash Memory SIMM Architecture
Flash Presence-Detect Lines
F_CS1~
M29F040 M29F040 M29F040 M29F040
F_CS2~ CS0~
ADS's Logic
M29F040
M29F040
M29F040
M29F040
F_CS3~ F_CS4~
M29F040
M29F040
M29F040
M29F040
M29F040
M29F040
M29F040
M29F040
DATA MCM29F020 SM73218 MCM29F040 SM73228 MCM29F080
access time Flash memory provided with nsec, however, nsec devices used well. Reading delay section Flash SIMM Presence-Detect lines, debugger establishes (via OR0) correct number wait-states (considering 50MHz system clock frequency). Motorola SIMMs built AMD's Am29F0X0 devices which programmable, i.e., there need external programming voltage flash written almostA regular memory. SMART parts however, require 0.5% programming voltage applied programming. on-boards programming such device required, supply needs connected (P12). Otherwise, normalB Flash operation, supply required. control over flash done using GPCM dedicated CS0~ region, controlling whole bank. During hard reset initializations, debugger reads Flash Presence-Detect lines BCSR2 decides program registers, within which size delay region determined. performance flash memory shown TABLE 4-5. "Flash Memory Performance Figures" below
TABLE 4-5. Flash Memory Performance Figures
Number System Clock Cycles System Clock Frequency [MHz] Flash Delay [nsec] Read Writea Access [Clocks]
manufacturer specific dedicated programming algorithm should implemented during flash programming. I.e., Read-Only.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
figures table refer actual write access. write operation continues internally device polled operation completion.
Flash module disabled enabled time writing'1' /'0' FlashEn~ BCSR1.
Synchronous Dram
enhance performance, especially higher operation frequencies MBytes SDRAM provided board. SDRAM unbuffered from configured 512K done with MT48LC2M32B2 chips Micron compatibles.
enhance performance, SDRAM unbuffered from MPC, saving delay associated with address data buffers. Since only memory chip involved, does adversely effect overall system performance. SDRAM does reside SIMM soldered directly pcb. SDRAM enabled disabled time writing SDRAMEN BCSR1. TABLE 4-11. "BCSR1 Description" page SDRAM's timing controlled UPMB assigned (See TABLE 4-1. "MPC86xADS Chip Selects' Assignment" page line. Unlike regular dram synchronous dram input addition signals. sdram connection scheme shown FIGURE "SDRAM Connection Scheme" page SDRAM's performance figures, shown TABLE 4-8. "Estimated SDRAM Performance Figures": This SDRAM Column. suggested interface between MPC8xx SDRAM illustrated Figure bellow clear that this glue less interface. bus, SDRAM devices connected.The control driven UPMB MPC8xx, SDRAM interfaced MPC8xx. other chip select line excluding would do.The signals used SDRAM devices select byte lanes connected appropriate Byte Strobe (BS0:3)signals MPC8xx. connected GPL0,since this functionality either drive address line, defined level. This required acts both address line control line. generated GPL1 GPL2 respectively. generated GPL3. driven MPC8xx's CLKOUT signal which reference point with respect MPC8xx's Memory Controller. SDRAM used example 2048 rows columns, have address lines column address lines.The line connected line A10, used high order address bit. Please remember that MPC8xx address lines have different numbering scheme than SDRAM address lines when reading address
line mapping Table below.
TABLE 4-6. SDRAM refer MPC8xx Pins
MPC8xx A11:A21 A22:A29 SDRAM BS1, Column
Register =0b000, address bits A11:21 mapped lines A19:29 addresses. start with line connect need
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description provide left over address using line (which would show multiplexed address), using GPL0 described above. Register MxMR, program GPL0 show complete addressing. this case there banks SDRAM device, Sometimes, single SDRAM bank enough memory application. Connecting multiple SDRAM based banks MPC8xx fairly straightforward. Extending interface described above easy. Above, most significant address connected SD.A10 used address size
bits (8/11 address multiplex!) covered example SDRAM device. SDRAM device with
lines,BS0 simply next address bit,e.g.,A10, MPC, with more significance keep memory mapping linear. essence, address lines binary encoding bank
selection.
TABLE 4-7. SDRAM Connected
output GPL0 Note1 Note1 SDRAM (AP) NC(A11) Internal Column Internal
Note
Note1 Incase user wonts change SDRAM larger SDRAM connected A10, this connection already exist board layout, user connect BS0,
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
this will done moving resistors board called from pins
TABLE 4-8. Estimated SDRAM Performance Figures
Number System Clock Cycles System Clock Frequency [MHz] Single Read Single Write Burst Read
3,1,1,1 2,1,1,1
5,1,1,1 3,1,1,1
Burst Write Refresh
fact upto 32MHz. additional cycle precharge 4-beat Refresh Burst, including arbitration overhead.
FIGURE SDRAM Connection Scheme
GPL1 GPL2 GPL3
GPL0 (A11) A(9,10) A(20:29) SDRAMEN SYSCLK BS0_B BS1_B BS2_B BS3_B D(0:31)
BS(1:0) A(9:0) DQM3 DQM2 DQM1 DQM0 DQ(31:0)
SDRAM Programming
After power-up, sdram needs initialized means programming, establish mode oper-
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
ation. Sdram programmed issuing Mode Register command. During that command, data passed Mode Register through Sdram's address lines. This command fully supported means dedicated Memory Address Register command option. Mode Register programming values shown TABLE 4-9. "SDRAM's Mode Register Programming" below: order operate SDRAM higher speed then 50Mhz user should read application note also MPC860COD09 MPC860 Programming Tool UPM860
MPC860COD10 UPM860 Manual MPC860 Programming Tool page
TABLE 4-9. SDRAM's Mode Register Programming
Value Frequency SDRAM Option Burst Length Burst Type Latency Write Burst Length 50MHz Sequential Burst 25MHz Sequential Burst
SDRAM Initializing Procedure
UPMB should programmed with values described TABLE 3-11. "UPMB Initialization KS643232C-TC60 upto 32MHz" page TABLE 3-12. "UPMB Initialization KS643232C-TC60, 32+MHz 50MHz" page Memory controller's MPTPR, MBMR, registers should programmed according TABLE 3-9. "Memory Controller Initializations 20Mhz" page TABLE 3-5. "Memory Controller Initialization 50Mhz with DRAM-EDO" page should with proper value (0x48 upto 32MHz 0x88 MHz) should written with 0x80808105 command programmed locations UPMB. MBMR's TLFB field should changed constitute 8-beat refresh Bursts. should written with 0x80808130 refresh sequence refresh cycles performed now) MBMR's TLFB field should restored provide 4-beat refresh Bursts normal operation. SDRAM initialized ready operation.
After Power-up SDRAM needs initialized certain manner, described below:
SDRAM Refresh
SDRAM refreshed using auto-refresh mode. I.e., using UMPB's periodic timer, burst four auto-refresh commands issued SDRAM every 62.4 µsec, that 2048 SDRAM rows refreshed within specified 32.8 msec.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
Communication Ports
Since board meant serve MPC86x family, contains modules that possible configured MPC86x. various communication ports below: SCC1 10BaseT Ethernet. SCC3 SMC1, SMC2 RS232. TDMB Serial E1/T1 FETHC Fast Ethernet Controller. PCMCIA Port Port Amux/Split, Port Split both PCMCIA Port MultyPhy SinglePhy
Ethernet Port
Ethernet port with T.P. (10-Base-T) provided MPC86xADS. comm. port over which this port resides, determined according typeA. done with MC68160 EEST 10-base-T transceiver, used also with MPC86xADS. allow alternative Ethernet's pins, they appear expansion connectors. Ports expansion connector (P7) this board, while Ethernet transceiver Disabled Enabled time writing'1' /'0' EthEn~ BCSR1.
Infra-Red Port
infra-Red communication port provided with Temic's TFDS 6000 integrated transceiver, which incorporates both receiver transmitter optical devices with translating logic supports Fast IrDA (upto Mbps). comm. port over which this port resides, determined according typeA. allow alternative I/Or's pins, infra-red transceiver disabled enabled time, writing /'0' IrdEn~ BCSR1, while pins appear expansion connector, this board.
Infra-Red Port Rate Range Selection
9600 MBps MBps MBps.
TFDS6000 bit-rate ranges:
Selection between ranges determined state transceiver's input falling edge IrdEn~. When input least nsec before falling edge IrdEn~, then, LOWER range selected. HIGH that period time, then, HIGHER range selected.
RS232 Ports
assist user's applications provided convenient communication channels with both terminal host computer, identical RS232 ports provided ADS. MPC's communication ports which these RS232 ports routed, established according type MPC. done with MAX3241ECAI transceivers which generates RS232 levels internally using single 3.3V supply equipped with shutdown mode. When RS232EN1 RS232EN2 bits BCSR1 asserted (low), associated transceiver enabled. When negated, associated transceiver enters standby mode, which receiver outputs tri-stated, enabling associated port's pins, off-board I.e., routing done daughter board.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
expansion connectors. SMC2 conflict with Aaddress pins. order work with SMC2 user should work Asingle phy, look description. done with pins, female D-Type stacked connector, configured directly (via flat cable) connected standard IBM-PC like RS232 connector.
FIGURE RS232 Serial Ports' Connector
N.C.
RS-232 Ports' Signal Description
list below, direction','I/O' relative board. (I.e.'I' means input ADS)
Data Carrier Detect. This line always asserted ADS. Transmit Data. Receive Data. Data Terminal Ready. This signal used software detect terminal connected board. Data Ready. This line always asserted ADS. Request Send. This line connected ADS. Clear Send. This line always asserted ADS.
Utopia Operation Interface
MPC862DB supports multy phy, single phy, muxed split Utopia operation. muxing logic shown FIGURE "UTOPIA Buses interfaces control" page realized using series logic switches data lines appropriate. split configuration transmit receive data signals separated. this configuration MPC86xADS limits operation several other port functions including disabling MII, 100BaseT Ethernet interface. muxed configuration MPC86xADS multiplexes ("mux"s) transmit receive data, clock utopia signals. This configuration allows MPC86xADS provide operation other port functions such 100BaseT Ethernet (MII). board also allows MPC862/6 exercised both Utopia level "master" Utopia level "slave" device. master mode MPC862/6 Utopia interface software programmable either muxing (combined bus) split configurations (separate bus). board select mode operation switches, SW2(2,3,4) select AFastEthernet mode operation.The ATM25 interface ATM155 interface used slave devices. should configured output Utopia clock. NOTE: split configuration (master slave modes) 100BaseT Ethernet interface necessarily disabled. MPC862/6 provides simultaneous control support multiple physical interfaces connected Utopia bus. Utopia addressing allows physical devices connected. this board there only ATM25 ATM155. only AADDRESS used Board receive transmit. PB16 RXADD0, PB17 RXADD1, PB20 TXADD0 PB21
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TXADD1. Note case using ATM, RS232-2 use. (marked board silk) NOTE: device interrupts ANDed together provide single interrupt MPC86x. Fast Ethernet will able connect PCMCIA port Port will according control logic. figure below shows connections Port-D PCMCIA port with control logic that selects each mode operation.
FIGURE UTOPIA Buses interfaces control
Port-D Select function signals
switch
signals Utopia APHYs
Jumpers
Logic
signals
Expanion Connector Switch Fast Ethernet
Port-D
Control Logic
Switch Control
switch
Expansion Connector
PCMCIA Port
PCMCIA Select function signals
ATM25
A25M connected Utopia bus. Supports mode through port-D transmit receive utopia signals split modetransmit signals through Port-D receive utopia signals through PCMCIA port. Implementation done using IDT77107 device. ATM25 memory mapped 0x2000000.
ATM155
A155 connected Utopia bus. Supports mode through port-D transmit receive utopia signals split modetransmit signals through Port-D receive utopia signals through PCMCIA port. Implementation done using uPD98404 device. Note: order operate NEC-uPD98404 correctly should init devise also init then reset APHY driving address 0x2000300 value 0x08 (reset uPD98404). ATM155 mapped 0x2000100.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
Serial A(Over E1/T1)
MPC862/6 capability perform layer. Alayer serial Aoutput connected TDMB. Implementation done using Infineon PEB2256 E1/T1 device. MPC862/6 drive through TDMB. PEB2256 mapped 0x2000200. 2.048M supplied board
Fast Ethernet.
MPC8626ADS provides 100BaseT Ethernet interface connected MPC862/6 inteface. MPC862 provides simultaneous operation both fast ethernet Utopia bus. board provides necessary hardware interfaces bussing logic support this simultaneous feature. address 0b01111. Note: inorder configure board desire configuration ATM, Fast-Ethernet TABLE 2-2. Fast-Ethernet configuration." page table.
PCMCIA Port
enhance PCMCIA development, dedicated PCMCIA port provided ADS. Support given only PC-Cards, PCMCIA standard 2.1+ compliant. necessary control signals generated itself. protect signals from external hazards, provide sufficient drive capability, buffers latches provided over PC-Card's address, data strobe lines. conform with design spirit ADS, i.e., making much possible resources available external application development, input buffers provided input control signals, controlled PCC_EN~ BCSR1, PCMCIA port Disabled Enabled time, writing that bit. When PCMCIA channel disabled, associated pins available off-board expansion connectors. loudspeaker provided board connected SPKROUT line MPC. speaker buffered from low-pass filtered. When PCC_EN~ BCSR1 negated (high) speaker buffer tri-stated SPKROUT signal used alternate function. Since desirableA apply control signals unpowered PC-Card, strobe data signal buffers transceivers tri-stated driven only when PC-Card powered. block diagram PCMCIA port shown FIGURE "PCMCIA Port Configuration" page
This since PC-Card might have protection diodes inputs, which will force down input signals regardless their driven level.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
FIGURE PCMCIA Port Configuration
PCMCIA SOCKET
PCCVCC From BCSR PCMCIA POWER CONTROL Power Logic LTC1315 equiv. PCCVPP
D[8:15] Data_A[15:8] D[0:7] From BCSR CE1_A(B) CE2_A(B) WE/PGM IORD,IOWR RESET_A(B) WE/PGM IORD,IOWR RESET PCMCIA_EN Data_A[7:0]
MPC8XX Daughter Board
POE_A(B)
buffer with Transparent latch with
Address_A[25:0]
A[6:31]
ALE_A(B) WAIT_A(B), IOIS16_A(B) RDY/BSY_A(B), BVD(1:2)_A(B)
SPKROUT CD(1:2)_A(B),VS(1:2)_A(B)
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
PCMCIA Power Control
support hot-insertionA socket's power controlled dedicated PCMCIA power controller LTC1315 made LINEAR TECHNOLOGY. This device, controlled BCSR1, switches card programming controls gates external MOSFET transistors, through which Card switched. When card inserted while channel enabled BCSR1, i.e., both CD(1:2)* (Card Detect) lines asserted (low), status voltage select lines VS(1:2)* should read determine Card's operation voltage level according which, PCCVCC(0:1) bits BCSR1 should set, drive correct (5V) PC-Card. When card being removed from socket while channel enabled BCSR1, negation CD1~ CD2~ sensed power supply card cut.
WARNNING
application handling PCMCIA channel must check Voltage-Sense lines before Power applied PC-Card. Otherwise, power applied 3.3V-Only card, permanent damage will inflicted PC-Card.
Board Control Status Register BCSR
Most hardware options MPC86xADS controlled monitored BCSR, which wide read write register file. BCSR accessed MPC's region fact includes registers: BCSR0 BCSR4. Since minimum block size region 32KBytes, BCSR0 BCSR4 multiply duplicated within that region. also TABLE 3-3. "Memory Compatible Mode" page following functions controlled monitored BCSR: MPC's Hard Reset Configuration. Flash Module Enable Disable Dram Module Enable Disable Dram port width bit. SDRAM Module Enable Disable. Ethernet port Enable Disable. Infra-Red port Enable Disable. RS232 port Enable Disable. RS232 port Enable Disable.
BCSR Enable Disable. Hard Reset Configuration Source BCSR0 FlashC Memory PCMCIA control which include: Channel Enable Disable.
I.e., card insertion when powered fact only upper bits D(0:15) used, BCSR mapped wide register should accessed such. Provided that support provided also within MPC.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
Card appliance. Card appliance.
Ethernet Port Control. Dram Type Size Delay Identification. Flash Size Delay Identification. External (off-board) tools identification option selection switch SW7status. Daughter Board Board Revision code Reset E1/T1 device Reset ATM155. Reset ATM25. Reset Fast Ethernet PHY.
BCSR Disable Protection Logic
BCSR itself disabled favor off-board logic. avoid accidental disable BCSR, event from which only power re-appliance recovers, protection logic provided: BCSR_EN~ resides BCSR1. This wakes-up active (low) during power-up changedA unless BCSR_EN_PROTECT~ BCSR3 written with previously. After BCSR_EN_PROTECT~ written with unprotect BCSR_EN~ there only shot disabling BCSR, since, immediately after write BCSR1, BCSR_EN_PROTECT~ re-activated BCSR_EN~ re-protected disabling procedure repeated desired.
BCSR0 Hard Reset Configuration Register
BCSR0 located offset BCSR space. read written timeB. BCSR0 gets defaults upon MAINC Power-On reset. During Hard-Reset data contained BCSR0 driven data provide Hard-Reset configuration MPC, this, Flash_Configuration_Enable~ BCSR1 active. BCSR0 written time change Hard-Reset configuration MPC. values become valid when next Hard-Reset issued regardless Hard-Reset source. description BCSR0 bits shown TABLE 4-10. "BCSR0 Description" page
written will influenced. Provided that BCSR disabled. I.e., when VDDH powered.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-10. BCSR0 Description
MNEMONIC Reserved BDIS BPS(0:1) Reserved ISB(0:1) FUNCTION External Arbitration. When during Hard-Reset, Arbitration performed internally. When during Hard-Reset, Arbitration performed externally. Interrupt Prefix. When during Hard-Reset, Interrupt prefix 0xFFF00000, Interrupt Prefix Implementeda Boot Disable. When during Hard-Reset, CS0~ region enabled boot. When '1', CS0~ region disabled boot. Boot Port Size. Determines port size CS0~ boot. '00' bit, '01' bit, '10' bit, '11' reserved. Implementeda Initial Space Base. Value during Hard-Reset determines initial base address internal memory map. When '00' initial space when '01' initial space 0x00F00000, when '10' initial space 0xFF000000, when '11' initial space 0xFFF00000. Debug Pins Configuration. Value during Hard-Reset determines function PCMCIA channel pins. When '00' these pins function PCMCIA channel pins, when '01' they serve Watch-Points,'10' Reserved, when '11' they become show-cycle attribute pins, e.g., VFLS, Debug Port Pins Configuration. Value during Hard-Reset determines location debug port pins. When '00' debug port pins JTAG port, when '01' debug port non-existent, '10' Reserved, when '11' debug port PCMCIA channel pins. External Division Factor. Value during Hard Reset determines factor upon which CLKOUT external bus, divided with respect internal clock. When '00' CLKOUT GCLK2 divided when '01', CLKOUT GCLK2 divided Implementeda. Un-Implemented DEF. '00' '10'
DBGC(0:1)
'11'
11-12
DBPC(0:1)
'00'
EBDF(0:1)b
'00'
Reserved Reserved
read written other fields presented their associated data pins during Hard-Reset. Applicable MPC's revision above. Otherwise have influence.
BCSR1 Board Control Register
BCSR1 serves control register ADS. accessed offset from BCSR base address. read written timeA. BCSR1 gets defaults upon Power-On reset. BCSR1 fields described TABLE 4-11. "BCSR1 Description" page
Provided that BCSR disabled.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-11. BCSR1 Descriptiona
MNEMONIC FLASH_EN Function Flash Enable. When this active (low), Flash memory module enabled local memory map. When in-active, Flash memory removed from local memory CS0~, which Flash memory connected used off-board expansion connectors. Dram Enable. When this active (low), DRAM module enabled local memory map. When in-active, DRAM removed from local memory CS2~ CS3~b, which DRAM connected used off-board expansion connectors. Ethernet Port Enable. When asserted (low) EEST connected SCC1 enabled. When negated (high) that EEST standby mode, while system signals tri-stated. Infra-Red Port Enable. When asserted (low), Infra-Red transceiver, connected SCC2 enabled. When negated, Infra-Red transceiver shutdown mode. SCC2 pins available off-board expansion connectors. Flash Configuration Enable. When this asserted (low): Hard-Reset configuration held BCSR0 driven data during Hard-Reset configuration data held 1'st word flash memory driven data during Hard-Reset. Control Register Enable Protect. When this active (low) BCSR_EN that register written. When in-active, BCSR_EN written remove BCSR from memory map. After write BCSR1 this becomes active again. This read-onlyd that register. BCSR Enable. When this active (low) Board Control Status Register enabled local memory map. When inactive, BCSR read written associated CS1~ available off-board expansion connectors. This written with only CNT_REG_EN_PROTECT negated (1). When BCSR disabled still continues configure board according last data held even during Hard-Reset. RS232 port Enable. When asserted (low) RS232 transceiver port enabled. When negated, RS232 transceiver port standby mode relevant communication port pins available offboard expansion connectors. Card Enable. When asserted (low), on-board PCMCIA channel enabled, i.e., address strobe buffers enabled from card. When negated, buffers from PCMCIA channel disabled allowing off-board associated lines. ATT.
DRAM_EN
ETHEN
IRDEN
FLASH_CFG_EN
CNT_REG_EN_P ROTECT
BCSR_EN
RS232EN_1
PCCEN
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-11. BCSR1 Descriptiona
MNEMONIC PCCVCC0 Function Card Select These signal conjunction with PCCVCC1 determine voltage applied PCMCIA card's VCC. Possible values encoding these lines their associated voltages TABLE 4-12. "PCCVCC(0:1) Encoding" page Card VPP. These signals determine voltage applied PCMCIA card's VPP. Possible values encoding these lines their associated voltages TABLE 4-13. "PCCVPP(0:1) Encoding" page Dram Half Word. When this active (low) steps listed "DRAM Operation" page taken, DRAM becomes wide. When inactive DRAM wide. RS232EN_2 RS232 port Enable. When asserted (low) RS232 transceiver port enabled. When negated, RS232 transceiver port standby mode relevant communication port pins available offboard expansion connectors. SDRAM Enable. When this active (high), SDRAM module enabled local memory map. When in-active, DRAM place low-power mode, fact removed from local memory map, allowing associated line, used off-board expansion connectors. Card Select These signal conjunction with PCCVCC0 determine voltage applied PCMCIA card's VCC. Possible values encoding these lines their associated voltages TABLE 4-12. "PCCVCC(0:1) Encoding" page Un-implemented ATT.
PCCVPP(0:1)
'11'
Dram_Half_Word
SDRAMEN
PCCVCC1
Reserved
Shaded areas additions with respect MPC86xADS. case Single Bank DRAM SIMM used CS3~ free well. Provided that this option supported driving address lines asserting CS0~ during Hard-Reset. written BCSR3.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-12. PCCVCC(0:1) Encoding
PCCVCC(0:1) PC-Card
TABLE 4-13. PCCVPP(0:1) Encoding
PCCVPP(0:1) Card Hi-Z
Provided that power supply applied.
BCSR2 Board Control Status Register
BCSR2 status register which accessed offset from BCSR base address. read only register which read timeA. BCSR2's various fields described TABLE 4-14. "BCSR2 Description" page
Provided that BCSR disabled.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-14. BCSR2 Description
MNEMONIC FLASH_PD(4:1) Function Flash Presence Detect(4:1). These lines connected Flash SIMM presence detect lines which encode type Flash SIMM mounted Flash SIMM socket. There additional presence detect lines which encode SIMM's delay appear BCSR3. encoding FLASH_PD(4:1) TABLE 4-15. "Flash Presence Detect (4:1) Encoding" page Un-implemented Dram Presence Detect. These lines connected DRAM SIMM presence detect lines which encode size delay DRAM SIMM mounted DRAM SIMM socket. encoding DRAM_PD(4:1) TABLE 4-16. "DRAM Presence Detect (2:1) Encoding" page TABLE 4-17. "DRAM Presence Detect (4:3) Encoding" page ATT.
Reserved DRAM_PD(4:1)
used used Reserved Un-implemented.
TABLE 4-15. Flash Presence Detect (4:1) Encoding
FLASH_PD(4:1) Reserved SM732A2000 SM73228 Mbyte SIMM, SMART Modular Technologies. SM732A1000A SM73218 Mbyte SIMM, SMART Modular Technologies. MCM29080 MByte SIMM, Motorola MCM29040 MByte SIMM, Motorola MCM29020 MByte SIMM, Motorola Reserved FLASH TYPE SIZE
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-16. DRAM Presence Detect (2:1) Encoding
DRAM_PD(2:1) DRAM TYPE SIZE MCM36100 Motorola MT8D132X Micron- MByte SIMM MCM36800 Motorola MT16D832X Micron MByte SIMM MCM36400 Motorola MT8D432X Micron MByte SIMM MCM36200 Motorola MT16D832X Micron MByte SIMM
TABLE 4-17. DRAM Presence Detect (4:3) Encoding
DRAM_PD(4:3) DRAM DELAY Reserved Reserved nsec nsec
WARNING
Since EXTOLI(0:3) lines DRIVEN ('0') dip-switch, OFF-BOARD tools should NEVER DRIVE them HIGH. Failure doing might result PERMANENT DAMAGE OFF-BOARD logic.
BCSR3 Board Control Status Register
BCSR3 additional control status register which accessed offset from BCSR base address. BCSR3 gets defaults during Power-On reset read written time. description BCSR3 shown TABLE 4-18. "BCSR3 Description" page
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-18. BCSR3 Description
MNEMONIC Reserved Reserved CNT_REG_EN_P ROTECT Implemented Control Register Enable Protect. When this active (low) BCSR_EN that register written. When in-active, BCSR_EN written remove BCSR from memory map. After write BCSR1 this becomes active again. This write-only that register. Un-Implemented Flash Presence Detect(7:5). These lines connected Flash SIMM presence detect lines which encode Delay Flash SIMM mounted Flash SIMM socket U43. There additional presence detect lines which encode SIMM's Type appear BCSR2. encoding FLASH_PD(7:5) TABLE 4-19. "FLASH Presence Detect (7:5) Encoding" page Function '00' ATT.
Reserved Reserved FLASH_PD(7:5)
Reserved Reserved Reserved Implemented
TABLE 4-19. FLASH Presence Detect (7:5) Encoding
FLASH_PD(7:5) Flash Delay [nsec] Supported Supported
BCSR4 Board Control Status Register
BCSR4 serves control register ADS. accessed offset from BCSR base address. read written timeA. BCSR4 gets defaults upon Power-On reset. BCSR4 fields
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
described TABLE 4-20. "BCSR4 Description" page
TABLE 4-20. BCSR4 Description
MNEMONIC ETHLOOP Function Ethernet port Diagnostic Loop-Back. When active (high), MC68160 EEST configured into diagnostic Loop-Back mode, where transmit output internally back into receive section. Twisted Pair Full-Duplex. When active (low), MC68160 EEST into full-duplex mode, where, simultaneous receive transmit enabled. Twisted Pair Signal Quality Error Test Enable. When active (low), simulated collision state generated within EEST, collision detection circuitry within EEST tested. Signal Lamp. When this signal active (low), dedicated illuminates. When in-active, this darkened. This used signalling user. ATT.
TFPLDL~
TPSQEL~
SIGNAL_LAMP
used used used used. used used used used used Reserved Un-implemented
BCSR5 Board Control Status Register
BCSR5 serves control register ADS. accessed Address 0x2000300 CS5. written time. BCSR5 gets defaults upon Power-On reset. BCSR5 fields described TABLE 4-21. "BCSR5 Description" page
Provided that BCSR disabled.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-21. BCSR5 Description
MNEMONIC RESET_MII Function Reset Fast Ethernet phy. Driving this reset PHY. power reset this drive value poreset signal. Write 0x01 order reset phy. RX-signals three-state. driving this disable output fast ethernet signals. Write 0x02 order disable RX-Signals. Reset ATM25 phy. Driving this reset PHY. power reset this drive value poreset signal. Write 0x04 order reset phy. Reset ATM155 phy. Driving this reset PHY. power reset this drive value poreset signal. Write 0x08 order reset phy. Reset E1/T1 Framer. Driving this reset FRAMER. power reset this drive value poreset signal. Write 0x10 order reset framer. Write only
MII_RX_EN
Write only
RESET_ATM25
Write only
RESET_ATM155
Write only
RESET_Framer
Write only
used used used
Write only Write only Write only
Debug Port Controller
debug port MPC86xADS implemented on-board, connected JTAGA port. Since locationB debug port determined Hard-Reset configuration, important that relevant configuration bits (see "Reset Configuration" page changed, working with local debug port desired. debug port controller interfaced host computer Motorola's port, which 8-bit wide parallel port. Since debug port serial, conversion done hardware between parallel serial protocols. MPC's debug port configured SOFT-Reset "Asynchronous Clock Mode" i.e., debug port generates debug clock DSCK, which asynchronous with system clock. debug port controller block diagram shown FIGURE "Debug Port Controller Block Diagram" page
debug port location determined HARD Reset configuration. terms pins.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
FIGURE Debug Port Controller Block Diagram
Port Connector Debug Port Conn.
MPC86x Address Selection Handshake Logic Port Control HRESET* SRESET*
VFLS0 VFLS1 CHINS*(GND)
Control Status Register
Data Register Parallel Serial Converter
DSDI DSCK DSDO
allow external debug port controller incorporated with allow target system debug ADS, standard pin, debug port connector provided local debug port controller disabledA removing bundle from connector. When ADI's lead cable disconnected from either connector from ADS's connector, debug port controller disabled allowing either connection external debug port controller, independent run, i.e., boots from flash memory user's application without debug port controller intervention. This feature becomes especially handy regarding demo's. this state, VFLS(0:1) FRZB signals routed debug port connector, that, external debug port controller mode status information. supports upto boards connected same bundle. Address selection done 1,2,3. "ADI Port Address Selection" page debug port registers: control status register data register. control status register hold related control status functions, while data register serves parallel side Transmit Receive shift register. control status register accessed when D_C~ while data register accessed when D_C~ driven high host port.
MPC86xADS Debug Port Controller Target System
used debug port controller target system, provided that target system
I.e., debug port controller outputs tri-stated, allowing debug port driven external debug-tool. Depended settings.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
header connector matching ADS. this mode operation, on-board debug port controller, connected target system's debugport connector (see "Debug Port Connection Target System Requirements" below). Since DSDO signal driven MPC, must, remove local from socket, avoid contention over this line. When either local removed from socket daughter board removed from ADS, ADS's modules inaccessible, except debug-port controller. module-enable indications darkened, regardless their associated enable bits BCSR. Pull-up resistors connected ChipSelect lines, they float when removed from socket, avoiding possible contention over data-bus lines.
Debug Port Connection Target System Requirements
order target system connected ADS, debug port controller, measures need taken target system:
10-pin header connector should made available, with electrical connections matching FIGURE "Standard Debug Port Connector" page Pull-down resistors, app. should connected over DSDIA DSCKA signals. These resistors provide normalB operation, when debug-port controller, connected target system debug-port should enabled routed desired pins. DBGC DBPC fields within HARD-RESET configuration word.
Debug Port Control Status Register
control status register register (bit stands MSB). description control status register TABLE 4-22. "Debug Port Control Status Register" page
Remember that location DSDI DSCK determined HARD-Reset configuration. Normal i.e., boot CS0~.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-22. Debug Port Control Status Register
MNEMONIC
Function
ATT.
MpcRst TxError
Reset. When this status only indicates when active (high) that either SOFT HARD reset driven MPC. Transmit Error. When this status only active (high) indicates that last transmission towards MPC, internal MPC866 reset source. This updated each byte sent. Debug Mode. When this status only active (high) indicates that debug modea. Debug Clock Frequency Select. This field controls frequency divider which divides DSCK. division factors associated DSCK frequencies TABLE 4-23. "DSCK Frequency Select" below. Status Request. When host writes this active (low), will issue status read request host asserting ADS_REQ line host. When host writes control register with this negated, status read request issued. Upon reset this wakes-up active. Diagnostic Loopback Mode. When this control active (low) placed Diagnostic Loopback Mode. I.e., DSDI connected internally DSDO, DSDI tri-stated, each data byte sent data register, sampled back into receive shift register. This mode allows complete test, upto transmit receive shift registers. Upon reset this wakes-up active. Debug Mode Entry. When this active (low), will enter debug mode instantly after SOFT reset. When inactive, will start executing normally will enter debug mode only after exception. Upon reset this wakes-up active.
InDebug DebugClockFreq
'00'
StatusRequest
DiagLoopBack
DebugEntry
Provided that PCMCIA channel pins configured debug pins i.e, VFLS(0:1) signals available. not, debug port operated correctly.
TABLE 4-23. DSCK Frequency Select
DebugClockFreq DSCK Frequency [MHz]
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconductor, Inc.
Functional Description
TABLE 4-23. DSCK Frequency Select
DebugClockFreq DSCK Frequency [MHz] 1.25
FIGURE Standard Debug Port Connector
VFLS0 VFLS1 DSDI DSDO SRESET DSCK
HRESET
Standard MPCXXX Debug Port Connector Description
pins standard debug port connector maximal group needed support debug port controllers both MPC5XX MPC866 families. Some pins redundant MPC866 family necessary MPC5XX family.
VFLS(0:1)
These pins indicate debug port controller whether debug mode. When both VFLS(0:1) '1', debug mode. These lines serve alternate functions with MPC, which case needs selected, either target systemA.
HRESET*
This Hard-Reset bidirectional signal MPC. When this signal asserted (low) enters hard reset sequence which include hard reset configuration. This signal made redundant with MPC866 debug port controller since there hard-reset command integrated within debug port protocol. However, local debug port controller uses this signal compatibility with MPC5XX existing boards s/w.
SRESET*
This Soft-Reset bidirectional signal MPC866. MPC5XX output. debug port configuration sampled determined rising-edgeB SRESET* (for both processor families). MPC866 bidirectional signal which driven externally generate soft reset sequence. This signal fact redundant regarding MPC866 debug port controller since there soft-reset command integrated within debug port protocol. However, local debug port controller uses this signal compatibility with MPC5XX existing boards s/w.
DSDI Debug-port Serial Data
DSDI signal, debug port controller sends data MPC. DSDI serves also role
target system needs VFLS(0:1) alternate function, then, line should connected both VFLS(0:1) pins debug port connector. fact that configuration divided into parts, first sampled system clock cycles prior rising edge SRESET* second sampled clocks after that edge.
More Information This Product, www.freescale.com
Release
FreescaleMPC866ADS User's Manual Semiconduct
Other recent searches
VSC7303 - VSC7303 VSC7303 Datasheet
PWRLITE-LS1105N - PWRLITE-LS1105N PWRLITE-LS1105N Datasheet
MMSI023 - MMSI023 MMSI023 Datasheet
CAT32 - CAT32 CAT32 Datasheet
AN027002-0710 - AN027002-0710 AN027002-0710 Datasheet
2SB1240 - 2SB1240 2SB1240 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
