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DSP56362/D Rev. 02/2004 24-Bit Audio Digital Signal Processor
Motorola designed DSP56362 support digital audio applications requiring digital audio compression decompression, sound field processing, acoustic equalization, other digital audio algorithms. DSP56362 uses high performance, single-clock-per-cycle DSP56300 core family programmable CMOS digital signal processors (DSPs) combined with audio signal processing capability Motorola SymphonyDSP family, shown Figure This design provides two-fold performance increase over Motorola's popular Symphony family DSPs while retaining code compatibility. Significant architectural enhancements include barrel shifter, 24-bit addressing, instruction cache, direct memory access (DMA). DSP56362 offers million instructions second (MIPS) using internal clock
Program RAM/ Data Instruction Data Cache 5632 3072 5632 Program 6144 6144 Bootstrap
Triple Timer
(SPDIF)
Host Interface
ESAI
Memory Expansion Area
PIO_EB
PM_EB
XM_EB
Address Generation Unit Channel Unit
YM_EB
Peripheral Expansion Area
External Address Switch
Address
24-Bit DSP56300 Core
DRAM/SRAM Interface Cache Control Control
Internal Data Switch
EXTAL
External Data Switch
Data
Clock Generator
Program Interrupt Controller
Program Decode Controller MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
Program Address Generator
CLKOUT
Data 56-bit 56-bit Accumulators 56-bit Barrel Shifter
Power Mngmnt.
JTAG OnCE
RESET PINIT/NMI
AA0456G
Figure DSP56362 Block Diagram
This document contains information product. Specifications information herein subject change without notice.
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SIGNAL/CONNECTION DESCRIPTIONS SPECIFICATIONS PACKAGING DESIGN CONSIDERATIONS ORDERING INFORMATION POWER CONSUMPTION BENCHMARK IBIS MODEL INDEX INDEX-I
TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses following conventions:
OVERBAR "asserted" "deasserted" Examples: Used indicate signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/Symbol
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage* VIL/VOL VIH/VOH VIH/VOH VIL/VOL
*Values VIL, VOL, VIH, defined individual product specifications.
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OVERVIEW
FEATURES
Multimode, multichannel decoder software functionality Dolby Digital Logic MPEG2 Bass management
Digital audio post-processing capabilities Virtual surround sound Lucasfilm THX5.1 Soundfield processing Equalization
Digital Signal Processing Core MIPS with clock Object code compatible with DSP56000 core Highly parallel instruction Data arithmetic logic unit (ALU) Fully pipelined 24-bit parallel multiplier-accumulator (MAC) 56-bit parallel barrel shifter (fast shift normalization; stream generation parsing) Conditional instructions 24-bit 16-bit arithmetic support under software control Position independent code (PIC) support Addressing modes optimized applications (including immediate offsets) On-chip instruction cache controller On-chip memory-expandable hardware stack Nested hardware loops Fast auto-return interrupts channels supporting internal external accesses One-, two-, three- dimensional transfers (including circular buffering)
Program control unit (PCU)
Direct memory access (DMA)
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Overview Features
End-of-block-transfer interrupts Triggering from interrupt lines peripherals Software programmable PLL-based frequency synthesizer core clock Allows change low-power divide factor (DF) without loss lock Output clock with skew elimination On-Chip Emulation (OnCE`) module Joint Action Test Group (JTAG) test access port (TAP) Address trace mode reflects internal program accesses external port
Phase-locked loop (PLL)
Hardware debugging support
On-Chip Memories Modified Harvard architecture allows simultaneous access program data memories 30720 24-bit on-chip program ROM1 (disabled 16-bit compatibility mode) 6144 24-bit on-chip X-data ROM1 6144 24-bit on-chip Y-data ROM1 Program RAM, instruction cache, data RAM, data sizes programmable
Instruction Cache Disabled Enabled Disabled Enabled
Switch Mode Disabled Disabled Enabled Enabled
Program Size 3072 24-bit 2048 24-bit 5120 24-bit 4096 24-bit
Instruction Cache Size 1024 24-bit 1024 24-bit
Data Size 5632 24-bit 5632 24-bit 5632 24-bit 5632 24-bit
Data Size 5632 24-bit 5632 24-bit 3584 24-bit 3584 24-bit
24-bit bootstrap (disabled sixteen-bit compatibility mode) Data memory expansion 256K 24-bit word memory memory using SRAM. Data memory expansion 24-bit word memory memory using DRAM. External memory expansion port( twenty-four data pins high speed external memory access allowing large number external accesses sample) Chip select logic glueless interface SRAMs On-chip DRAM controller glueless interface DRAMs Enhanced serial audio interface (ESAI) includes: serial data lines, selectable receive transmit transmit only. Master slave capability I2S, Sony, AC97, other audio protocol implementations
Off-Chip Memory Expansion
Peripheral Support Circuits
1.These ROMs factory programmed with data programs provided application developer.
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Overview Documentation
Serial host interface (SHI) features: protocol with multi-master capability protocol with single-master capability Ten-word receive FIFO Support 16-, 24-bit words.
Byte-wide parallel host interface (HDI08) with support features serial transmitter capable supporting S/PDIF, IEC958, IEC1937, CP-340, AES/EBU digital audio formats; alternate configuration supports GPIO lines Triple timer module with single external interface GPIO line On-chip peripheral registers memory mapped data memory space Very low-power (3.3 CMOS design Wait stop low-power standby modes Fully-static logic, operation frequency down (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, mode-dependent)
Reduced Power Dissipation
Package
144-pin plastic thin quad flat pack (LQFP) surface-mount package
DOCUMENTATION
Table lists documents that provide complete description DSP56362 required design properly with part. Documentation available from local Motorola distributor, Motorola semiconductor sales office, Motorola Literature Distribution Center, through Motorola home page Internet (the source latest information).
Table
Document Name DSP56300 Family Manual
DSP56362 Documentation
Description Order Number DSP56300FM/AD
Detailed description 56000-family architecture 24-bit core processor instruction Detailed description memory, peripherals, interfaces
DSP56362 User's Manual
DSP56362UM/AD DSP56362/D
DSP56362 Advance Information Electrical timing specifications; package descriptions There also product brief this chip. DSP56362 Product Brief Brief description chip
DSP56362P/D
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SECTION SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
input output signals DSP56362 organized into functional groups, which listed Table illustrated Figure 1-1.
DSP56362 operated from supply; however, some inputs tolerate special notice this feature added signal descriptions those inputs.
Table DSP56362 Functional Signal Groupings
Functional Group Power (VCC) Ground (GND) Clock Address Data control Interrupt mode control HDI08 ESAI Digital audio transmitter (DAX) Timer JTAG/OnCE Port Port Port Port Port Number Signals Detailed Description Table Table Table Table Table Table Table Table Table 1-10 Table 1-11 Table 1-12 Table 1-13 Table 1-14
Port external memory interface port, including external address bus, data bus, control signals. Port signals GPIO port signals which multiplexed with HDI08 signals. Port signals GPIO port signals which multiplexed with ESAI signals. Port signals GPIO port signals which multiplexed with signals.
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Signal/Connection Descriptions Signal Groupings
DSP56362
VCCP VCCQH VCCQL VCCA VCCD VCCC VCCH VCCS
GNDP
Power Inputs: External Internal Logic Address Data Control HDI08 SHI/ESAI/DAX/Timer Grounds: Internal Logic Address Data Control HDI08 SHI/ESAI/DAX/Timer
Host Interface (HDI08) Port1
GNDQ GNDA GNDD GNDC GNDH GNDS EXTAL CLKOUT PCAP PINIT/NMI
GNDP1
NonMultiplexed H0-H7 HCS/HCS Single HDS/HDS Single HOREQ/HOREQ HACK/HACK Mode MOSI MISO HREQ
Multiplexed HAD0-HAD7 HAS/HAS HA10 Double HRD/HRD HWR/HWR Double HTRQ/HTRQ HRRQ/HRRQ
Port GPIO PB0-PB7 PB10 PB13 PB11 PB12 PB14 PB15
Serial Host Interface (SHI)
Mode HREQ Port GPIO PC10 PC11 Port GPIO Timer GPIO TIO0
Clock
Port
A0-A17 D0-D23 AA0-AA3/ RAS0-RAS3 MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET Notes: External Address External Data External Control Digital Audio Transmitter (DAX)2 Timer Interrupt/ Mode Control Enhanced Serial Audio Interface (ESAI)2
SCKR HCKR SCKT HCKT SDO5/SDI0 SDO4/SDI1 SDO3/SDI2 SDO2/SDI3 SDO1 SDO0
TIO0
TRST AA0601 HDI08 port supports nonmultiplexed multiplexed bus, single double data strobe (DS), single double host request (HR) configurations. Since each these modes configured independently, combination these modes possible. These HDI08 signals also configured alternately GPIO signals (PB0-PB15). Signals with dual designations (e.g., HAS/HAS) have configurable polarity. ESAI signals multiplexed with port GPIO signals (PC0-PC11). signals multiplexed with Port GPIO signals (PD0-PD1). timer signal configured alternately timer GPIO signal (TIO0). JTAG/ OnCE Port
Figure Signals Identified Functional Group
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Signal/Connection Descriptions Power
POWER
Table Power Inputs
Power Name VCCP Description Power-VCCP dedicated use. voltage should wellregulated input should provided with extremely impedance path power rail. There VCCP input. Quiet Core (Low) Power-VCCQL isolated power core processing logic. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCQ inputs. Quiet External (High) Power-VCCQH quiet power source lines. This input must tied externally other chip power inputs. user must provide adequate decoupling capacitors. There three VCCQH inputs. Address Power-VCCA isolated power sections address drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There three VCCA inputs. Data Power-VCCD isolated power sections data drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCD inputs. Control Power-VCCC isolated power control drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCC inputs. Host Power-VCCH isolated power HDI08 drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCH input. SHI, ESAI, DAX, Timer Power-VCCS isolated power SHI, ESAI, DAX, Timer drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCS inputs.
VCCQL
VCCQH
VCCA
VCCD
VCCC
VCCH
VCCS
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Signal/Connection Descriptions Ground
GROUND
Table Grounds
Ground Name Description Ground-GNDP ground dedicated use. connection should provided with extremely low-impedance path ground. VCCP should bypassed GNDP 0.47 capacitor located close possible chip package. There GNDP connection. Ground 1-GNDP1 ground dedicated use. connection should provided with extremely low-impedance path ground. There GNDP1 connection. Quiet Ground-GNDQ isolated ground internal processing logic. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDQ connections. Address Ground-GNDA isolated ground sections address drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDA connections. Data Ground-GNDD isolated ground sections data drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDD connections. Control Ground-GNDC isolated ground control drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDC connections. Host Ground-GNDH isolated ground HDI08 drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDH connection. SHI, ESAI, DAX, Timer Ground-GNDS isolated ground SHI, ESAI, DAX, Timer drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDS connections.
GNDP
GNDP1
GNDQ
GNDA
GNDD
GNDC
GNDH
GNDS
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Signal/Connection Descriptions Clock
CLOCK
Table Clock Signals
Signal Name Type State during Reset Signal Description External Clock Input-An external clock source must connected EXTAL order supply clock internal clock generator PLL. This input cannot tolerate Clock Output-CLKOUT provides output clock synchronized internal core clock phase. enabled both multiplication division factors equal one, then CLKOUT also synchronized EXTAL. disabled, CLKOUT frequency half frequency EXTAL. CLKOUT functional frequencies above. Capacitor-PCAP input connecting off-chip capacitor filter. Connect capacitor terminal PCAP other terminal VCCP. used, PCAP tied VCC, GND, left floating. Initial/Non maskable Interrupt-During assertion RESET, value PINIT/NMI written into Enable (PEN) control register, determining whether enabled disabled. After RESET deassertion during normal instruction processing, PINIT/NMI Schmitttrigger input negative-edge-triggered maskable interrupt (NMI) request internally synchronized CLKOUT. PINIT/NMI cannot tolerate
EXTAL
Input
Input
CLKOUT
Output
Chip-driven
PCAP
Input
Input
PINIT/
Input
Input
EXTERNAL MEMORY EXPANSION PORT (PORT
When DSP56362 enters low-power standby mode (stop wait), releases mastership tristates relevant port signals: A0-A17, D0-D23, AA0/RAS0-AA3/RAS3, CAS.
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Signal/Connection Descriptions External Memory Expansion Port (Port
External Address
Table External Address Signals
Signal Name Type State during Reset Signal Description Address Bus-When master, A0-A17 active-high outputs that specify address external program data memory accesses. Otherwise, signals tri-stated. minimize power dissipation, A0-A17 change state when external memory spaces being accessed.
A0-A17
Output
Tri-stated
External Data
Table External Data Signals
Signal Name Type State during Reset Signal Description Data Bus-When master, D0-D23 active-high, bidirectional input/ outputs that provide bidirectional data external program data memory accesses. Otherwise, D0-D23 tri-stated.
D0-D23
Input/Output
Tri-stated
External Control
Table External Control Signals
Signal Name Type State during Reset Signal Description Address Attribute Address Strobe-When defined these signals used chip selects additional address lines. When defined RAS, these signals used DRAM interface. These signals tri-stated outputs with programmable polarity.
AA0-AA3/ RAS0- RAS3
Output
Tri-stated
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Signal/Connection Descriptions External Memory Expansion Port (Port Table External Control Signals (Continued)
Signal Name Type State during Reset Signal Description Column Address Strobe-When master, active-low output used DRAM strobe column address. Otherwise, mastership enable (BME) DRAM control register cleared, signal tri-stated. Read Enable-When master, active-low output that asserted read external memory data (D0-D23). Otherwise, tristated. Write Enable-When master, active-low output that asserted write external memory data (D0-D23). Otherwise, signals tri-stated. Transfer Acknowledge-If DSP56362 master there external activity, DSP56362 master, input ignored. input data transfer acknowledge (DTACK) function that extend external cycle indefinitely. number wait states .infinity) added wait states inserted keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. current cycle completes clock period after asserted synchronous CLKOUT. number wait states determined input control register (BCR), whichever longer. used minimum number wait states external cycles. order functionality, must programmed least wait state. zero wait state access cannot extended deassertion, otherwise improper operation result. operate synchronously asynchronously, depending setting operating mode register (OMR). functionality used while performing DRAM type accesses, otherwise improper operation result.
Output
Tri-stated
Output
Tri-stated
Output
Tri-stated
Input
Ignored Input
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Signal/Connection Descriptions External Memory Expansion Port (Port Table External Control Signals (Continued)
Signal Name Type State during Reset Signal Description Request-BR active-low output, never tristated. asserted when requests mastership. deasserted when longer needs bus. asserted deasserted independent whether DSP56362 master slave. "parking" allows deasserted even though DSP56362 master. (See description "parking" signal description.) request hold (BRH) allows asserted under software control even though does need bus. typically sent external arbitrator that controls priority, parking, tenure each master same external bus. only affected requests external bus, never internal bus. During hardware reset, deasserted arbitration reset slave state. Grant-BG active-low input. asserted external arbitration circuit when DSP56362 becomes next master. When asserted, DSP56362 must wait until deasserted before taking mastership. When deasserted, mastership typically given current cycle. This occur middle instruction that requires more than external cycle execution. default mode operation this signal requires setup hold time referred CLKOUT. CLKOUT operation guaranteed from 100MHz asynchronous arbitration must used clock frequencies 100MHz above. asynchronous arbitration enabled setting register.
Output
Output (deasserted)
Input
Ignored Input
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Signal/Connection Descriptions External Memory Expansion Port (Port Table External Control Signals (Continued)
Signal Name Type State during Reset Signal Description Busy-BB bidirectional active-low input/output. indicates that active. Only after deasserted pending master become master (and then assert signal again). master keep asserted after ceasing activity regardless whether asserted deasserted. This called "bus parking" allows current master reuse without rearbitration until another device requires bus. deassertion done "active pull-up" method (i.e., driven high then released held high external pull-up resistor). default mode operation this signal requires setup hold time referred CLKOUT. CLKOUT operation guaranteed from 100MHz asynchronous arbitration must used clock frequencies 100MHz above. asynchronous arbitration enabled setting register. requires external pull-up resistor.
Input/ Output
Input
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Signal/Connection Descriptions Interrupt Mode Control
INTERRUPT MODE CONTROL
interrupt mode control signals select chip's operating mode comes hardware reset. After RESET deasserted, these inputs hardware interrupt request lines.
Table Interrupt Mode Control
Signal Name Type State during Reset Signal Description Mode Select A/External Interrupt Request MODA/IRQA active-low Schmitt-trigger input, internally synchronized clock. MODA/IRQA selects initial chip operating mode during hardware reset becomes level-sensitive negative-edgetriggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. IRQA asserted synchronous CLKOUT, multiple processors resynchronized using WAIT instruction asserting IRQA exit wait state. processor stop standby state MODA/IRQA pulled GND, processor will exit stop state. This input tolerant. Mode Select B/External Interrupt Request MODB/IRQB active-low Schmitt-trigger input, internally synchronized clock. MODB/IRQB selects initial chip operating mode during hardware reset becomes level-sensitive negative-edgetriggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. IRQB asserted synchronous CLKOUT, multiple processors re-synchronized using WAIT instruction asserting IRQB exit wait state. This input tolerant.
MODA/IRQA
Input
Input
MODB/IRQB
Input
Input
1-10
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Signal/Connection Descriptions Interrupt Mode Control Table Interrupt Mode Control (Continued)
Signal Name Type State during Reset Signal Description Mode Select C/External Interrupt Request MODC/IRQC active-low Schmitt-trigger input, internally synchronized clock. MODC/IRQC selects initial chip operating mode during hardware reset becomes level-sensitive negative-edgetriggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. IRQC asserted synchronous CLKOUT, multiple processors resynchronized using WAIT instruction asserting IRQC exit wait state. This input tolerant. Mode Select D/External Interrupt Request MODD/IRQD active-low Schmitt-trigger input, internally synchronized clock. MODD/IRQD selects initial chip operating mode during hardware reset becomes level-sensitive negative-edgetriggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. IRQD asserted synchronous CLKOUT, multiple processors resynchronized using WAIT instruction asserting IRQD exit wait state. This input tolerant.
MODC/IRQC
Input
Input
MODD/IRQD
Input
Input
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1-11
Signal/Connection Descriptions Host Interface (HDI08) Table Interrupt Mode Control (Continued)
Signal Name Type State during Reset Signal Description Reset-RESET active-low, Schmitt-trigger input. When asserted, chip placed reset state internal phase generator reset. Schmitttrigger input allows slowly rising input (such capacitor charging) reset chip reliably. RESET deasserted synchronous CLKOUT, exact start-up timing guaranteed, allowing multiple processors start synchronously operate together "lockstep." When RESET signal deasserted, initial chip operating mode latched from MODA, MODB, MODC, MODD inputs. RESET signal must asserted during power stable EXTAL signal must supplied while RESET being asserted. This input tolerant.
RESET
Input
Input
HOST INTERFACE (HDI08)
HDI08 provides fast, 8-bit, parallel data port that connected directly host bus. HDI08 supports variety standard buses directly connected number industry standard microcomputers, microprocessors, DSPs, hardware.
Host Port Configuration
Signal functions associated with HDI08 vary according interface operating mode determined HDI08 port control register (HPCR). 6.5.6 Host Port Control Register (HPCR) page Section 6-13 detailed descriptions this register (See Host Interface (HDI08) page Section 6-1.) descriptions other HDI08 configuration registers.
1-12
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Signal/Connection Descriptions Host Interface (HDI08) Table Host Interface
Signal Name Type State during Reset Signal Description Host Data-When HDI08 programmed interface nonmultiplexed host function selected, these signals lines bidirectional, tri-state data bus. Host Address-When HDI08 programmed interface multiplexed host function selected, these signals lines address/data bidirectional, multiplexed, tristate bus. Port 0-7-When HDI08 configured GPIO, these signals individually programmable input, output, internally disconnected. default state after reset these signals GPIO disconnected. This input tolerant. Host Address Input 0-When HDI08 programmed interface nonmultiplexed host function selected, this signal line host address input bus. Host Address Strobe-When HDI08 programmed interface multiplexed host function selected, this signal host address strobe (HAS) Schmitt-trigger input. polarity address strobe programmable, configured active-low (HAS) following reset. Port 8-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
H0-H7
Input/ output
HAD0- HAD7
Input/ output
GPIO disconnected
PB0-PB7
Input, output, disconnected
Input
Input HAS/ GPIO disconnected
Input, output, disconnected
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1-13
Signal/Connection Descriptions Host Interface (HDI08) Table Host Interface (Continued)
Signal Name Type State during Reset Signal Description Host Address Input 1-When HDI08 programmed interface nonmultiplexed host function selected, this signal line host address (HA1) input bus. Host Address 8-When HDI08 programmed interface multiplexed host function selected, this signal line host address (HA8) input bus. Port 9-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant. Host Address Input 2-When HDI08 programmed interface non-multiplexed host function selected, this signal line host address (HA2) input bus. Host Address 9-When HDI08 programmed interface multiplexed host function selected, this signal line host address (HA9) input bus. Port 10-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. PB10 Input, Output, Disconnected default state after reset this signal GPIO disconnected. This input tolerant.
Input
Input
GPIO disconnected
Input, output, disconnected
Input
Input
GPIO disconnected
1-14
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Signal/Connection Descriptions Host Interface (HDI08) Table Host Interface (Continued)
Signal Name Type State during Reset Signal Description Host Read/Write-When HDI08 programmed interface single-data-strobe host function selected, this signal Host Read/Write (HRW) input. Host Read Data-When HDI08 programmed interface double-data-strobe host function selected, this signal host read data strobe (HRD) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HRD) after reset. Port 11-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. PB11 Input, Output, Disconnected default state after reset this signal GPIO disconnected. This input tolerant. Host Data Strobe-When HDI08 programmed interface single-data-strobe host function selected, this signal host data strobe (HDS) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HDS) following reset. Host Write Data-When HDI08 programmed interface double-data-strobe host function selected, this signal host write data strobe (HWR) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HWR) following reset. Port 12-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. PB12 Input, output, disconnected default state after reset this signal GPIO disconnected. This input tolerant.
Input
Input
HRD/
GPIO disconnected
Input HDS/
Input HWR/
GPIO disconnected
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1-15
Signal/Connection Descriptions Host Interface (HDI08) Table Host Interface (Continued)
Signal Name Type State during Reset Signal Description Host Chip Select-When HDI08 programmed interface nonmultiplexed host function selected, this signal host chip select (HCS) input. polarity chip select programmable, configured active-low (HCS) after reset. Host Address 10-When HDI08 programmed interface multiplexed host function selected, this signal line host address (HA10) input bus. Port 13-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant. Host Request-When HDI08 programmed interface single host request host function selected, this signal host request (HOREQ) output. polarity host request programmable, configured active-low (HOREQ) following reset. host request programmed driven open-drain output. Transmit Host Request-When HDI08 programmed interface double host request host function selected, this signal transmit host request (HTRQ) output. polarity host request programmable, configured active-low (HTRQ) following reset. host request programmed driven open-drain output. Port 14-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. PB14 Input, output, disconnected default state after reset this signal GPIO disconnected. This input tolerant.
Input
Input HA10
GPIO disconnected
PB13
Input, output, disconnected
Output HOREQ/ HOREQ
Output HTRQ/ HTRQ GPIO disconnected
1-16
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Signal/Connection Descriptions Host Interface (HDI08) Table Host Interface (Continued)
Signal Name Type State during Reset Signal Description Host Acknowledge-When HDI08 programmed interface single host request host function selected, this signal host acknowledge (HACK) Schmitttrigger input. polarity host acknowledge programmable, configured active-low (HACK) after reset. Receive Host Request-When HDI08 programmed interface double host request host function selected, this signal receive host request (HRRQ) output. polarity host request programmable, configured active-low (HRRQ) after reset. host request programmed driven open-drain output. Port 15-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
Input HACK/ HACK
Output HRRQ/ HRRQ GPIO disconnected
PB15
Input, output, disconnected
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1-17
Signal/Connection Descriptions Serial Host Interface
SERIAL HOST INTERFACE
five signals that configured allow operate either mode.
Table 1-10 Serial Host Interface Signals
Signal Name Signal Type State during Reset Signal Description
Input output
Tri-stated
Serial Clock-The signal output when configured master Schmitt-trigger input when configured slave. When configured master, signal derived from internal clock generator. When configured slave, signal input, clock signal from external master synchronizes data transfer. signal ignored defined slave slave select (SS) signal asserted. both master slave devices, data shifted edge signal sampled opposite edge where data stable. Edge polarity determined transfer protocol. Serial Clock-SCL carries clock transactions mode. Schmitttrigger input when configured slave open-drain output when configured master. should connected through pull-up resistor. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
Input output
1-18
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Signal/Connection Descriptions Serial Host Interface Table 1-10 Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description
MISO
Input output
Master-In-Slave-Out-When configured master, MISO master data input line. MISO signal used conjunction with MOSI signal transmitting receiving serial data. This signal Schmitt-trigger input when configured Master mode, output when configured Slave mode, tri-stated configured Slave mode when deasserted. external pull-up resistor required operation. Data Acknowledge-In mode, Schmitt-trigger input when receiving opendrain output when transmitting. should connected through pull-up resistor. carries data transactions. data must stable during high period SCL. data only allowed change when low. When free, high. line only allowed change during time high case start stop events. high-to-low transition line while high unique situation, defined start event. low-to-high transition while high unique situation defined stop event. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
Tri-stated
Input open-drain output
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Signal/Connection Descriptions Serial Host Interface Table 1-10 Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description
MOSI
Input output
Master-Out-Slave-In-When configured master, MOSI master data output line. MOSI signal used conjunction with MISO signal transmitting receiving serial data. MOSI slave data input line when configured slave. This signal Schmitt-trigger input when configured Slave mode. Tri-stated Slave Address 0-This signal uses Schmitttrigger input when configured mode. When configured slave mode, signal used form slave device address. ignored when configured master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant. Slave Select-This signal active Schmitt-trigger input when configured mode. When configured Slave mode, this signal used enable slave transfer. When configured master mode, this signal should kept deasserted (pulled high). asserted while configured master, error condition flagged. deasserted, ignores clocks keeps MISO output signal high-impedance state. Tri-stated Slave Address 2-This signal uses Schmitttrigger input when configured mode. When configured Slave mode, signal used form slave device address. ignored master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
Input
Input
Input
1-20
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Signal/Connection Descriptions Serial Host Interface Table 1-10 Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description
Host Request-This signal active Schmitt-trigger input when configured master mode active output when configured slave mode. When configured slave mode, HREQ asserted indicate that ready next data word transfer deasserted first clock pulse data word transfer. When configured master mode, HREQ input. When asserted external slave device, will trigger start data word transfer master. After finishing data word transfer, master will await next assertion HREQ proceed next transfer. This signal tri-stated during hardware, software, personal reset, when HREQ1-HREQ0 bits HCSR cleared. There need external pull-up this state. This input tolerant.
HREQ
Input Output
Tri-stated
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Signal/Connection Descriptions Enhanced Serial Audio Interface
ENHANCED SERIAL AUDIO INTERFACE
Table 1-11 Enhanced Serial Audio Interface Signals
Signal Name Signal Type State during Reset Signal Description High Frequency Clock Receiver-When programmed input, this signal provides high frequency clock source ESAI receiver alternate core clock. When programmed output, this signal serve highfrequency sample clock (e.g., external digital analog converters [DACs]) additional system clock. Port 2-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. High Frequency Clock Transmitter-When programmed input, this signal provides high frequency clock source ESAI transmitter alternate core clock. When programmed output, this signal serve high frequency sample clock (e.g., external DACs) additional system clock. Port 5-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
HCKR
Input output
GPIO disconnected Input, output, disconnected
HCKT
Input output
GPIO disconnected Input, output, disconnected
1-22
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Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Frame Sync Receiver-This receiver frame sync input/output signal. asynchronous mode (SYN=0), operates frame sync input output used enabled receivers. synchronous mode (SYN=1), operates either serial flag (TEBE=0), transmitter external buffer enable control (TEBE=1, RFSD=1). When this configured serial flag pin, direction determined RFSD RCCR register. When configured output flag OF1, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF1, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Port 1-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Frame Sync Transmitter-This transmitter frame sync input/output signal. synchronous mode, this signal frame sync both transmitters receivers. asynchronous mode, frame sync transmitters only. direction determined transmitter frame sync direction (TFSD) ESAI transmit clock control register (TCCR). Port 4-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Input output
GPIO disconnected
Input, output, disconnected
Input output
GPIO disconnected Input, output, disconnected
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Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Receiver Serial Clock-SCKR provides receiver serial clock ESAI. SCKR operates clock input output used enabled receivers asynchronous mode (SYN=0), serial flag synchronous mode (SYN=1). When this configured serial flag pin, direction determined RCKD RCCR register. When configured output flag OF0, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF0, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Port 0-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Transmitter Serial Clock-This signal provides serial rate clock ESAI. SCKT clock input output used enabled transmitters receivers synchronous mode, enabled transmitters asynchronous mode. GPIO disconnected Input, output, disconnected Port 3-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
SCKR
Input output
GPIO disconnected
Input, output, disconnected
SCKT
Input output
1-24
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Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Serial Data Output 5-When programmed transmitter, SDO5 used transmit data from serial transmit shift register. Serial Data Input 0-When programmed receiver, SDI0 used receive serial data into serial receive shift register. Port 6-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Serial Data Output 4-When programmed transmitter, SDO4 used transmit data from serial transmit shift register. Serial Data Input 1-When programmed receiver, SDI1 used receive serial data into serial receive shift register. Port 7-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Output SDO5 Input SDI0
GPIO disconnected
Input, output, disconnected
Output SDO4 Input SDI1 Input, output, disconnected
GPIO disconnected
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Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Serial Data Output 3-When programmed transmitter, SDO3 used transmit data from serial transmit shift register. Serial Data Input 2-When programmed receiver, SDI2 used receive serial data into serial receive shift register. Port 8-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Serial Data Output 2-When programmed transmitter, SDO2 used transmit data from serial transmit shift register. Serial Data Input 3-When programmed receiver, SDI3 used receive serial data into serial receive shift register. Port 9-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Serial Data Output 1-SDO1 used transmit data from serial transmit shift register. Output SDO1 PC10 Input, output, disconnected GPIO disconnected Port 10-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Output SDO3 Input SDI2
GPIO disconnected
Input, output, disconnected
Output SDO2 Input SDI3 Input, output, disconnected
GPIO disconnected
1-26
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Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Serial Data Output 0-SDO0 used transmit data from serial transmit shift register. Output SDO0 PC11 Input, output, disconnected GPIO disconnected Port 11-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
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Signal/Connection Descriptions Digital Audio Interface (DAX)
DIGITAL AUDIO INTERFACE (DAX)
Table 1-12 Digital Audio Interface (DAX) Signals
Signal Name Type State During Reset Signal Description Audio Clock Input-This clock input. When programmed external clock, this input supplies clock. external clock frequency must 256, 384, times audio sampling frequency (256 respectively). Disconnecte Input, output, disconnected Port 0-When configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Digital Audio Data Output-This signal audio non-audio output form AES/EBU, CP340 IEC958 data biphase mark format. Disconnecte Port 1-When configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Input
Output Input, output, disconnected
1-28
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Signal/Connection Descriptions Timer
TIMER
Table 1-13 Timer Signal
Signal Name Type State during Reset Signal Description Timer Schmitt-Trigger Input/Output-When timer functions external event counter measurement mode, TIO0 used input. When timer functions watchdog, timer, pulse modulation mode, TIO0 used output.
TIO0
Input Output
Input
default mode after reset GPIO input. This changed output configured timer input/output through timer control/ status register (TCSR0). TIO0 being used, recommended either define GPIO output immediately beginning operation leave defined GPIO input connected through pull-up resistor order ensure stable logic level input. This input tolerant.
JTAG/OnCE INTERFACE
Table 1-14 JTAG/OnCEInterface
Signal Name Type State during Reset Signal Description Test Clock-TCK test clock input signal used synchronize JTAG test logic. internal pull-up resistor. This input tolerant. Test Data Input-TDI test data serial input signal used test instructions data. sampled rising edge internal pull-up resistor. This input tolerant. Tristated Test Data Output-TDO test data serial output signal used test instructions data. tri-stated actively driven shift-IR shift-DR controller states. changes falling edge TCK.
Input
Input
Input
Input
Output
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Signal/Connection Descriptions JTAG/OnCE Interface Table 1-14 JTAG/OnCEInterface (Continued)
Signal Name Type State during Reset Signal Description Test Mode Select-TMS input signal used sequence test controller's state machine. sampled rising edge internal pull-up resistor. This input tolerant. Test Reset-TRST active-low Schmitt-trigger input signal used asynchronously initialize test controller. TRST internal pull-up resistor. TRST Input Input TRST recommended designs. recommended leave TRST disconnected. This input tolerant. Debug Event-DE open-drain, bidirectional, active-low signal providing, input, means entering debug mode operation from external command controller, and, output, means acknowledging that chip entered debug mode. This signal, when asserted input, causes DSP56300 core finish current instruction being executed, save instruction pipeline information, enter debug mode, wait commands entered from debug serial input line. This signal asserted output three clock cycles when chip enters debug mode result debug request result meeting breakpoint condition. internal pull-up resistor. This standard part JTAG controller. signal connects directly OnCE module initiate debug mode directly provide direct external indication that chip entered debug mode. other interface with OnCE module must occur through JTAG port. recommended designs. recommended leave disconnected. This input tolerant.
Input
Input
Input/ Output
Input
1-30
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SECTION SPECIFICATIONS
INTRODUCTION
DSP56362 fabricated high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs outputs. DSP56362 specifications preliminary from design simulations, fully tested guaranteed. Finalized specifications will published after full characterization device qualifications complete.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields. However, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability operation enhanced unused inputs pulled appropriate logic voltage level (e.g., either VCC). suggested value pullup pulldown resistor
Note:
calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification will never occur same device that "minimum" value another specification; adding maximum minimum represents condition that never exist.
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Specifications Thermal Characteristics Table Maximum Ratings
Rating1 Supply Voltage input voltages excluding tolerant" inputs3 tolerant" input voltages3 Current drain excluding Symbol VIN5 TSTG Value1, Unit
-0.3 +4.0
-0.3 -0.3 3.95
Operating temperature range Storage temperature
Notes:
+105 +125
.16V, +100°C, Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond maximum rating affect device reliability cause permanent damage device. CAUTION: Tolerant" input voltages must more than 3.95 greater than supply voltage; this restriction applies "power on", well during normal operation. case, input voltages cannot more than 5.75 Tolerant" inputs inputs that tolerate
THERMAL CHARACTERISTICS
Table Thermal Characteristics
Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter
Notes:
Symbol
LQFP Value 45.3 10.1
Unit °C/W °C/W °C/W
Junction-to-ambient thermal resistance based measurements horizontal singlesided printed circuit board SEMI G38-87 natural convection.(SEMI Semiconductor Equipment Materials International, East Middlefield Rd., Mountain View, 94043, (415) 964-5111.) Measurements were done with parts mounted thermal test boards conforming specification EIA/JESD51-3. Junction-to-case thermal resistance based measurements using cold plate SEMI G30-88, with exception that cold plate temperature used case temperature.
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Specifications Electrical Characteristics
ELECTRICAL CHARACTERISTICS
Table Electrical Characteristics6
Characteristics Supply voltage Input high voltage D(0:23), PINIT/ VIHP 3.95 3.95 Symbol 3.14 3.46 Unit
MOD1/IRQ1, RESET, TCK/TDI/ TMS/TRST/ESAI/Timer/HDI08/ SHI(SPI mode) pins SHI(I2C mode) pins EXTAL8 Input voltage D(0:23), MOD1/IRQ1, RESET, PINIT/NMI JTAG/ESAI/Timer/HDI08/ SHI(SPI mode) pins SHI(I2C mode) pins EXTAL
VIHX
VILP
-0.3 -0.3 -0.3
VILX ITSI
-0.3
Input leakage current High impedance (off-state) input current Output high voltage (IOH -0.4 mA)5,7 CMOS (IOH µA)5 Output voltage (IOL open-drain pins mA)5,7 CMOS (IOL µA)5 Internal supply current2: (Operating frequency 100MHz current measurements) Normal mode Wait mode
0.01
0.01
ICCI ICCW
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Specifications Electrical Characteristics Table Electrical Characteristics6 (Continued)
Characteristics Stop mode4 supply current Input capacitance5
Notes:
Symbol ICCS
Unit
Refers MODA/IRQA, MODB/IRQB, MODC/IRQC, MODD/IRQD pins Power Consumption Considerations page provides formula compute estimated current requirements Normal mode. order obtain these results, inputs must terminated (i.e., allowed float). Measurements based synthetic intensive benchmarks. power consumption numbers this specification measured results this benchmark. This reflects typical applications. Typical internal supply current measured with 3.3V 100°C. Maximum internal supply current measured with 3.46 100°C. Deleted. order obtain these results, inputs, which disconnected Stop mode, must terminated (i.e., allowed float). Periodically sampled 100% tested +100°C, This characteristic does apply PCAP. Driving EXTAL VIHX high VILX value cause additional power consumption current). minimize power consumption, minimum VIHX should lower than maximum VILX should higher than VCC.
ELECTRICAL CHARACTERISTICS
timing waveforms shown electrical characteristics section tested with maximum minimum pins except EXTAL, which tested using input levels shown Note previous table. timing specifications, which referenced device input signal, measured production with respect point respective input signal's transition. DSP56362 output levels measured with production test machine reference levels respectively. Note: Although minimum value frequency EXTAL MHz, device test conditions rated speed.
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Specifications Internal Clocks
INTERNAL CLOCKS
Table Internal Clocks, CLKOUT
Characteristics Internal operation frequency CLKOUT with enabled Internal operation frequency CLKOUT with disabled Symbol Expression1, MF)/ (PDF Ef/2
Internal clock CLKOUT high period With disabled With enabled With enabled Internal clock CLKOUT period With disabled With enabled With enabled Internal clock CLKOUT cycle time with enabled Internal clock CLKOUT cycle time with disabled Instruction cycle time
Notes:
0.49 DF/MF 0.47 DF/MF
0.51 DF/MF 0.53 DF/MF
0.49 DF/MF 0.47 DF/MF ICYC
DF/MF
0.51 DF/MF 0.53 DF/MF
Division Factor External frequency External clock cycle Multiplication Factor Predivision Factor internal clock cycle Clock Generation section DSP56300 Family Manual detailed discussion PLL.
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Specifications EXTERNAL CLOCK OPERATION
EXTERNAL CLOCK OPERATION
DSP56362 system clock externally supplied square wave voltage source connected EXTAL(Figure 2-1)
VIHC EXTAL VILC CLKOUT With Disabled CLKOUT With Enabled
AA0459
Midpoint
Note:
midpoint (VIHC VILC).
Figure External Clock Timing Table Clock Operation Values
Characteristics Frequency EXTAL (EXTAL Frequency) rise fall time this external clock should maximum. EXTAL input high1, With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6) EXTAL input low1, With disabled (46.7%-53.3% duty cycle6) 4.67 4.67 4.67 0.00 Symbol
100.0
120.0
4.25 157.0 0.00 157.0
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Specifications EXTERNAL CLOCK OPERATION Table Clock Operation (Continued) Values
Characteristics With enabled (42.5%-57.5% duty cycle6) EXTAL cycle time2 With disabled With enabled CLKOUT change from EXTAL fall with disabled CLKOUT rising edge from EXTAL rising edge with enabled MHz)3,5 CLKOUT falling edge from EXTAL rising edge with enabled MHz)3,5 CLKOUT falling edge from EXTAL falling edge with enabled MHz)3,5 Instruction cycle time ICYC Table (46.7%-53.3% duty cycle) With disabled With enabled
Notes:
Symbol
4.25 157.0 4.25 1570.00
10.00
8.33
10.00 273.1 8.33 273.1 11.0
ICYC
0.00 0.00
8.53 8.53
Measured input transition maximum value enabled given minimum maximum Periodically sampled 100% tested maximum value enabled given minimum maximum skew guaranteed other value. indicated duty cycle specified maximum frequency which part rated. minimum clock high time required correction operation, however, remains same lower operating frequencies; therefore, when lower clock frequency used, signal symmetry vary from specified duty cycle long minimum high time time requirements met.
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Specifications Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table Characteristics
Characteristics frequency when enabled 2/PDF) external capacitor (PCAP VCCP) (CPCAP1) Unit
Note:
580)
780) 1470
CPCAP value capacitor (connected between PCAP VCCP). recommended value CPCAP computed from following equations: (680 120, 1100
RESET, STOP, MODE SELECT, INTERRUPT TIMING
Table Reset, Stop, Mode Select, Interrupt Timing Values6
Characteristics Delay from RESET assertion pins reset value3 Expression 26.0 26.0 Unit
Required RESET duration4
Power external clock generator, disabled Power external clock generator, enabled Power internal oscillator During STOP, XTAL disabled (PCTL During STOP, XTAL enabled (PCTL During normal operation
1000 75000 75000
500.0 10.0 25.0 25.0
416.7 20.8 20.8
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Specifications Reset, Stop, Mode Select, Interrupt Timing Table Reset, Stop, Mode Select, Interrupt Timing Values6
Characteristics Expression Unit
Delay from asynchronous RESET deassertion first external address output (internal reset deassertion)5 Minimum Maximum Synchronous reset setup time from RESET deassertion CLKOUT Transition Minimum Maximum Synchronous reset deasserted, delay time from CLKOUT Transition first external address output Minimum Maximum Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory access address valid Caused first interrupt instruction fetch Caused first interrupt instruction execution Delay from IRQA, IRQB, IRQC, IRQD, assertion general-purpose transfer output valid caused first interrupt instruction execution 4.25 7.25 44.5 74.5 37.4 62.4 3.25 20.25 33.5 30.0 207.5 30.0 3.25 20.25 7.50 34.5 211.5 29.1 176.2
10.0
105.0
88.3
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Specifications Reset, Stop, Mode Select, Interrupt Timing Table Reset, Stop, Mode Select, Interrupt Timing Values6
Characteristics Expression Unit
Delay from address output valid caused first interrupt instruction execute interrupt (3.75 10.94 request deassertion level sensitive fast interrupts1 Delay from assertion interrupt request deassertion level sensitive fast interrupts1 Delay from assertion interrupt request deassertion level sensitive fast interrupts1 DRAM SRAM SRAM WS=2,3 SRAM 3.5) 10.94 3.5) 10.94 1.75 2.75 (3.25 10.94
(Note
(Note
(Note
(Note
(Note (Note (Note (Note
(Note (Note (Note (Note
Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, assertion CLKOUT Transition Synchronous interrupt delay time from CLKOUT Transition first external address output valid caused first instruction fetch after coming Wait Processing state Minimum Maximum Duration IRQA assertion recover from Stop state
9.25 24.75
93.5
252.5
78.1
211.2
2-10
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Specifications Reset, Stop, Mode Select, Interrupt Timing Table Reset, Stop, Mode Select, Interrupt Timing Values6
Characteristics Delay from IRQA assertion fetch first instruction (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (Implies Stop Delay) (128 PLC/2) 13.6 Expression Unit
(23.75 0.5)
232.5 12.3
(8.25 0.5)
77.5
87.5
64.6
72.9
Duration level sensitive IRQA assertion ensure interrupt service (when exiting Stop)2,
active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (implies Stop delay)
(128K PLC/2) (20.5 0.5)
13.6
12.3
55.0
45.8
Interrupt Requests Rate HI08, ESAI, SHI, Timer IRQ, (edge trigger) IRQ, (level trigger) 12TC 12TC 120.0 80.0 80.0 120.0 100.0 66.7 66.7 100.0
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Specifications Reset, Stop, Mode Select, Interrupt Timing Table Reset, Stop, Mode Select, Interrupt Timing Values6
Characteristics Expression Unit
Requests Rate Data read from HI08, ESAI,
60.0 70.0 20.0 30.0
50.0 58.0 16.7 25.0
Data write HI08, ESAI, Timer IRQ, (edge trigger)
2-12
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Specifications Reset, Stop, Mode Select, Interrupt Timing Table Reset, Stop, Mode Select, Interrupt Timing Values6
Characteristics Expression Unit
Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory (DMA source) access address valid
Notes:
4.25
44.0
37.4
When using fast interrupts IRQA, IRQB, IRQC, IRQD defined level-sensitive, timings through apply prevent multiple interrupt service. avoid these timing restrictions, deasserted Edge-triggered mode recommended when using fast interrupts. Long interrupts recommended when using Level-sensitive mode. This timing depends several settings: disable, using internal oscillator (PLL Control Register (PCTL) oscillator disabled during Stop (PCTL stabilization delay required assure oscillator stable before executing programs. that case, resetting Stop delay (OMR will provide proper delay. While possible recommended these specifications guarantee timings that case. disable, using internal oscillator (PCTL oscillator enabled during Stop (PCTL 17=1), stabilization delay required recovery time will minimal (OMR setting ignored). disable, using external clock (PCTL stabilization delay required recovery time will defined PCTL settings. enable, PCTL shutdown during Stop. Recovering from Stop requires locked. lock procedure duration, Lock Cycles (PLC), range 1000 cycles. This procedure occurs parallel with stop delay counter, stop recovery will when last these events occurs. stop delay counter completes count lock procedure completion. value disable maximum value 4096 (maximum divided desired internal frequency (i.e., 4096/100 40.96µs). During stabilization period, will constant, their width vary, timing vary well. Periodically sampled 100% tested external clock generator, RESET duration measured during time which RESET asserted, valid, EXTAL input active valid. internal oscillator, RESET duration measured during time which RESET asserted valid. specified timing reflects crystal oscillator stabilization time after power-up. This number affected both specifications crystal other components connected oscillator reflects worst case conditions. When valid, other "required RESET duration" conditions specified above) have been met, device circuitry will uninitialized state that result significant power consumption heat-up. Designs should minimize this state shortest possible duration. does lose lock 0.16 +100°C, number wait states (measured clock cycles, number expression compute maximum value. These values depend number wait states (WS) selected
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Specifications Reset, Stop, Mode Select, Interrupt Timing
RESET
Pins Reset Value
A0-A17
First Fetch
Figure Reset Timing
AA0460
CLKOUT RESET
A0-A17
AA0461
Figure Synchronous Reset Timing
2-14
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Specifications Reset, Stop, Mode Select, Interrupt Timing
First Interrupt Instruction Execution/Fetch
A0-A17
IRQA, IRQB, IRQC, IRQD,
First Interrupt Instruction Execution
General Purpose
IRQA, IRQB, IRQC, IRQD,
General Purpose
Figure External Fast Interrupt Timing
AA0462
IRQA, IRQB, IRQC, IRQD, IRQA, IRQB, IRQC, IRQD,
AA0463
Figure External Interrupt Timing (Negative Edge-Triggered)
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Specifications Reset, Stop, Mode Select, Interrupt Timing
CLKOUT
IRQA, IRQB, IRQC, IRQD,
A0-A17
AA0464
Figure Synchronous Interrupt from Wait State Timing
RESET MODA, MODB, MODC, MODD, PINIT
IRQA, IRQB, IRQC, IRQD,
AA0465
Figure Operating Mode Select Timing
IRQA
A0-A17 First Instruction Fetch
Figure Recovery from Stop State Using IRQA
AA0466
2-16
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Specifications Reset, Stop, Mode Select, Interrupt Timing
IRQA
A0-A17
First IRQA Interrupt Instruction Fetch
AA0467
Figure Recovery from Stop State Using IRQA Interrupt Service
A0-A17
Source Address
IRQA, IRQB, IRQC, IRQD,
First Interrupt Instruction Execution
AA1104
Figure 2-10 External Memory Access (DMA Source) Timing
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Specifications External Memory Expansion Port (Port
EXTERNAL MEMORY EXPANSION PORT (PORT
SRAM Timing
Table SRAM Read Write Accesses MHz3
Characteristics Symbol Expression1 tRC, MHz: 0.25 1.25 MHz: assertion pulse width frequencies: 0.5) MHz: 0.25 1.25 deassertion address valid 2.25 frequencies: 1.25 2.25 Address valid input data valid MHz: tAA, 0.75)
16.0 56.0 106.0 10.5 11.0 16.0 31.0 10.5 20.5
12.0 46.0 87.0 12.7 25.2 16.7
Unit
Address valid assertion pulse width
Address valid assertion
18.5
10.5
14.7
2-18
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Specifications External Memory Expansion Port (Port Table SRAM Read Write Accesses MHz3 (Continued)
Characteristics Symbol Expression1 MHz: 0.25)
Unit
assertion input data valid deassertion data valid (data hold time) Address valid deassertion Data valid deassertion (data setup time)
tOHZ 0.75)
13.5
10.6
MHz: (tDW) 0.25) MHz: 0.25 1.25 2.25 0.75
10.5 20.5
16.7
Data hold time from deassertion
assertion data active
0.25 -0.25 0.25 1.25 2.25 1.25 2.25 3.25
deassertion data high impedance
10.6 18.9
Previous deassertion data active (write)
14.7 23.1
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Specifications External Memory Expansion Port (Port Table SRAM Read Write Accesses MHz3 (Continued)
Characteristics Symbol Expression1 0.75 1.75 2.75
13.5 23.5 21.0 31.0 10.5 20.5
10.6 18.9 16.8 25.2 16.7
Unit
deassertion time
deassertion time Address valid assertion assertion pulse width 0.25) -4.0 0.25 1.25 2.25 setup before deassertion4 hold after deassertion
Notes:
deassertion address valid
0.25
number wait states specified BCR. Timings 100, guaranteed design, tested. timings measured from case negation: timing relative deassertion edge were remain active Timing 110, 111, 112, specified MHz.
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Specifications External Memory Expansion Port (Port
A0-A17 AA0-AA3
D0-D23 Data
AA0468
Figure 2-11 SRAM Read Access
A0-A17 AA0-AA3 D0-D23 Data
AA0469
Figure 2-12 SRAM Write Access
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Specifications External Memory Expansion Port (Port
DRAM Timing
selection guides provided Figure 2-13 Figure 2-16 should used primary selection only. Final selection should based timing provided following tables. example, selection guide suggests that wait states must used operation when using Page Mode DRAM. However, using information appropriate table, designer choose evaluate whether fewer wait states might used determining which timing prevents operation MHz, running chip slightly lower frequency (e.g., MHz), using faster DRAM becomes available), control factors such capacitive resistive load improve overall system performance. Note: This figure should used primary selection. exact detailed timings following tables.
DRAM Type (tRAC
Chip Frequency (MHz)
Wait States Wait States
Wait States Wait States
AA0472
Figure 2-13 DRAM Page Mode Wait States Selection Guide
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Specifications External Memory Expansion Port (Port Table DRAM Page Mode Timings, Wait State (Low-Power Applications)1,
Characteristics Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses. Symbol Expression MHz6 1.25 tCAC tOFF tRSH tRHCP tCAS 0.75 0.75 62.5 33.5 96.0 33.5 42.5 67.5 41.7 21.0 62.7 21.0 25.8 42.5 100.0 MHz6 66.7 Unit
assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion deassertion4 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion
tCRP
1.75
81.5
52.3 102.2 135.5 202.1 12.7 12.7 21.0 62.7 21.2 12.5
3.25 156.5 4.25 206.5 6.25 306.5
tASC tCAH tRAL tRCS tRCH tWCH
0.75 0.75 0.25
21.0 21.0 33.5 96.0 33.7 20.8
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Specifications External Memory Expansion Port (Port Table DRAM Page Mode Timings, Wait State (Low-Power Applications)1, (Continued)
Characteristics Symbol tRWL tCWL tWCS tROH 0.75 0.25 Expression 1.75 1.75 0.25 0.75 MHz6 assertion pulse width Last assertion deassertion assertion deassertion 70.5 83.2 83.2 33.5 45.7 71.0 37.2 42.5 12.5 MHz6 45.5 54.0 54.0 21.0 29.0 46.0 24.7 25.8 Unit
Data valid assertion (Write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid assertion data active deassertion data high impedance
Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows Page Mode DRAM with Wait state. Figure 2-13.
Table 2-10 DRAM Page Mode Timings, Wait States1,
Characteristics Symbol Expression 37.5 34.4 2.75 Unit
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses.
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Specifications External Memory Expansion Port (Port Table 2-10 DRAM Page Mode Timings, Wait States1, (Continued)
Characteristics Symbol tCAC tOFF tRSH tRHCP tCAS 1.75 3.25 Expression 17.9 36.6 14.8 12.3 24.8 Unit
assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion deassertion5 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid assertion data active
tCRP
19.0 37.8 50.3 75.3 11.6 17.9 33.5 11.8 14.6 26.8 30.1 27.0 17.9 27.3
15.4
tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL tWCS tROH
1.25 1.75 1.25 2.75 0.25 1.75 1.75 0.75
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Specifications External Memory Expansion Port (Port Table 2-10 DRAM Page Mode Timings, Wait States1, (Continued)
Characteristics Symbol Expression 0.25 Unit
deassertion data high impedance
Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56362. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM Control Register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. There fast enough DRAMs wait states Page mode 100MHz. Figure 2-13.
Table 2-11 DRAM Page Mode Timings, Three Wait States1,
Characteristics Symbol Expression 40.0 35.0 21.0 41.0 16.0 tCAC tOFF tRSH tRHCP tCAS MHz: MHz: 13.0 23.0 Unit
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses. assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0]
tCRP
2.25 3.75 4.75 6.75
41.5 61.5
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Specifications External Memory Expansion Port (Port Table 2-11 DRAM Page Mode Timings, Three Wait States1, (Continued)
Characteristics Symbol tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL tWCS tROH 0.75 0.25 Expression MHz: 1.25 MHz: 0.75 2.25 3.75 3.25 1.25 MHz: 11.0 21.0 36.0 18.3 30.5 33.2 28.2 21.0 31.0 18.0 Unit
deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion
deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance
Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56362. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of page-access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ.
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Specifications External Memory Expansion Port (Port Table 2-12 DRAM Page Mode Timings, Four Wait States 120MHz1,
Characteristics Symbol Expression
50.0 45.0 20.5 30.5 41.7
Unit
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses. assertion data valid (read)
tCAC tOFF tRSH tRHCP tCAS MHz: 2.75 MHz: 3.75
37.5 25.2 46.0 16.8 15.9 24.2
Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width
31.0 56.0 21.0
tCRP
2.75 4.25
37.7 54.4 12.7 25.2 37.7 22.9 33.0
5.25 46.5 7.25 66.5 tASC tCAH tRAL tRCS tRCH tWCH MHz: 1.25 MHz: 1.25 16.0 31.0 46.0
3.25 28.3 40.5
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Specifications External Memory Expansion Port (Port Table 2-12 DRAM Page Mode Timings, Four Wait States 120MHz1, (Continued)
Characteristics Symbol tRWL tCWL tWCS tROH 0.75 0.25 Expression
25.5 35.3 26.9 25.2 33.5 20.1
Unit
Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance
Notes:
4.75 43.2 3.75 33.2 1.25 MHz: 3.25 31.0 41.0
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56362. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ.
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2-29
Specifications External Memory Expansion Port (Port
Column Address
Column Address
Last Column Address
A0-A17
D0-D23
Data Data Data
Figure 2-14 DRAM Page Mode Write Accesses
AA0473
2-30
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Specifications External Memory Expansion Port (Port
A0-A17
Column Address
Column Address
Last Column Address
D0-D23
Data Data Data
AA0474
Figure 2-15 DRAM Page Mode Read Accesses
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Specifications External Memory Expansion Port (Port
DRAM Type (tRAC
Note:
This figure should primary selection. exact detailed timings following tables.
Wait States Wait States
Chip Frequency (MHz)
Wait States Wait States
AA0475
Figure 2-16 DRAM Out-of-Page Wait States Selection Guide Table 2-13 DRAM Out-of-Page Refresh Timings, Four Wait States1,
Characteristics3 Symbol tRAC tCAC tOFF 1.75 Expression 2.75 1.25 MHz4 250.0 83.5 130.0 55.0 67.5 MHz4 166.7 54.3 84.2 34.2 42.5 Unit
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion
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Specifications External Memory Expansion Port (Port Table 2-13 DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
Characteristics3 Symbol tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR Expression 3.25 1.75 2.75 1.25 1.25 2.25 1.75 1.75 1.25 0.25 1.75 3.25 0.75 0.25 MHz4 158.5 83.5 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 83.5 158.5 96.0 71.2 33.8 70.8 145.8 77.0 64.5 MHz4 104.3 54.3 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 54.3 104.3 62.7 46.2 21.3 45.8 95.8 52.0 43.7 Unit
assertion pulse width assertion deassertion assertion deassertion
assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion
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Specifications External Memory Expansion Port (Port Table 2-13 DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
Characteristics3 Symbol tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 0.25 Expression 4.75 4.25 2.25 1.75 3.25 1.25 MHz4 220.5 233.2 208.2 108.5 83.5 158.5 145.7 21.0 58.5 221.0 37.2 192.5 12.5 MHz4 145.5 154.0 137.4 71.0 54.3 104.3 95.7 12.7 37.7 146.0 24.7 125.8 Unit
assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid3 assertion data active deassertion data high impedance
Notes:
number wait states page access specified DCR. refresh period specified DCR. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows DRAM out-of-page access with four Wait states. Figure 2-16.
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Specifications External Memory Expansion Port (Port Table 2-14 DRAM Out-of-Page Refresh Timings, Eight Wait States1,
Characteristics4 Symbol tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL 3.25 5.75 3.25 4.75 2.25 1.75 4.25 2.75 3.25 1.75 0.75 3.25 5.75 1.25 0.25 8.75 7.75 4.75 Expression3 4.75 2.25 36.6 67.9 36.6 55.4 24.1
112. 52.9 21.6 31.0
Unit
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write)
29.3 33.3 19.9 23.9 49.1 30.4 36.6 17.9 36.6 67.9 46.0 21.2 11.9 33.3 64.6 101. 105. 92.6 55.4
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Specifications External Memory Expansion Port (Port Table 2-14 DRAM Out-of-Page Refresh Timings, Eight Wait States1, (Continued)
Characteristics4 Symbol tDHR tWCS tCSR tRPC tROH Expression3 3.25 5.75 1.75 0.75 0.25
36.6 67.9 64.5 14.8 17.9 102. 87.3
Unit
assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh)
assertion deassertion assertion data valid deassertion data valid4 assertion data active deassertion data high impedance
Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56362. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table 2-15 DRAM Out-of-Page Refresh Timings, Eleven Wait States1,
Characteristics4 Symbol tRAC tCAC tOFF tRAS tRSH tCSH 4.25 7.75 5.25 6.25 Expression3 6.25 3.75
120.0 38.5 73.5 48.5 58.5
55.5 30.5 38.0
Unit
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion
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Specifications External Memory Expansion Port (Port Table 2-15 DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (Continued)
Characteristics4 Symbol tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH Expression3 3.75 1.75 5.75 4.25 4.25 1.75 0.75 5.25 7.75 1.75 0.25 0.25 11.5
33.5 21.0 13.5 53.5 38.5 38.5 13.5 48.5 73.5 56.0 26.0 13.5 45.8 70.8 110.5
29.0 21.5 93.0
Unit
assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width
address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid
11.75 113.2 10.25 103.2 5.75 5.25 7.75 2.75 11.5 53.5 48.5 73.5 60.7 11.0 23.5 111.0
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Specifications External Memory Expansion Port (Port Table 2-15 DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (Continued)
Characteristics4 Symbol 0.75 0.25 Expression3
Unit
deassertion data valid4 assertion data active deassertion data high impedance
Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56362. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table 2-16 DRAM Out-of-Page Refresh Timings, Fifteen Wait States 120MHz1,
Characteristics3 Symbol tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR Expression 8.25 4.75 6.25 9.75 6.25 8.25 4.75 2.75 7.75 6.25 6.25
160.0 58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5 58.5 58.5
76.8 41.8 49.3 37.0 29.5
133.3
63.0 33.9 40.1
Unit
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion
48.1 77.2 48.1 64.7 35.6 27.2 20.9 60.6 48.1 48.1
31.2 24.9
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Specifications External Memory Expansion Port (Port Table 2-16 DRAM Out-of-Page Refresh Timings, Fifteen Wait States 120MHz1, (Continued)
Characteristics3 Symbol tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 0.25 Expression 2.75 0.75 6.25 9.75 1.75 0.25 15.5
23.5 58.5 93.5 66.0 46.2 13.8 55.8 90.8 150.5
134.3
18.9 48.1 77.2 54.3 37.9 10.9 45.8 75.0 124.7 126.9 114.4 68.9 48.1 77.2 74.9 35.6 125.2
111.0
Unit
assertion address valid Column address valid assertion assertion column address valid
assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid3 assertion data active deassertion data high impedance
15.75 153.2 14.25 138.2 8.75 6.25 9.75 4.75 15.5 83.5 58.5 93.5 90.7 11.0 43.5 151.0
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Specifications External Memory Expansion Port (Port Table 2-16 DRAM Out-of-Page Refresh Timings, Fifteen Wait States 120MHz1, (Continued)
Notes:
Characteristics3
Symbol
Expression
Unit
number wait states out-of-page access specified DCR. refresh period specified DCR. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
A0-A17
Address Column Address
Data
D0-D23
AA0476
Figure 2-17 DRAM Out-of-Page Read Access
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Specifications External Memory Expansion Port (Port
A0-A17
Address
Column Address
D0-D23
Data
AA0477
Figure 2-18 DRAM Out-of-Page Write Access
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Specifications External Memory Expansion Port (Port
AA0478
Figure 2-19 DRAM Refresh Access
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Specifications External Memory Expansion Port (Port
Synchronous Timings (SRAM)
Table 2-17 External Synchronous Timings (SRAM Access)4
Characteristics Expression1, 0.25 0.25
11.5
Unit
CLKOUT high address, valid5 CLKOUT high address, invalid5
valid CLKOUT high (setup time) CLKOUT high invalid (hold time) CLKOUT high data active CLKOUT high data valid CLKOUT high data invalid CLKOUT high data high impedance Data valid CLKOUT high (setup) CLKOUT high data invalid (hold) CLKOUT high assertion CLKOUT high deassertion frequencies: CLKOUT high deassertion
Notes:
0.25 0.25 0.25 0.25
0.75
CLKOUT high assertion3
number wait states specified BCR. asynchronous delays specified expressions valid DSP56362. assertion refers next rising edge CLKOUT. External synchronous timings should used only reference clock relative timings. T198 T199 valid Address Trace mode set. status (See T212) determine whether access referenced A0-A23 internal external, when this mode enabled
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Specifications External Memory Expansion Port (Port
CLKOUT A0-A17 AA0-AA3
D0-D23 D0-D23 Data
AA0479
Data
Figure 2-20 Synchronous Timings SRAM (BCR Controlled)
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Specifications External Memory Expansion Port (Port
CLKOUT A0-A17 AA0-AA3
D0-D23 D0-D23 Data
AA0480
Data
Figure 2-21 Synchronous Timings SRAM Controlled)
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Specifications External Memory Expansion Port (Port
Arbitration Timings
Table 2-18 Arbitration Timings1
Characteristics Expression 0.25 0.25 0.25 Unit
CLKOUT high assertion/ deassertion2 asserted/deasserted CLKOUT high (setup)
CLKOUT high deasserted/ asserted (hold) deassertion CLKOUT high (input setup) CLKOUT high assertion (input hold) CLKOUT high assertion (output) CLKOUT high deassertion (output) high high impedance (output) CLKOUT high address controls active CLKOUT high address controls high impedance CLKOUT high active CLKOUT high deassertion CLKOUT high high impedance
Notes:
0.25 0.75
asynchronous delays specified expressions valid DSP56362. T212 valid Address Trace mode when set. deasserted internal accesses asserted external accesses.
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Specifications External Memory Expansion Port (Port
CLKOUT
A0-A17
AA0-AA3
AA0481
Figure 2-22 Acquisition Timings
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Specifications External Memory Expansion Port (Port
CLKOUT
A0-A17 AA0-AA3
AA0482
Figure 2-23 Release Timings Case (BRT Cleared)
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Specifications External Memory Expansion Port (Port
CLKOUT
A0-A17 AA0-AA3
Figure 2-24 Release Timings Case (BRT Set)
AA0483
Table 2-19 Asynchronous Arbitration timing
Characteristics assertion window from input negation. Delay from assertion assertion Expression Unit
Comments: register must enter Asynchronous Arbitration mode recommended Asynchronous Arbitration mode. Asynchronous Arbitration mode active, none timings Table 2-19 required. order guarantee timings 250, 251, recommended assert inputs different 56300 devices same bus) overlap manner shown Figure 2-25.
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Specifications External Memory Expansion Port (Port
Figure 2-25 Asynchronous Arbitration Timing
250+251
Figure 2-26 Asynchronous Arbitration Timing
Background explanation Asynchronous Arbitration: asynchronous arbitration enabled internal synchronization circuits inputs. These synchronization circuits delay from external signal until exposed internal logic. result this delay, 56300 part assume mastership assert some time after negated. This reason timing 250. Once asserted, there synchronization delay from assertion time this assertion exposed other 56300 components which potential masters same bus. input asserted before that time, situation asserted, negated, cause another 56300 component assume mastership same time. Therefore some non-overlap period between input active another input active, required. Timing ensures that such situation avoided.
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Specifications Parallel Host Interface (HDI08) Timing
PARALLEL HOST INTERFACE (HDI08) TIMING
Table 2-20 Host Interface (HDI08) Timing1,
Characteristics3 Expression 19.9 Unit
Read data strobe assertion width HACK read assertion width Read data strobe deassertion width HACK read deassertion width
Read data strobe deassertion width4 after "Last Data Register" reads5,6, between consecutive CVR, ICR, reads7 HACK deassertion width after "Last Data Register" reads5,6
Write data strobe assertion width HACK write assertion width
31.6
13.2
Write data strobe deassertion width8 HACK write deassertion width after ICR, "Last Data Register" writes5 after writes, after TXH:TXM writes (with HBE=0), after TXL:TXM writes (with HBE=1) deassertion data strobe assertion9
31.6 16.5
assertion width Host data input setup time before write data strobe deassertion Host data input setup time before HACK write deassertion Host data input hold time after write data strobe deassertion Host data input hold time after HACK write deassertion Read data strobe assertion output data active from high impedance HACK read assertion output data active from high impedance
Read data strobe assertion output data valid HACK read assertion output data valid
24.2
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Specifications Parallel Host Interface (HDI08) Timing Table 2-20 Host Interface (HDI08) Timing1, (Continued)
Characteristics3 Expression Unit
Read data strobe deassertion output data high impedance HACK read deassertion output data high impedance Output data hold time after read data strobe deassertion Output data hold time after HACK read deassertion
+9.9
19.9
19.1
assertion read data strobe deassertion4 assertion write data strobe deassertion8 assertion output data valid hold time after data strobe deassertion9 Address (AD7-AD0) setup time before deassertion (HMUX=1) Address (AD7-AD0) hold time after deassertion (HMUX=1) A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion9 Read Write A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion9 Delay from read data strobe deassertion host request assertion "Last Data Register" read4,
Delay from write data strobe deassertion host request assertion "Last Data Register" write5, Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD 0)5, Delay from data strobe assertion host request deassertion "Last Data Register" read or5, write (HROD open drain Host Request)
19.1
300.
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Specifications Parallel Host Interface (HDI08) Timing Table 2-20 Host Interface (HDI08) Timing1, (Continued)
Characteristics3 Delay from HACK deassertion HOREQ assertion "Last Data Register" read5 19.1 "Last Data Register" write5 other cases Delay from HACK assertion HOREQ deassertion HROD Delay from HACK assertion HOREQ deassertion "Last Data Register" read write HROD open drain Host Request5,
Notes:
Expression
Unit
39.1
20.2
19.1 34.1
300.
Host Port Usage Considerations DSP56362 User Design Manual. timing diagrams below, controls pins drawn active low. polarity programmable. 0.16 +100°C, read data strobe dual data strobe mode single data strobe mode. "last data register" register address which last location read written data transfers. This RXL/TXL little endian mode (HBE RXH/TXH endian mode (HBE This timing applicable only read from "last data register" followed read from RXL, RXM, registers without first polling RXDF HREQ bits, waiting assertion HOREQ signal. This timing applicable only consecutive reads from these registers executed. write data strobe dual data strobe mode single data strobe mode. data strobe host read (HRD) host write (HWR) dual data strobe mode host data strobe (HDS) single data strobe mode. host request HOREQ single host request mode HRRQ HTRQ double host request mode. this calculation, host request signal pulled resistor open-drain mode.
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Specifications Parallel Host Interface (HDI08) Timing
HACK HD7-HD0
HOREQ
AA1105
Figure 2-27 Host Interrupt Vector Register (IVR) Read Timing Diagram
HA0-HA2
HRD, HD0-HD7 HOREQ, HRRQ, HTRQ
Figure 2-28 Read Timing Diagram, Non-Multiplexed
AA0484
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Specifications Parallel Host Interface (HDI08) Timing
HA0-HA2
HWR,
HD0-HD7 HOREQ, HRRQ, HTRQ
AA0485
Figure 2-29 Write Timing Diagram, Non-Multiplexed
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Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10
HRD, HAD0-HAD7 Address HOREQ, HRRQ, HTRQ
AA0486
Data
Figure 2-30 Read Timing Diagram, Multiplexed
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Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10
HWR,
HAD0-HAD7 Address
Data
HOREQ, HRRQ, HTRQ
AA0487
Figure 2-31 Write Timing Diagram, Multiplexed
HOREQ (Output)
HACK (Input)
TXH/M/L Write
H0-H7 (Input)
Data Valid
Figure 2-32 Host Write Timing Diagram
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Specifications Serial Host Interface Protocol Timing
HOREQ (Output)
Read Data Valid
HACK (Input)
H0-H7 (Output)
Figure 2-33 Host Read Timing Diagram
SERIAL HOST INTERFACE PROTOCOL TIMING
Table 2-21 Serial Host Interface Protocol Timing
Characteristics Mode Filter Mode Bypassed Narrow Wide Bypassed Master Narrow Wide Expression 100MHz Unit
Tolerable spike width clock data Minimum serial clock cycle tSPICC(min)
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Specifications Serial Host Interface Protocol Timing Table 2-21 Serial Host Interface Protocol Timing (Continued)
Characteristics Mode Filter Mode Bypassed Master Serial clock high period Slave Narrow Wide Bypassed Narrow Wide Bypassed Expression 100MHz 2000 Unit
Master Serial clock period Slave Master Slave Slave
Narrow Wide Bypassed Narrow Wide Bypassed Narrow Wide Bypassed
Serial clock rise/fall time assertion first edge CPHA CPHA
Slave
Narrow Wide Bypassed
Last edge asserted
slave
Narrow Wide
Data input valid Master Bypassed edge (data input set-up /Slave Narrow MAX{(20-TC), time) Wide MAX{(40-TC), last sampling edge data input valid assertion data active deassertion data high impedance edge data valid (data delay time) Master /Slave Slave Slave Master /Slave Bypassed Narrow Wide Bypassed Narrow Wide
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Specifications Serial Host Interface Protocol Timing Table 2-21 Serial Host Interface Protocol Timing (Continued)
Characteristics Mode Master /Slave Slave Filter Mode Bypassed Narrow Wide Bypassed Slave Narrow Wide Bypassed Slave Narrow Wide Bypassed HREQ assertion first edge Master Narrow Wide HREQ deassertion last sampling edge (HREQ set-up time) (CPHA First edge HREQ asserted (HREQ hold time)
Note:
Expression TC+5 TC+55 TC+106 TC+33 TC+6 tSPICC
100MHz
Unit
edge data valid (data hold time) assertion data valid (CPHA First sampling edge HREQ output deassertion Last sampling edge HREQ output deasserted (CPHA
deassertion Slave HREQ output deasserted (CPHA deassertion pulse width (CPHA Slave
Master
Master
Periodically sampled, 100% tested
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Specifications Serial Host Interface Protocol Timing
(Input)
(CPOL=0 (Output)
(CPOL (Output)
MISO (Input)
Valid
Valid
MOSI (Output) HREQ (Input)
Figure 2-34 Master Timing (CPHA
AA0271
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Specifications Serial Host Interface Protocol Timing
(Input)
(CPOL (Output) (CPOL (Output)
MISO (Input)
Valid Valid
MOSI (Output) HREQ (Input)
AA0272
Figure 2-35 Slave Timing (CPHA
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Specifications Serial Host Interface Protocol Timing
(Input)
(CPOL (Output) (CPOL (Output)
MISO (Input)
Valid Valid
MOSI (Output) HREQ (Input)
AA0272
Figure 2-36 Master Timing (CPHA
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Specifications Serial Host Interface Protocol Timing
(Input)
(CPOL (Input)
(CPOL (Input)
MISO (Output) MOSI (Input)
Valid
Valid
HREQ (Output)
AA0273
Figure 2-37 Slave Timing (CPHA
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Specifications Serial Host Interface Protocol Timing
(Input)
(CPOL (Input) (CPOL (Input)
MISO (Output)
MOSI (Input) HREQ (Output)
Valid Valid
Figure 2-38 Slave Timing (CPHA
AA0274
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Specifications Serial Host Interface (SHI) Protocol Timing
SERIAL HOST INTERFACE (SHI) PROTOCOL TIMING
Table 2-22 Protocol Timing
Standard I2C* Characteristics Tolerable spike width Filters bypassed Narrow filters enabled FSCL TBUF TSU;STA THD;STA TLOW THIGH TSU;DAT THD;DAT TSU;STO FDSP Filters bypassed Narrow filters enabled Wide filters enabled HREQ deassertion last edge (HREQ set-up time) First sampling edge HREQ output deassertion2 tSU;RQI TNG;RQO 10.6 11.8 13.1 28.5 39.7 61.0 Symbol/ Expression Standard Fast-Mode Unit
Wide filters enabled clock frequency free time Start condition set-up time Start condition hold time period high period rise time fall time Data set-up time Data hold time Stop condition set-up time Capacitive load each line clock frequency
1000
Filters bypassed Narrow filters enabled Wide filters enabled Last edge HREQ output deasserted2 TAS;RQO
Filters bypassed Narrow filters enabled Wide filters enabled
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Specifications Serial Host Interface (SHI) Protocol Timing Table 2-22 Protocol Timing (Continued)
Standard I2C* Characteristics HREQ assertion first edge Symbol/ Expression Standard Fast-Mode Unit
TAS;RQI Filters bypassed TI2CCP 4327 Narrow filters enabled 4282 Wide filters enabled 4238
Note:
(min)
Programming Serial Clock
programmed serial clock cycle, I2CCP specified value HDM[5:0] bits HCKR (SHI clock control register). expression I2CCP
I2CCP (HDM[7:0] HRS)
where
prescaler rate
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