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MPCPCMEC / D Motorola Order Number 8 / 97

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Freescale Semiconductor, Inc.
MPCPCMEC / D (Motorola Order Number) 8 / 97
Freescale Semiconductor, Inc..
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PCM Hardware Specifications
The Processor and Cache Module (PCM) is a 17 x 17 pin grid array (PGA) circuit assembly which combines a PowerPC® microprocessor and SRAM components into a CPU subsystem. The PCM provides a standard mechanical, electrical, and functional interface which can be socketed on a computer system board and allow many combinations of processors and optional components to be easily interchanged. This document describes the general characteristics for a module consisting of a single PowerPC microprocessor and two SRAM devices for L2 cache. The PCM packaging and PGA signal definition also accomodates single processors without SRAM, and multiple processors.
Processor and Cache Module Hardware Specifications
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This document contains the following topics:
Topic Page
Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.5, "Pin Assignments" Section 1.6, "Pinout Listings" Section 1.7, "Package Description" Section 1.8, "System Design Information" Section 1.9, "Ordering Information"
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This section summarizes features of the PCM. Major features of the PCM are as follows:
An FR4 PCM to connect a 360-lead CBGA PowerPC microprocessor to the 288-pin PGA. An interconnection area between the processor and SRAM memory when configured with an L2 cache. (When the MPC750 microprocessor is configured to support an L2 cache, the L2address and data buses are entirely contained on the processor module without any increase in the number of PGA pins or complexity for the system designer.) Additional power supply filtering on the processor module - PLL voltage supply (AVdd) filtering on the PGA PCM close to the processor improves noise immunity. - Core voltage (Vdd) filtering on PCM reduces voltage variations.
PCM signals determine selection of processor voltage and identification of module type - Direct encoding and control of power supply modules - Four voltage ID pins select operating core voltage from 1.3V to 3.5V. - Encodings match industry-standard power-controllers. - Self-identification of the module - 3-pin encoding for simple modules. - Serial EEPROM encoding for complex modules.
The same signals and system interface operation as the attached PowerPC processor would provide in a 255-pin (16 x 16) CBGA package.
1.2 Features
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The PCM is a circuit assembly which combines a PowerPC microprocessor and two SRAM components into a CPU subsystem. The PCM consists of an epoxy-glass (FR4) substrate which adapts a processor in a ceramic ball grid array (CBGA) package with 50 mil spacing to a 288-pin PGA with 100 mil spacing that can be easily socketed and hence, easily upgraded. The FR4 substrate can be extended beyond the area of the 17 x 17 pin grid array to provide an interconnect area for SRAM components configured as closely coupled L2 cache. The resulting PCM provides numerous flexible configurations of processor and cache for various price / performance system designs.
1.1 Overview
To locate any published errata or updates for this document, refer to the website at http://www.mot.com / SPS / PowerPC / .
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1.3 General Parameters
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1.4 Electrical and Thermal Characteristics
The AC and DC electrical specifications for the PCM are identical to the electrical specifications for the attached microprocessor unless otherwise specified in the part number specifications for a particular module. The thermal characteristics for the PCM are generally the composite of the thermal characteristics for the attached microprocessor and SRAMs. The variety of processor and SRAM speeds possible dictate that thermal characteristics are unique to a particular module and therefore are described in its associated part number specifications.
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1.5 Pin Assignments
Figure 1 (in part A) shows the pinout of the PCM as viewed from the top surface. Part B shows the side profile of the module to indicate the direction of the top surface view.
Part A
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Part B
CBGA Substrate Microprocessor Die CQFP Packaged SRAM View
FR4 PCM
Figure 1. 17 x 17 PGA Processor + Cache Module Pinout
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Not to Scale
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1.6 Pinout Listings
Table 1 provides the pinout listing for the 17 x 17 PGA PCM. This pinout is the superset of all 17 x 17 PCMs and should be followed for maximum interchangeability between modules however, particular implementations may not connect all signals between the PGA pins and the PowerPC microprocessor. See the individual part number specifications for specific pinouts by part number.
Table 1. Pinout Listing for the 17 x 17 PGA Module
Signal Name A0-31 Pin Number F13, E1, D17, F3, E16, F1, E17, G5, F15, G4, G13, G3, F17, G2, G14, G1, G15, H1, G16, H3, G17, J1, H13, H5, H15, J2, H17, J3, J13, L1, K13, M1 K3 L3 E6, C4, C5, A4 C8 A8 K5 A11 J5 E13 E8 Active I / O I / O
Low Low High Low Low Low High Low Low Low Low Low - Low Low High Low Low Low Low Low High
Input I / O I / O Output Input I / O Input Input Input Output Output Output Output Input Output Output I / O Input Input Input Input I / O
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DL0-31
A17 C9 E7, B5 L17 J15 R15 P13, N12, T15, U15, R13, U14, N10, P11, T11, U11, R10, U10, U9, T9, N9, P9, R9, U8, R8, U7, N8, P7, T7, U6, R7, R6, N7, U5, T5, U4, R5, U3 L16, K15, M17, L14, N17, M15, N16, L13, M13, N15, P17, R17, N14, P15, R16, U16, R14, N11, T13, R12, U13, R11, U12, N3, P3, N4, R2, T1, T3, R4, P5, N6 L4, N1, M3, N2, P1, L5, R1, M5
DP0-7
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Table 1. Pinout Listing for the 17 x 17 PGA Module (Continued)
Signal Name DPE DRTRY DRVMOD0-1 GBL GND B7 J17 E3, D3 F5 B4, B8, B10, B14, D2, D6, D12, D16, F4, F6, F8, F10, F12, F14, G7, G9, G11, H2, H6, H8, H10, H12, H16, J7, J9, J11, K2, K6, K8, K10, K12, K16, L7, L9, L11, M4, M6, M8, M10, M12, M14, P2, P6, P12, P16, T4, T8, T10, T14 D9 B9 E14 U17 D11 B11 A7 E10 D15 D7 Pin Number Active Low Low - Low Low I / O Output Input Input I / O Input
HALTED
High Low Low Low Low - High - Low High - High Output Input Input Input Input Input Input Input Input Input Input High High Low Low Low - - Low Low Low - - Low I / O Input Input Output Output Input I / O I / O Input Input Input Input Input
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N13 B2, B6, B12, B16, D4, D8, D10, D14, F2, F9, F16, H4, H14, J6, J12, K4, K14, M2, M9, M16, P4, P8, P10, P14, T2, T6, T12, T16 U1, U2, R3 A9, A10, A13, C11 N5 D5 C1 B17 D13 C10 T17 J16
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Table 1. Pinout Listing for the 17 x 17 PGA Module (Continued)
Signal Name TBEN TBST TC0-24 TCK TDI TDO TEA TLBISYNC E4 E12 C6, A5, C7 C12 B13 A14 J14 C15 C13 A12 E11, A15, B15 L15 Pin Number Active High Low High - High I / O Input I / O Output Input Input Output Input Input Input Input I / O I / O I / O Input Input Output Output
High Low Low High Low High Low High High High Low Low
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TMS TRST TSIZ0-2 TS TT0-4 VDD3 VID0-4 WT XATS1 Notes:
A16, C14, C16, C17, E15
F7, F11, G6, G8, G10, G12, H7, H9, H11, J8, J10, K7, K9, K11, L6, L8, L10, L12, M7, M11 B1, C2, A2, B3, C3
2. These are test signals for factory use only and must be pulled up to Vdd for normal machine operation. 3. OVdd inputs supply power to the I / O drivers and Vdd inputs supply power to the processor core. 4. TC2 defined for PowerPC 604TM-class processors only. 5. These signals are undefined and must be left disconnected.
Many of the PCM signals have the same definition and timing as that of the attached processor. The actual signals present vary depending upon the type of the PowerPC microprocessor used refer to the corresponding processor hardware specifications for details. The PCM implements several signals that are not part of the PowerPC 60x bus specification, nor of any particular PowerPC processor. These pins are unique to the PCM and are used to set operational parameters or indicate the features the PCM provides. Table 2 describes the functions of the signals provided for identification or configuration of the PCM.
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1. Not recommended for new designs.
D1 K17
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Table 2. PCM Unique / Redefined Pins
Pin Name VID4-0 Definitions The VID pins encode the voltage encoding as described in Section 1.8.6, "Voltage Encoding." Note the little-endian bit ordering, used for compatibility with industry standard parts. Notes These pins must be pulled up by the power controller for proper operation. The pullups must be wired to a voltage level which is stable while the power controller ramps up after power up. Many power controllers include internal pullups to handle this.
PID0-2
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SYSCLK2
Clock for second processor. Same timing as SYSCLK for PowerPC CPUs.
I2C serial clock input
Data Bus grant for second processor. Same timing as DBG for PowerPC CPUs.
Bus grant for second processor. Same timing as BG for PowerPC CPUs.
Bus request for second processor. Same timing as BR for PowerPC CPUs.
Interrupt for second processor. Same timing as INT for PowerPC CPUs.
SDATA
I2C command input / data output
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Unused signal-Reserved for future function signal should remain disconnected
Unused signal-Reserved for future function signal should remain disconnected Unused signal-Reserved for future function signal should remain disconnected Unused signal-Reserved for future function signal should remain disconnected Connected when EEPROM presence detect mode is implemented. Connected when EEPROM presence detect mode is implemented.
PLL0-3
Specified PLL setting to use.
The PID pins carry the presence detect codes as described in Section 1.8.7, "Presence Detect."
These pins must be pulled up by the system with 1K to 10K pullup resistors.
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1.7 Package Description
The following sections provide the package parameters and the mechanical dimensions for the PCM.
1.7.1 Package Parameters
The package parameters are as provided in the following list. The package consists of a 288-lead pin grid array (PGA) on the bottom of a 1.75 x 2.5 inch glass-epoxy (FR4) substrate with a PowerPC microprocessor in a ceramic ball grid array (CBGA) package and two fast static RAMs (FSRAMs) in ceramic quad flat pack (CQFP) or plastic ball grid array (PBGA) packages attached on the top. The package parameters for the PGA PCM are: Package outline Interconnects 1.75 in. by 2.50 in. 288 0.1 in 0.018 in .180 in Au .215 in
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Pin Diameter Pin Length Lead Plating Module Height without pins
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Pitch
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Figure 2 provides the mechanical dimensions for the PCM.
D (D4)
B (D5) NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN INCHES. 3. TOP SIDE A1 CORNER INDEX IS A SILK SCREENED FEATUREWITHVARIOUSSHAPES.BOTTOMSIDEA1 CORNERISDESIGNATEDWITHAPINMISSINGFROM THE ARRAY 4. DIMENSIONS D1 AND E1 ARE LESSTHAN OR EQUAL TO D AND E. 5. MINIMUM HANDLING CLEARANCE BETWEEN PACKAGE EDGE AND PASSIVE COMPONENTS IS 0.020.
E (E3)
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A1 CORNER
(D6) (D3) TOP VIEW
Inches DIM A A1 A2 A3 A4 A5 A6 b D D1 D2 D3 D4 D5 D6 D7 e E E1 E2 E3 E4 E5 E6 E7 MIN MAX 0.390 0.420 0.170 0.190 - 0.065 0.090 0.115 0.055 0.063 - 0.098 0.0980 0.132 0.016 0.020 2.480 2.550 See Note 4 1.600 REF 0.984 REF 0.870 REF 0.787 BSC 0.532 REF 0.560 REF 0.100 BSC 1.740 1.780 See Note 4 1.600 REF 0.984 REF 0.630 BSC 0.551 BSC 0.532 REF 0.420 REF
(D2) BOTTOM VIEW
e b 0.030 A B C 0.010 A A5 A6 A SIDE VIEW
Figure 2. Mechanical Dimensions and Bottom Surface Nomenclature of the PCM
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1.8 System Design Information
1.8.1 PLL Configuration
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1.8.2 PLL Power Supply Filtering
The AVdd power signal provides power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal of the microprocessor should be as electrically quiet as possible. For maximum effectiveness the filter circuit of Figure 3 which is normally recommended for inclusion in the system design has been included on the PCM itself.
AVdd (or L2AVdd) 10 µF 0.1 µF GND
Figure 3. PLL Power Supply Filter Circuit
The PCM resistors are used to program the connection between the external signals and the microprocessor PLL supply as shown in Figure 4. If required, the system can provide additional power supply filtering for the AVdd signal, shown in Figure 3, to the PCM AVdd signal. The PCM provides AVdd power supply filtering as shown in Figure 4.
10 External Vdd 10 µF External AVdd NC GND 0.1 µF 0.1 µF Internal AVdd Internal L2AVDD
Figure 4. PCM PLL Power Supply Filter Circuit
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The microprocessor and cache on the PCM can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the system, and the module itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd and OVdd pin of the module. It is also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance.
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Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the PCM.
Table 3. Voltage Encoding
VID4-0 Output 01111 01110 01101 01100 01011 01010 01001 01000 Voltage (V) 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V 1.55 V 1.60 V 1.65 V VID4-0 Output 10000 10001 10010 10011 10100 10101 10110 10111 Voltage (V) 3.50 V 3.40 V 3.30 V 3.20 V 3.10 V 3.00 V 2.90 V 2.80 V
The core operating voltage (Vdd and AVdd) for PowerPC processors has varied with semiconductor process technology. Within a narrow range determined by the process technology, Motorola has specified nonstandard core voltages for some processors in device-specific part number specifications.
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1.8.6 Voltage Encoding
The PCM is specifically designed for the flexibility of a socket. The PGA footprint is compatible with the widely available Socket #3 footprint popular in the PC industry. Several vendors provide this socket, including Amp Incorporated (part number: 916668-1).
1.8.5 Socketing
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
1.8.4 Connection Recommendations
The module will provide some bulk decoupling and high frequency decoupling capacitors on the module itself to improve the overall system noise immunity.
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Table 3. Voltage Encoding (Continued)
VID4-0 Output 00111 00110 00101 00100 00011 00010 00001 00000 Voltage (V) 1.70 V 1.75 V 1.80 V 1.85 V 1.90 V 1.95 V 2.00 V 2.05 V VID4-0 Output 11000 11001 11010 11011 11100 11101 11110 11111 Voltage (V) 2.70 V 2.60 V 2.50 V 2.40 V 2.30 V
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The PCM provides a means of self-identification (called presence detection after the method(s) used to identify memory and cache modules). The module implements a three-wire solution which combines the inexpensive parallel encoding of Single In-line Memory Modules (SIMMs) with the more flexible serial solution found on Dual In-line Memory Modules (DIMMs). Figure 5 shows the architecture of the presence detection:
VCC VCC VCC
1.8.7 Presence Detect
The PCM encodes the voltage setting by selectively installing 0-ohm resistors on the VID bus. The regulator must have internal pullups to properly encode the settings (this is true of all known 5-bit encoded switching controllers).
Note: The bit numbering shown here is little-endian due to pre-existing standards. This differs from most other PowerPC bus numbering conventions.
2.20 V 2.10 V
No CPU
PID0 PID1 PID2
SCLK SDATA
Figure 5. CPU Present Detect Hardware
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Note that either the pull-down resistors are installed, or the I2C EEPROM, but not both. For the simplest case, the three presence detect pins encode seven specific configurations of processor or processor / cache combinations, with one reserved for identification of the serial EEPROM method. The motherboard requires pullups on the parallel lines (1K to 10K ohms), and the PCM selectively pulls down the PID lines to create the PID encoding. The possible combinations of processor and cache with all the attendant settings are too numerous to directly encode in the three bits allotted, so predefined configurations are assigned an identifier. Additionally, the table used will be associated with the processor attached (determined by reading the processor PVR). Together, the processor ID register and PID bits are used to determine the most difficult cache settings, with the remainder handled by software, as shown in Table 4.
Parameter
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Cache size Processor core / cache bus clock ratio Cache type Cache enable Cache parity Cache write-through / copyback Cache output hold Cache clock type
PPD encoding
Table 5 shows example settings for an MPC750-based PCM with cache:
PID0-2 000 001
Cache / Core Ratio
Table 5. MPC750 Presence Detect Table
SRAM Type Late-write Pipelined Hold (ns) 0.5 0.5 Size 1M 512 K Example Module CPU / Cache 300 / 200 300 / 150 266 / 133 233 / 117 300 / 150 266 / 133 233 / 117 200 / 100 300 / 120 266 / 106 233 / 93 300 / 120 266 / 106 233 / 93 SRAM Speed 200 150 133 117 150 133 117 100 120 117 100 120 117 100
Pipelined
0.5 Pipelined 0.5 Pipelined 0.5
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Software Always 0.5 ns 1M 512 K 1M
PPD encoding
Software, or always off Software, or always copyback
If late-write: differential If pipelined: single-ended
Table 4. Processor Presence Detect (PPD) Information
Determined by
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Table 5. MPC750 Presence Detect Table (Continued)
PID0-2 101 Cache / Core Ratio 3:1 SRAM Type Pipelined Hold (ns) 0.5 Size 512 K Example Module CPU / Cache 300 / 100 266 / 88 300 / 100 266 / 88 SRAM Speed 100 90 100 90
Pipelined
No Module ID
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1.8.7.1 Presence Detect EEPROM Format
The format of the data is based upon the following criteria:
Minimize software impact by re-using memory SPD data formats. This also implies that littleendian multi-byte ordering is retained. Keep the block / length structure so that I2C readers can be re-used. The first few bytes should not be all ones, so that the I2C EEPROM reader routine can easily detect the presence / absence of data.
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The Software Presence Detect (SPD) describes the PCM but does not tell the software what register bits to use (interfaces change over time).
The data within presence detect EEPROM memory generally follows JEDEC DIMM outline and reuses the same data formats. The format is not JEDEC approved, and will not be since it cannot be shared with DIMM memory presence detect lines.
Either software or an I2C controller may be used to address EEPROM #2 (the address of the presence detect EEPROM) and load the configuration data.
For each new processor with cache a similar table will be created. If a PCM needs a particular combination that was not pre-defined in this table, then a serial presence detect EEPROM will be used. A serial EEPROM is detected when all ones are sensed on the PID lines. To determine the system configuration, software will have to read the data from the EEPROM, as shown in Figure 5.
Note that there are various cache speeds for each entry. The processor does not need to know the actual speed of its cache, only the proper ratio of core:cache, in order to properly configure the cache controller. If the cache speed is of interest, the bus frequency and PLL settings must be determined via software.
This indicates the presence of a serial EEPROM or non-cache PCM.
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Table 6 shows the PCM SPD format.
Table 6. PCM SPD Data Format
Byte 0 1 2 5, 6 7 Field NO SIZE TYPE WIDTH VID Description Number of bytes written into EEPROM Total number blocks of SPD RAM Module type Data width of module Voltage level of module (Mirrors VID encoding) Signaling level Range of Values 64, 128, 255 4, 8, 16 CPU 1-65536 3.3V 2.5V 80 08 00 Example
80, 00 12 1A 01 02 03 00 00
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SIGLEV
1:LVTTL 2:SSTL
TAU0 TAU100
TAU calibration, 0 °C TAU calibration, 100 °C
Reserved for other general information CTYPE Cache type
0 1M 2M 0 180 200 0-n
3:GTL -128.127 -128.127
0:None 1:Flow-through 2:Pipelined 3:Late-write
00 01 02 03 00, 00 00, 02 00, 04 00, 08 00, 00 B4, 00 C8, 00 00 01 00 05 10 15
CSIZE
Cache size LSB, MSB (K)
19, 20 CSPEED Cache speed LSB, MSB (MHz) 21 CCLOCK Cache clock type 22 CHOLD Cache output hold 23-31 32 CPUS CPU count
0:Single-ended 1:Differential 0.0 ns 0.5 ns 1.0 ns 1.5 ns
Reserved for other cache information 01
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Table 6. PCM SPD Data Format (Continued)
Byte 33 Field SPEED Description CPU speed LSB, MSB (MHz) 66 200 333 34, 35 BUSSPD Bus speed LSB, MSB (MHz) 66 100 36-63 64-67 68-90 MANUF CPUID Reserved for other CPU information Manufacturers ID CPU ID Manufacturers data Unused Stock name Range of Values Example 42, 00 C8, 00 4D, 01 42, 00 64, 00
Part marking TBD
"MOT" "MCM603RRX 366LARX" FF FF
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91-127 128-nnn
NO SIZE
TYPE WIDTH
VID SIGLEV
The type encoding field is zero to indicate that it is not a memory DIMM. This field is retained for compatibility with existing SPD standards. This field describes the width of the module. The value is the width of the PCM, either 0x0080 (64-bit) or 0x0100 (128-bit). This field is retained for compatibility with existing SPD standards. The VID field contains a copy of the encoding presented to the motherboard via the VID pins. Refer to the VRM table for the encoded values. The SIGLEV field contains an encoded description of the PCM interface level see Table 7.
Table 7. PCM Interface Level
Interface Level LVTTL SSTL GTL Code 01 02 03
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This field contains the total number of bytes written during manufacture. This field is retained for compatibility with existing SPD standards.
The fields of the EEPROM are described in detail as follows:
The first eight bytes are fairly similar to the DIMM SPDs in the hope that it will enable the EEPROM access software to retrieve a block from either SPD with minimal effort. Thereafter, the formats diverge but should allow the re-use of existing DIMM data conversion routines (for example, the format for output hold).
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Table 8. CTYPE Field Encoding
CTYPE 0 1 2 3 None Cache Type
Flow-through
CSIZE CSPEED CCLOCK CHOLD
The CSIZE field contains the size of the cache, in kilobytes. The CSPEED field contains the speed of the cache, in megahertz.
The CHOLD field contains the hold time needed for the cache memories, encoded in the pseudo-BCD method used for SPD data values. The lower nibble ranges from 0.9, and describes fractions of nanoseconds. The upper range is from 0.15, and is in nanoseconds. The lower nibble may be used as-is, or simply to round up the upper nibble, as needed. The CPUS field contains the number of CPUs present on the PCM. The SPEED field contains the maximum specified core operating speed of the CPU(s), in megahertz. The BUSSPD field contains the maximum specified bus operating speed of the CPU(s), in megahertz. The MANUF field contains the stock ticker symbol of the manufacturer of the CPU. The encoding method is ASCII unused bytes are filled with zero. The CPUID field contains the literal ASCII name (part ordering number) of the CPU(s) installed. For example, a 300 MHz PowerPC 603e would be encoded as MPC603RRX300LA. Unused bytes are filled with zeroes.
CPUS SPEED BUSSPD MANUF CPUID
The CCLOCK field is used to configure the L2 clock signals as single-ended (0 value) or differential (1 value).
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Pipelined
Late-write
CTYPE
The CTYPE field contains an encoding which indicates the type of cache attached to the processor dedicated L2 interface, if any. If zero is present, indicating no cache, none of the other cache parameters have any meaning see Table 8.
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1.9 Ordering Information
This section provides the part numbering nomenclature for the PCM. Note that the individual part numbers correspond to a particular PowerPC microprocessor at a maximum core frequency and a certain size of SRAM. Often the ratio of core to L2 frequency is called out in the part number also because this ratio and the maximum core frequency set the maximum frequency of the attached SRAM. These details for a particular part are provided in the part number specifications available from the Motorola PowerPC website at: http://www.mot.com / SPS / PowerPC / .
1.9.1 Part Number Key
Figure 6 provides an example of the part numbering scheme for the PCM.
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Product Code PPC-Sample XPC-XC Qualified MPC-MC Qualified Part Identifier 603, 604, 740, 750
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Figure 6. Motorola Part Number Key
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