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MPCPCMEC/D (Motorola Order Number) 8/97
Advance Information
PowerPC name registered trademark PowerPC logotype, PowerPC 603, PowerPC 603e, PowerPC trademarks International Busines Machines Corporation, used Motorola under license from International Business Machines Corporation. This document contains information product under development Motorola. Motorola reserves right change discontinue this product without notice. Motorola Inc., 1997. rights reserved.
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Hardware Specifications
This document must used conjunction with Motorola part number specification, located Motorola PowerPC website part number specifications describe configuration ordering information, provide references appropriate processor SRAM hardware specifications describe component parts particular PCM. order precedence such that microprocessor SRAM component documents such user's manuals hardware specifications take precedence unless otherwise indicated this document (for example, packaging pinout). part number specifications take precedence over this document areas addresses (for example, specifics part numbers, configurations, requisite application relief electrical parameters.)
Processor Cache Module (PCM) grid array (PGA) circuit assembly which combines PowerPC® microprocessor SRAM components into subsystem. provides standard mechanical, electrical, functional interface which socketed computer system board allow many combinations processors optional components easily interchanged. This document describes general characteristics module consisting single PowerPC microprocessor SRAM devices cache. packaging signal definition also accomodates single processors without SRAM, multiple processors.
Processor Cache Module Hardware Specifications
This document contains following topics:
Topic Page
Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical Thermal Characteristics" Section 1.5, "Pin Assignments" Section 1.6, "Pinout Listings" Section 1.7, "Package Description" Section 1.8, "System Design Information" Section 1.9, "Ordering Information"
This section summarizes features PCM. Major features follows:
connect 360-lead CBGA PowerPC microprocessor 288-pin PGA. interconnection area between processor SRAM memory when configured with cache. (When MPC750 microprocessor configured support cache, L2address data buses entirely contained processor module without increase number pins complexity system designer.) Additional power supply filtering processor module voltage supply (AVdd) filtering close processor improves noise immunity. Core voltage (Vdd) filtering reduces voltage variations.
signals determine selection processor voltage identification module type Direct encoding control power supply modules Four voltage pins select operating core voltage from 1.3V 3.5V. Encodings match industry-standard power-controllers. Self-identification module 3-pin encoding simple modules. Serial EEPROM encoding complex modules.
same signals system interface operation attached PowerPC processor would provide 255-pin CBGA package.
Features
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circuit assembly which combines PowerPC microprocessor SRAM components into subsystem. consists epoxy-glass (FR4) substrate which adapts processor ceramic ball grid array (CBGA) package with spacing 288-pin with spacing that easily socketed hence, easily upgraded. substrate extended beyond area grid array provide interconnect area SRAM components configured closely coupled cache. resulting provides numerous flexible configurations processor cache various price/performance system designs.
Overview
locate published errata updates this document, refer website http://www.mot.com/ SPS/PowerPC/.
General Parameters
following list provides summary general parameters with MPC750 processor Kbytes, Kbytes, Mbyte SRAM: Technology Size Transistor Count Package Core Power Supply Power Supply General Parameters individual components. General Parameters individual components. General Parameters individual components. grid array Generally refer part number specifications specific part accurate information
Electrical Thermal Characteristics
electrical specifications identical electrical specifications attached microprocessor unless otherwise specified part number specifications particular module. thermal characteristics generally composite thermal characteristics attached microprocessor SRAMs. variety processor SRAM speeds possible dictate that thermal characteristics unique particular module therefore described associated part number specifications.
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Assignments
Figure part shows pinout viewed from surface. Part shows side profile module indicate direction surface view.
Part
Part
CBGA Substrate Microprocessor CQFP Packaged SRAM View
Figure Processor Cache Module Pinout
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Scale
Pinout Listings
Table provides pinout listing PCM. This pinout superset PCMs should followed maximum interchangeability between modules; however, particular implementations connect signals between pins PowerPC microprocessor. individual part number specifications specific pinouts part number.
Table Pinout Listing Module
Signal Name A[0-31] Number F13, D17, E16,F1, E17, F15, G13, F17, G14, G15, G16, G17, H13, H15, H17, J13, K13, Active
AACK
High
High High High High
Input Output Input Input Input Input Output Output Output Output Input Output Output Input Input Input Input
AP[0-3] ARRAY_WR2 ARTRY AVDD CLK_OUT CKSTP_IN CKSTP_OUT CSE0-CSE11 DBDIS DBG2 DBWO DH[0-31]
DL[0-31]
P13, N12, T15, U15, R13, U14, N10,P11, T11, U11, R10, U10, N9,P9, T7,U6, R5,U3 L16, K15, M17, L14, N17, M15, N16, L13, M13, N15, P17, R17, N14, P15, R16, U16, R14, N11, T13, R12, U13, R11, U12,
High
DP[0-7]
High
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Table Pinout Listing Module (Continued)
Signal Name DRTRY DRVMOD[0-1] B10, B14, D12, D16,F4, F10, F12, F14, G11, H10, H12, H16, J11, K10, K12, K16, L11, M10, M12, M14, P12, P16, T10, Number Active Output Input Input Input
HALTED
High High High High Output Input Input Input Input Input Input Input Input Input Input High High Input Input Output Output Input Input Input Input Input Input
HRESET INT2 LSSD_MODE2 L1_TSTCLK L2_INT L2_TSTCLK2 NAP_RUN OVDD3
PID[0-2] PLL_CFG[0-3] QACK QREQ RSRV SCLK SDATA SRESET SYSCLK SYSCLK2
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B12, B16, D10, D14, F16, H14, J12, K14, M16, P10, P14, T12, A10, A13,
Table Pinout Listing Module (Continued)
Signal Name TBEN TBST TC[0-2]4 TLBISYNC E11, A15, Number Active High High High Input Output Input Input Output Input Input Input Input Input Input Output Output
High High High High High High
TRST TSIZ[0-2] TT[0-4] VDD3 VID[0-4] XATS1 Notes:
A16, C14, C16, C17,
F11, G10, G12, H11, J10, K11, L10, L12,
These test signals factory only must pulled normal machine operation. OVdd inputs supply power drivers inputs supply power processor core. defined PowerPC 604TM-class processors only. These signals undefined must left disconnected.
Many signals have same definition timing that attached processor. actual signals present vary depending upon type PowerPC microprocessor used; refer corresponding processor hardware specifications details. implements several signals that part PowerPC specification, particular PowerPC processor. These pins unique used operational parameters indicate features provides. Table describes functions signals provided identification configuration PCM.
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recommended designs.
Table Unique/Redefined Pins
Name VID[4-0] Definitions pins encode voltage encoding described Section 1.8.6, "Voltage Encoding." Note little-endian ordering, used compatibility with industry standard parts. Notes These pins must pulled power controller proper operation. pullups must wired voltage level which stable while power controller ramps after power Many power controllers include internal pullups handle this.
PID[0-2]
SYSCLK2
Clock second processor. Same timing SYSCLK PowerPC CPUs.
INT2
DBG2
SCLK
serial clock input
Data grant second processor. Same timing PowerPC CPUs.
grant second processor. Same timing PowerPC CPUs.
request second processor. Same timing PowerPC CPUs.
Interrupt second processor. Same timing PowerPC CPUs.
SDATA
command input/ data output
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Unused signal-Reserved future function; signal should remain disconnected
Unused signal-Reserved future function; signal should remain disconnected
Unused signal-Reserved future function; signal should remain disconnected Unused signal-Reserved future function; signal should remain disconnected Unused signal-Reserved future function; signal should remain disconnected Connected when EEPROM presence detect mode implemented. Connected when EEPROM presence detect mode implemented.
PLL[0-3]
Specified setting use.
These pins connected ground PLL-encoded ordered; otherwise, motherboard control CPU's pins directly usual with PowerPC CPUs.
pins carry presence detect codes described Section 1.8.7, "Presence Detect."
These pins must pulled system with pullup resistors.
Package Description
following sections provide package parameters mechanical dimensions PCM.
1.7.1 Package Parameters
package parameters provided following list. package consists 288-lead grid array (PGA) bottom 1.75 inch glass-epoxy (FR4) substrate with PowerPC microprocessor ceramic ball grid array (CBGA) package fast static RAMs (FSRAMs) ceramic quad flat pack (CQFP) plastic ball grid array (PBGA) packages attached top. package parameters are: Package outline Interconnects 1.75 2.50 0.018 .180 .215
Diameter Length Lead Plating Module Height without pins
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Pitch
Freescale Semiconductor, Inc. 1.7.2 Mechanical Dimensions
Figure provides mechanical dimensions PCM.
(D4)
(D5) NOTES: DIMENSIONS TOLERANCING ASME Y14.5M, 1994. DIMENSIONS INCHES. SIDE CORNER INDEX SILK SCREENED ARRAY DIMENSIONS LESSTHAN EQUAL MINIMUM HANDLING CLEARANCE BETWEEN PACKAGE EDGE PASSIVE COMPONENTS 0.020.
(E4)
(E5)
(E3)
(E7)
(E6)
CORNER
(D6) (D3) VIEW
(D7)
Inches 0.390 0.420 0.170 0.190 0.065 0.090 0.115 0.055 0.063 0.098 0.0980 0.132 0.016 0.020 2.480 2.550 Note 1.600 0.984 0.870 0.787 0.532 0.560 0.100 1.740 1.780 Note 1.600 0.984 0.630 0.551 0.532 0.420
(D2) BOTTOM VIEW
288X
(E2)
0.030 0.010 SIDE VIEW
Figure Mechanical Dimensions Bottom Surface Nomenclature
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System Design Information
Refer device-specific user's manuals hardware specifications system design information about processor SRAM attached module. This section provides descriptions functionality electrical thermal design recommendations unique PCM.
1.8.1 Configuration
system utilizing expected configure processor PLL_CFG[0-3] signals appropriate attached processor. given SYSCLK (bus) frequency, configuration signals internal frequency operation. Refer system design information appropriate processor's hardware specifications appropriate settings. possible during manufacture settings PLL_CFG[0-3] jumpers substrate particular combination that will independent signals asserted system pins; this done particular part number, will noted part number specifications that specific part.
1.8.2 Power Supply Filtering
AVdd power signal provides power clock generation phase-locked loop. ensure stability internal clock, power supplied AVdd input signal microprocessor should electrically quiet possible. maximum effectiveness filter circuit Figure which normally recommended inclusion system design been included itself.
AVdd L2AVdd)
Figure Power Supply Filter Circuit
resistors used program connection between external signals microprocessor supply shown Figure required, system provide additional power supply filtering AVdd signal, shown Figure AVdd signal. provides AVdd power supply filtering shown Figure
External External AVdd Internal AVdd Internal L2AVDD
Figure Power Supply Filter Circuit
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interface between processor SRAMs module will operate CPU-to-L2 frequency divisors ÷1.5, ÷2.5, These ratios will have programmed into cache control registers processor operating system cache enabled before SRAM will functional module. part number specifications CPU-to-L2 frequency divisor(s) supported particular part.
Freescale Semiconductor, Inc. 1.8.3 Decoupling Recommendations
microprocessor cache generate transient power surges high frequency noise power supply, especially while driving large capacitive loads. This noise must prevented from reaching other components system, module itself requires clean, tightly regulated source power. Therefore, recommended that system designer place least decoupling capacitor each OVdd module. also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, power planes PCB, utilizing short traces minimize inductance.
Power ground connections must made external Vdd, OVdd, pins PCM.
provides additional pins communicate attached processor's preferred core voltage. desired voltage setting encoded VID[4-0] signals. This 5-bit encodes various voltage settings which match existing industry standards. most systems these signals connected directly Voltage Regulator Module (VRM) on-board power supply which accepts encoded voltage setting. encoding voltage levels supported shown Table
Table Voltage Encoding
VID[4-0] Output 01111 01110 01101 01100 01011 01010 01001 01000 Voltage 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 VID[4-0] Output 10000 10001 10010 10011 10100 10101 10110 10111 Voltage 3.50 3.40 3.30 3.20 3.10 3.00 2.90 2.80
core operating voltage (Vdd AVdd) PowerPC processors varied with semiconductor process technology. Within narrow range determined process technology, Motorola specified nonstandard core voltages some processors device-specific part number specifications.
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1.8.6 Voltage Encoding
specifically designed flexibility socket. footprint compatible with widely available Socket footprint popular industry. Several vendors provide this socket, including Incorporated (part number: 916668-1).
1.8.5 Socketing
ensure reliable operation, highly recommended connect unused inputs appropriate signal level. Unused active inputs should tied Vdd. Unused active high inputs should connected GND. (no-connect) signals must remain unconnected.
1.8.4 Connection Recommendations
module will provide some bulk decoupling high frequency decoupling capacitors module itself improve overall system noise immunity.
Table Voltage Encoding (Continued)
VID[4-0] Output 00111 00110 00101 00100 00011 00010 00001 00000 Voltage 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 VID[4-0] Output 11000 11001 11010 11011 11100 11101 11110 11111 Voltage 2.70 2.60 2.50 2.40 2.30
provides means self-identification (called presence detection after method(s) used identify memory cache modules). module implements three-wire solution which combines inexpensive parallel encoding Single In-line Memory Modules (SIMMs) with more flexible serial solution found Dual In-line Memory Modules (DIMMs). Figure shows architecture presence detection:
1.8.7 Presence Detect
encodes voltage setting selectively installing 0-ohm resistors bus. regulator must have internal pullups properly encode settings (this true known 5-bit encoded switching controllers).
Note: numbering shown here little-endian pre-existing standards. This differs from most other PowerPC numbering conventions.
2.20 2.10
PID0 PID1 PID2
SCLK SDATA
Figure Present Detect Hardware
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Note that either pull-down resistors installed, EEPROM, both. simplest case, three presence detect pins encode seven specific configurations processor processor/cache combinations, with reserved identification serial EEPROM method. motherboard requires pullups parallel lines ohms), selectively pulls down lines create encoding. possible combinations processor cache with attendant settings numerous directly encode three bits allotted, predefined configurations assigned identifier. Additionally, table used will associated with processor attached (determined reading processor PVR). Together, processor register bits used determine most difficult cache settings, with remainder handled software, shown Table
Parameter
Cache size Processor core/cache clock ratio Cache type Cache enable Cache parity Cache write-through/copyback Cache output hold Cache clock type
encoding
Table shows example settings MPC750-based with cache:
PID[0-2]
Cache/Core Ratio
Table MPC750 Presence Detect Table
SRAM Type Late-write Pipelined Hold (ns) Size Example Module CPU/Cache 300/200 300/150 266/133 233/117 300/150 266/133 233/117 200/100 300/120 266/106 233/ 300/120 266/106 233/ SRAM Speed
Pipelined
Pipelined Pipelined
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Software Always
encoding
encoding
Software, always Software, always copyback
late-write: differential pipelined: single-ended
Table Processor Presence Detect (PPD) Information
Determined
Table MPC750 Presence Detect Table (Continued)
PID[0-2] Cache/Core Ratio SRAM Type Pipelined Hold (ns) Size Example Module CPU/Cache 300/100 266/ 300/100 266/88 SRAM Speed
Pipelined
Module
1.8.7.1 Presence Detect EEPROM Format
format data based upon following criteria:
Minimize software impact re-using memory data formats. This also implies that littleendian multi-byte ordering retained. Keep block/length structure that readers re-used. first bytes should ones, that EEPROM reader routine easily detect presence/absence data.
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Software Presence Detect (SPD) describes does tell software what register bits (interfaces change over time).
data within presence detect EEPROM memory generally follows JEDEC DIMM outline reuses same data formats. format JEDEC approved, will since cannot shared with DIMM memory presence detect lines.
Either software controller used address EEPROM (the address presence detect EEPROM) load configuration data.
each processor with cache similar table will created. needs particular combination that pre-defined this table, then serial presence detect EEPROM will used. serial EEPROM detected when ones sensed lines. determine system configuration, software will have read data from EEPROM, shown Figure
Note that there various cache speeds each entry. processor does need know actual speed cache, only proper ratio core:cache, order properly configure cache controller. cache speed interest, frequency settings must determined software.
This indicates presence serial EEPROM non-cache PCM.
Table shows format.
Table Data Format
Byte Field SIZE TYPE WIDTH Description Number bytes written into EEPROM Total number blocks Module type Data width module Voltage level module (Mirrors encoding) Signaling level Range Values 128, 1-65536 3.3V 2.5V Example
SIGLEV
1:LVTTL 2:SSTL
11-15
TAU0 TAU100
calibration, calibration,
Reserved other general information CTYPE Cache type
3:GTL -128.127 -128.127
0:None 1:Flow-through 2:Pipelined 3:Late-write
CSIZE
Cache size LSB,
CSPEED Cache speed LSB, (MHz) CCLOCK Cache clock type CHOLD Cache output hold 23-31 CPUS count
512K
0:Single-ended 1:Differential
Reserved other cache information
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Table Data Format (Continued)
Byte Field SPEED Description speed LSB, (MHz) BUSSPD speed LSB, (MHz) 36-63 64-67 68-90 MANUF CPUID Reserved other information Manufacturers Manufacturers data Unused Stock name Range Values Example
Part marking
"MOT" "MCM603RRX 366LARX"
91-127 128-nnn
SIZE
TYPE WIDTH
SIGLEV
type encoding field zero indicate that memory DIMM. This field retained compatibility with existing standards. This field describes width module. value width PCM, either 0x0080 (64-bit) 0x0100 (128-bit). This field retained compatibility with existing standards. field contains copy encoding presented motherboard pins. Refer table encoded values. SIGLEV field contains encoded description interface level; Table
Table Interface Level
Interface Level LVTTL SSTL Code
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This field contains number 16-byte blocks available EEPROM. value 0x10 indicates EEPROM bytes long. This field retained compatibility with existing standards.
This field contains total number bytes written during manufacture. This field retained compatibility with existing standards.
fields EEPROM described detail follows:
first eight bytes fairly similar DIMM SPDs hope that will enable EEPROM access software retrieve block from either with minimal effort. Thereafter, formats diverge should allow re-use existing DIMM data conversion routines (for example, format output hold).
This field describes calibration factors necessary temperature compensate thermal assist unit (TAU), such found MPC750 processors. current units have high relative accuracy, absolute accuracy ±12°C. With appropriate compensation factors stored EEPROM, TAU-handling software determine temperature specified accuracy. parameters describe numerical offset applied 100°C. software elect adjust temperature over described interval greatest accuracy (using linear interpolation), apply only 100°C factor faster compensation (with less accuracy).
Table CTYPE Field Encoding
CTYPE None Cache Type
Flow-through
CSIZE CSPEED CCLOCK CHOLD
CSIZE field contains size cache, kilobytes. CSPEED field contains speed cache, megahertz.
CHOLD field contains hold time needed cache memories, encoded pseudo-BCD method used data values. lower nibble ranges from 0.9, describes fractions nanoseconds. upper range from 0.15, nanoseconds. lower nibble used as-is, simply round upper nibble, needed. CPUS field contains number CPUs present PCM. SPEED field contains maximum specified core operating speed CPU(s), megahertz. BUSSPD field contains maximum specified operating speed CPU(s), megahertz. MANUF field contains stock ticker symbol manufacturer CPU. encoding method ASCII; unused bytes filled with zero. CPUID field contains literal ASCII name (part ordering number) CPU(s) installed. example, PowerPC 603ewould encoded MPC603RRX300LA. Unused bytes filled with zeroes.
CPUS SPEED BUSSPD MANUF CPUID
CCLOCK field used configure clock signals single-ended value) differential value).
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Pipelined
Late-write
CTYPE
CTYPE field contains encoding which indicates type cache attached processor dedicated interface, any. zero present, indicating cache, none other cache parameters have meaning; Table
Ordering Information
This section provides part numbering nomenclature PCM. Note that individual part numbers correspond particular PowerPC microprocessor maximum core frequency certain size SRAM. Often ratio core frequency called part number also because this ratio maximum core frequency maximum frequency attached SRAM. These details particular part provided part number specifications available from Motorola PowerPC website
1.9.1 Part Number
Figure provides example part numbering scheme PCM.
Product Code PPC-Sample XPC-XC Qualified MPC-MC Qualified Part Identifier 603*, 604, 740,
Revision Level Application Modifier example, core:L2 core:L2 core:L2 Max. Internal Processor Speed Package Code RC-PGA with gold pins IP-PGA IM-MCM
Note: term `603' used abbreviation `PowerPC 603TM'
Part Modifier Enhanced (603/604 only) Low-Voltage 740/750 cache with 256K pipeline burst with pipeline burst with late write flow-through with 512K pipeline burst
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Figure Motorola Part Number
Information this document provided solely enable system software implementers PowerPC microprocessors. There express implied copyright licenses granted hereunder design fabricate PowerPC integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Mfax trademark Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. trademark International Business Machines Corporation. PowerPC name registered trademark PowerPC logotype, PowerPC 603, PowerPC 603e, PowerPC trademarks International Business Machines Corporation used Motorola under license from International Business Machines Corporation. Motorola Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. 5405; Denver, Colorado 80217; Tel.: 1-800-441-2447 1-303-675-2140; World Wide Address: http://ldc.nmd.com/ JAPAN: Nippon Motorola SPD, Strategic Planning Office 4-32-1, Nishi- Gotanda Shinagawa-ku, Tokyo 141, Japan Tel.: 81-3-5487-8488 ASIA/PACIFC: Motorola Semiconductors H.K. Ltd.; Ping Industrial Park, Ting Road, N.T., Hong Kong; Tel.: 852-26629298 MfaxTM: RMFAX0@email.sps.mot.com; TOUCHTONE 1-602-244-6609; Canada ONLY (800) 774-1848; World Wide Address: http://sps.motorola.com/mfax INTERNET: home-http://motorola.com/sps Technical Information: Motorola Inc. Customer Support Center 1-800-521-6274; electronic mail address: crc@wmkmail.sps.mot.com. Document Comments: (512) 891-2638, Attn: RISC Applications Engineering. World Wide Addresses: http://www.mot.com/SPS/PowerPC/ MPCPCMEC/D
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