SKEW, 1-TO-12 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Ful
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ICS87973I-147
SKEW, 1-TO-12 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Fully integrated LVCMOS/LVTTL outputs; (12) clock, feedback, sync Selectable LVCMOS/LVTTL differential CLK, nCLK inputs CLK0, CLK1 accept following input levels: LVCMOS LVTTL CLK, nCLK pair accept following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Output frequency range: 10MHz 150MHz range: 240MHz 500MHz Output skew: 200ps (maximum) Cycle-to-cycle jitter, (all banks 55ps (maximum) Full 3.3V supply voltage -40°C 85°C ambient operating temperature compatible with MPC973 Compatible with PowerPCand PentiumMicroprocessors
GENERAL DESCRIPTION
HiPerClockS
ICS87973I-147 LVCMOS/LVTTL clock generator member HiPerClockSTMfamily High Performance Clock Solutions from ICS. ICS87973I-147 three selectable inputs provides LVCMOS/LVTTL outputs.
ICS87973I-147 highly flexible device. three selectable inputs differential single ended inputs) often used systems requiring redundant clock sources. three different output frequencies generated among three output banks. three output banks feedback output each have their output dividers which allows device generate multitude different bank frequency ratios output-to-input frequency ratios. addition, outputs Bank (QC2, QC3) selected inverting non-inverting. output frequency range 10MHz 150MHz. input frequency range 6MHz 120MHz. ICS87973I-147 also QSYNC output which used system synchronization purposes. monitors Bank Bank outputs goes period prior coincident rising edges Bank Bank clocks. QSYNC then goes high again when coincident rising edges Bank Bank occur. This feature used primarily applications where Bank Bank running different frequencies, particularly useful when they running non-integer multiples another. Example Applications: System Clock generator: 16.66MHz reference clock generate eight 33.33MHz copies four 100MHz copies PCI-X. Line Card Multiplier: Multiply differential 62.5MHz from back plane single-ended 125MHz line Card ASICs Gigabit Ethernet Serdes. Zero Delay buffer Synchronous memory: twelve 100MHz copies from memory controller reference clock memory chips memory module with zero delay.
ASSIGNMENT
EXT_FB GNDO GNDO GNDO VDDO VDDO
FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 VDDO GNDO VDDO GNDO VCO_SEL
GNDI
FSEL_FB0
FSEL_FB1 QSYNC GNDO VDDO FSEL_C0 FSEL_C1 VDDO GNDO INV_CLK
ICS87973I-147
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2 PLL_SEL
REF_SEL CLK_SEL
CLK0 CLK1 nCLK VDDA
52-Lead LQFP 10mm 10mm 1.4mm package body package View
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BLOCK DIAGRAM
VCO_SEL PLL_SEL REF_SEL nCLK CLK0 CLK1 CLK_SEL EXT_FB PHASE DETECTOR
SYNC SYNC SYNC SYNC
SYNC SYNC SYNC SYNC
FSEL_FB2
nMR/OE POWER-ON RESET FSEL_B0:1 FSEL_C0:1 FSEL_FB0:2 DATA GENERATOR SYNC PULSE
SYNC
SYNC SYNC
FSEL_A0:1
SYNC
QSYNC
FRZ_CLK OUTPUT DISABLE CIRCUITRY
FRZ_DATA
INV_CLK
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nMR/OE
SIMPLIFIED BLOCK DIAGRAM
FSEL_A[0:1]
nCLK CLK0 CLK1 CLK_SEL REF_SEL EXT_FB
RANGE 240MHz 500MHz
FSEL_
SYNC SYNC SYNC SYNC
FSEL_B[0:1]
VCO_SEL
PLL_SEL
FSEL_
SYNC SYNC SYNC SYNC
FSEL_C[0:1]
FSEL_
SYNC
SYNC SYNC
INV_CLK FSEL_FB[0:2]
FSEL_
FRZ_CLK FRZ_DATA
OUTPUT DISABLE CIRCUITRY SYNC
QSYNC
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SKEW, 1-TO-12 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Description Power supply ground. Master reset output enable. When HIGH, enables outputs. When LOW, resets outputs tristate resets output divide circuitr Enables disables outputs. LVCMOS LVTTL interface levels. Clock input freeze circuitr LVCMOS LVTTL interface levels. Configuration data input freeze circuitr LVCMOS LVTTL interface levels. Select pins control Feedback Divide value. LVCMOS LVTTL interface levels. Selects between reference clocks input output dividers. When HIGH, selects PLL. When LOW, bypasses PLL. LVCMOS LVTTL interface levels. Selects between CLK0 CLK1 CLK, nCLK inputs. When HIGH, selects CLK, nCLK. When LOW, selects CLK0 CLK1. LVCMOS LVTTL interface levels. Clock select input. Selects between CLK0 CLK1 phase detector reference. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS LVTTL interface levels. Reference clock inputs. LVCMOS LVTTL interface levels. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Analog supply pin. Pullup Inver clock select outputs. LVCMOS LVTTL interface levels. Power supply ground. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins. Pullup Select pins Bank outputs. LVCMOS LVTTL interface levels. Synchronization output Bank Bank Refer Figure Timing Diagrams. LVCMOS LVTTL interface levels. Core supply pins. Feedback clock output. LVCMOS LVTTL interface levels. Pullup Extended feedback. LVCMOS LVTTL interface levels. Bank clock outputs.7 typical output impedance. LVCMOS LVTTL interface levels. Pullup Pullup Select pins Bank outputs. LVCMOS LVTTL interface levels. Select pins Bank outputs. LVCMOS LVTTL interface levels. Bank clock outputs.7 typical output impedance. LVCMOS LVTTL interface levels. Selects VCO. When HIGH, selects When LOW, selects LVCMOS LVTTL interface levels.
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TABLE DESCRIPTIONS
Number Name GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2, FSEL_FB1, FSEL_FB0 PLL_SEL Power Input Input Input Input Pullup Pullup Pullup Pullup
Input
Pullup
REF_SEL
Input
Pullup
CLK_SEL CLK0, CLK1 nCLK VDDA INV_CLK GNDO QC3, QC2, QC1, VDDO FSEL_C1, FSEL_C0 QSYNC EXT_FB QB3, QB2, QB1, FSEL_B1, FSEL_B0 FSEL_A1, FSEL_A0 QA3, QA2, QA1, VCO_SEL
Input Input Input Input Power Input Power Output Power Input Output Power Output Input Output Input Input Output Input
Pullup Pullup Pullup
Pullup
NOTE: Pullup refer internal input resistors. table Characteristics, typical values.
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SKEW, 1-TO-12 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions Minimum Typical VDD, VDDA, VDDO 3.465V Maximum Units
TABLE CHARACTERISTICS
Symbol RPULLUP, RPULLDOWN ROUT Parameter Input Capacitance Input Pullup/Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance
TABLE OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs FSEL_A1 FSEL_A0 Outputs Inputs FSEL_B1 FSEL_B0 Outputs Inputs FSEL_C1 FSEL_C0 Outputs
TABLE FEEDBACK CONFIGURATION SELECT FUNCTION TABLE
Inputs FSEL_FB2 FSEL_FB1 FSEL_FB0 Outputs
TABLE CONTROL INPUT SELECT FUNCTION TABLE
Control VCO_SEL REF_SEL CLK_SEL PLL_SEL nMR/OE INV_CLK Logic VCO/2 CLK0 CLK1 CLK0 BYPASS Master Reset/Output Non-Inver QC2, Logic CLK, nCLK CLK1 Enable Enable Outputs Inver QC2,
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MODE
fVCO
QSYNC
MODE
QSYNC
MODE
QC(÷2) QA(÷4) QSYNC
MODE
QC(÷2) QA(÷8) QSYNC
MODE
QC(÷2) QA(÷8) QSYNC
MODE
QA(÷6) QC(÷8) QSYNC
MODE
QA(÷12) QC(÷2) QSYNC
FIGURE TIMING DIAGRAMS
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4.6V -0.5V -0.5V VDDO 0.5V 42.3°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 2.935 3.135 Typical Maximum 3.465 3.465 3.465 Units
NOTE: Special thermal handling required some configurations.
TABLE DIFFERENTIAL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter VCMR Input High Voltage Input Voltage Input Current Output High Voltage Output Voltage Peak-to-Peak Input Voltage; NOTE Common Mode Input Voltage; NOTE -20mA 20mA CLK, nCLK CLK, nCLK 0.6V LVCMOS Inputs LVCMOS Inputs Test Conditions Minimum -0.3 Typical Maximum ±120 Units
NOTE Common mode voltage defined differential signal. NOTE single ended applications, maximum input voltage nCLK 0.3V.
TABLE INPUT FREQUENCY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input Frequency Test Conditions Minimum Typical Maximum Units CLK0, CLK1, CLK, nCLK; NOTE FRZ_CLK NOTE Input frequency depends feedback divide ratio ensure "clock Feedback Divide" range 240MHz 500MHz.
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Test Conditions Minimum Typical Maximum 83.33 62.5 -130 Banks 0.8V Units
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter
fMAX
Output Frequency
CLK0 Static Phase Offset; CLK1 NOTE CLK, nCLK Output Skew; NOTE Cycle-to-Cycle Jitter; NOTE Lock Range Lock Time; NOTE Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE Output Disable TIme; NOTE
Frequency 50MHz
tsk(o) tjit(cc)
fVCO tLOCK tPZL, tPZH tPLZ, tPHZ
NOTE Defined time difference between input reference clock average feedback input signal when locked input reference frequency stable. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDO/2. NOTE These parameters guaranteed characterization. tested production. NOTE This parameter defined accordance with JEDEC Standard
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PARAMETER MEASUREMENT INFORMATION
1.65V±5%
VDD, VDDA, VDDO
SCOPE
nCLK
LVCMOS
Cross Points
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
QA0:QA3, QB0:QB3, QC0:QC3, QSYNC,
DIFFERENTIAL INPUT LEVEL
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
nCLK
EXT_FB
mean Static Phase Offset
(where random sample, mean average sampled cycles measured controlled edges)
(where random sample, mean average sampled cycles measured controlled edges)
STATIC PHASE OFFSET (DIFFERENTIAL)
STATIC PHASE OFFSET (LVCMOS)
0.8V
0.8V
Clock Outputs
QA0:QA3, QB0:QB3, QC0:QC3, QSYNC,
OUTPUT RISE/FALL TIME
87973DYI-147
OUTPUT DUTY CYCLE/ PULSE WIDTH PERIOD
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tcycle
sk(o)
OUTPUT SKEW
CLK0, CLK1
EXT_FB
mean Static Phase Offset
Pulse Width
PERIOD
PERIOD
ICS87973I-147
SKEW, 1-TO-12 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION
USING OUTPUT FREEZE CIRCUITRY
OVERVIEW
enable power states within system, each output ICS87973I-147 (Except QFB) individually frozen (stopped logic state) using simple serial interface shift register. serial interface chosen eliminate need each output have Output Enable pin, which would dramatically increase count package cost. Common sources system that used drive ICS87973I-147 serial interface FPGA's ASICs. edge FRZ_CLK signal. place output freeze state, logic must written respective freeze enable shift register. unfreeze output, logic must written respective freeze enable bit. Outputs will become enabled/disabled until data bits shifted into shift register. When data bits shifted register, next rising edge FRZ_CLK will enable disable outputs. that following 12th register logic "0", used start next cycle; otherwise, device will wait won't start next cycle until sees logic bit. Freezing unfreezing output clock synchronous (see timing diagram below). When going into frozen state, output clock will time would normally LOW, freeze logic will keep output until unfrozen. Likewise, when coming frozen state, output will HIGH only when would normally HIGH. This logic, therefore, prevents runt pulses when going into frozen state.
PROTOCOL
Serial interface consists pins, FRZ_Data (Freeze Data) FRZ_CLK (Freeze Clock). Each outputs which frozen freeze enable shift register. sequence started supplying logic start followed 12NRZ freeze enable bits. period each FRZ_DATA equals period FRZ_CLK signal. FRZ_DATA serial transmission should timed ICS87973I-147 sample each FRZ_DATA with rising
FRZ_DATA
QSYNC
FRZ_CLK
FIGURE FREEZE DATA INPUT PROTOCOL
FREEZE Internal
Internal
FIGURE OUTPUT DISABLE TIMING
87973DYI-147
Latched
Clocked
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POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87973I-147 provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA pin.
3.3V .01µF .01µF
FIGURE POWER SUPPLY FILTERING
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VDD/2 generated bias resistors This bias circuit should located close possible input pin. ratio
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Single Ended Clock Input V_REF nCLK 0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested
3.3V 3.3V
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V 3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
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logic control input pull up/down power supply filtering. this example, clock input driven LVCMOS driver.
SCHEMATIC EXAMPLE
Figure shows schematic example using ICS87973I-147. This example shows general design input, output termination,
Serial Clcok Serial Data
VCO_SEL GNDO VDDO GNDO VDDO FSEL_A0 FSEL_A1 FSEL_B0 FSEL_B1
LVCMOS CLOCK 0.01u
GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 nCLK VDDA INV_CLK GNDO VDDO FSEL_C1 FSEL_C0 VDDO GNDO QSYNC FSEL_FB1
GNDO VDDO GNDO VDDO EXT_FB GNDO FSEL_FB0
ICS87973I-147
Logic Input Examples
Logic Input
Logic Input
Install
Logic Input pins
Install
Logic Input pins
(U1-17)
(U1-22)
(U1-28)
(U1-33)
(U1-37)
(U1-45)
(U1-49)
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VDD=3.3V
FIGURE ICS87973I-147 SCHEMATIC EXAMPLE
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SKEW, 1-TO-12 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87973I-147 8364
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LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.22 0.09 MINIMUM NOMINAL -1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC -0.75 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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Marking ICS7973DI147 ICS7973DI147 Package Lead LQFP Lead LQFP Tape Reel Count tray Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87973DYI-147 ICS87973DYI-147T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87973DYI-147
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