SST27SF512, SST27VF512 FEATURES: 5.0-Volt Read Operation 27SF512
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Kilobit (64K SuperFlash
SST27SF512, SST27VF512
FEATURES: 5.0-Volt Read Operation 27SF512 2.7-Volt Read Operation 27VF512 Superior Reliability Endurance: Minimum 1000 Cycles Greater than years Data Retention Power Consumption Active Current: (typical) 10mA (typical) 2.7V Standby Current: (typical) both 27SF512 27VF512 Fast Access Time 5.0-Volt Read 2.7-Volt Read
Fast Programming Operation byte second entire chip Features Electrical Erase Does Require Source Chip Erase Time: Compatibility JEDEC Standard Byte-wide EPROM Pinouts Power Supply Programming/Erase Packages Available 32-Pin PLCC Plastic TSOP
PRODUCT DESCRIPTION 27SF512/27VF512 CMOS, many-time programmable (MTP) cost flash, manufactured with SST's proprietary, high performance SuperFlash technology. split gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. 27SF512/ 27VF512 electrically erased programmed least 1000 times using external programmer. 27SF512/27VF512 have erased prior programming. 27SF512/27VF512 conform JEDEC standard pinouts byte-wide memories. Featuring high performance byte programming, 27SF512/27VF512 provide byte-program time entire memory programmed byte byte seconds. Designed, manufactured, tested wide spectrum applications, 27SF512/27VF512 offered with endurance 1000 cycles. Data retention rated greater than years. 27SF512/27VF512 suited applications that require infrequent writes power nonvolatile storage. 27SF512/27VF512 will improve flexibility, efficiency, performance while matching cost nonvolatile applications that currently UV-EPROMs, OTPs, mask ROMs. meet surface mount conventional through hole requirements, 27SF512/27VF512 offered 32pin PLCC, 28-pin PDIP 28-pin TSOP packages. Figures pinouts.
Device Operation 27SF512/27VF512 cost flash solutions that used replace existing UV-EPROM, OTP, mask sockets. They functionally (read program) compatible with industry standard EPROM products. addition EPROM functionality, device also supports Electrical Erase operation external programmer. 27SF512/27VF512 require source erase, therefore packages have window. Read Read operation 27SF512/27VF512 controlled OE#. Both have system obtain data from outputs. Once address stable, address access time equal delay from output (TCE). Data available output after delay from falling edge OE#, assuming that been addresses have been stable least TOE. When high, chip deselected typical standby current consumed. output control used gate data from output pins. data high impedance state when either high. Programming operation 27SF512/27VF512 usually programmed using external programmer. programming mode activated asserting (±5%) OE#/Vpp pin, 5V±5%, pin. device programmed
1998 Silicon Storage Technology, Inc. logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon storage Technology, Inc. 320-04 11/97 These specifications subject change without notice.
Kilobit SuperFlash SST27SF512, SST27VF512
Preliminary Specifications byte byte with desired data desired address using single pulse (CE# low) Using programming algorithm, byte programming process continues byte byte until entire chip Kbytes) been programmed. Chip Erase Operation only change data from electrical erase that changes every device "1". Unlike traditional EPROMs, which light chip erase, 27SF512/27VF512 electrical chip erase operation. This saves significant amount time (about minutes each erase operation compared with erase). entire chip erased single pulse (CE# low). order activate erase mode, (±5%) applied OE#/VPP pins, 5V±5%, pin. other address data pins "don't care". falling edge will start Chip Erase operation. Once chip been erased, bytes must verified Refer figure flow chart. 27SF512/27VF512 also reprogrammed system. This requires availability OE#/ program additional address erase. Product Identification Mode product identification mode identifies device 27SF512 27VF512 manufacturer SST. This mode accessed hardware method. activate this mode, programming equipment must force (12V±5%) address with 5V±10%. identifier bytes then sequenced from device outputs toggling address line details, Table hardware operation. TABLE PRODUCT IDENTIFICATION TABLE Byte Manufacturer's Code 0000 27SF512 Device Code 0001 27VF512 Device Code 0001
Data
T1.0
FUNCTIONAL BLOCK DIAGRAM SST27SF512/27VF512
X-Decoder
524,288 EEPROM Cell Array
Address Buffer Y-Decoder
OE#/VPP
Control Logic
Buffers
B1.0
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
OE#/VPP
Standard Pinout View
F01.0
FIGURE ASSIGNMENTS 28-PIN TSOP PACKAGES
OE#/VPP
OE#/VPP
28-Pin PDIP View
32-Lead PLCC View
F02.1
FIGURE ASSIGNMENTS 28-PIN PLASTIC DIPS 32-LEAD PLCCS TABLE DESCRIPTION Symbol Name A15-A0 Address Inputs DQ7-DQ0 Data Input/Output OE#/VPP Chip Enable Output Enable/VPP Power Supply Ground Connection
Functions provide memory addresses output data during read cycles receive input data during program cycle, outputs tri-state when high activate device when gate data output buffers during read operation high voltage (12V±5%) during chip erase programming operation provide 5-volt supply (±10%) 27SF512 3-volt supply (2.7-3.6 27VF512 Unconnected pins
T2.0
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Preliminary Specifications TABLE OPERATION MODES SELECTION Mode OE#/VPP Read Output Disable Program VPPH Standby Chip Erase VPPH Program/Erase Inhibit VPPH Product Identification
DOUT High High High High Manufacturer Code (BF) Device Code 27SF512, 27VF512)
Address VIL, VIL,
T3.0
Note:
VPPH 12V±5%, 12V±5%
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VCC+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VCC+ 1.0V Voltage Ground Potential -0.5V 14.0V Package Power Dissipation Capability 25°C) 1.0W Through Hole Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1)
Note: Outputs shorted more than second. more than output shorted time.
27SF512 OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C
CONDITIONS TEST 5V±10% 5V±10% Input Rise/Fall Time Output Load Gate Figures
27VF512 OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C
CONDITIONS TEST 2.7-3.6V 2.7-3.6V Input Rise/Fall Time Output Load Gate Figures
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Preliminary Specifications TABLE 27SF512 READ MODE OPERATING CHARACTERISTICS V±10%, 70°C (Commercial) -40°C +85°C (Industrial) Limits Symbol Parameter Units Test Conditions Read Current I/Os open, Address Input VIL/VIH 1/TRC Min, IPPR Read Current VIL, I/Os open, Address Input VIL/VIH 1/TRC Min, Max, ISB1 Standby Current VIH, (TTL input) ISB2 Standby Current CE#=OE#=VCC -0.3V (CMOS input) Max. Input Leakage Current VCC, Output Leakage Current VOUT VCC, Input Voltage Input High Voltage Vcc+0.5 Output Voltage Output High Voltage -400µA, Supervoltage Current VIL, Max.
T4.1
TABLE 27VF512 READ MODE OPERATING CHARACTERISTICS 2.7-3.6V, 70°C (Commercial) -40°C +85°C (Industrial) Limits Symbol Parameter Units Test Conditions Read Current CE#=OE#=VIL I/Os open, Address input VIL/VIH f=1/TRC Min., VCC=VCC IPPR Read Current VIL, I/Os open, Address Input VIL/VIH 1/TRC Min, Max, ISB1 Standby Current CE#=OE#=VIH, =VCC Max. (TTL input) ISB2 Standby Current CE#=OE#=VCC -0.3V. (CMOS input) Max. Input Leakage Current =GND VCC, Max. Output Leakage Current VOUT =GND VCC, Max. Input Voltage Max. Input High Voltage Vcc+0.5 Max. Output Voltage Min. Output High Voltage -100 Min. Supervoltage Current VIL, Max.
T5.1
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Preliminary Specifications TABLE 27SF512/27VF512 PROGRAM/ERASE OPERATING CHARACTERISTICS V±10%, VPPH,TA 25°C±5°C Limits Symbol Parameter Units Test Conditions Erase Program VIL, OE#/Vpp 12V±5%, Current Erase Program VIL, OE#/Vpp 12V±5%, Current Input Leakage Current VCC, Output Leakage Current VOUT VCC, Supervoltage 11.4 12.6 Supervoltage Current VIL, VPPH High Voltage 11.4 12.6
T6.1
TABLE POWER-UP TIMINGS Symbol Parameter TPU-READ Power-up Read Operation
Maximum
Units
T7.0
TABLE CAPACITANCE MHz, other pins open) Parameter Description Test Condition CI/O(1) Capacitance VI/O CIN(1) Input Capacitance
Maximum
T8.0
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention VZAP_HBM(1) Susceptibility Human Body Model VZAP_MM Susceptibility Machine Model ILTH Latch
Note:
Minimum Specification 1000 2000
Units Cycles Years Volts Volts
Test Method MIL-STD-883, Method 1033 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T9.0
This parameter measured only initial qualification after design process change that could affect this parameter.
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Preliminary Specifications CHARACTERISTICS TABLE 27SF512 READ CYCLE TIMING PARAMETERS Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change 27SF512-55 27SF512-70 Units
T10.1
TABLE 27VF512 READ CYCLE TIMING PARAMETERS Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1)
Note:
(1)This
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change
27VF512-120
27VF512-150
Units
T11.0
parameter measured only initial qualification after design process change that could affect this parameter.
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Preliminary Specifications TABLE PROGRAMMING/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TPRT OE#/VPP Pulse Rise Time Address Setup Time Address Hold Time TOES OE#/VPP Setup Time TOEH OE#/VPP Hold Time Program Pulse Width Erase Pulse Width Data Setup Time Data Hold Time OE#/VPP Recovery Time TART Rise Time during Erase TA9S Setup Time during Erase TA9H Hold Time during Erase Units
T12.0
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
ADDRESS
TOHZ
OE#/Vpp
TOLZ
DATA VALID
F03.0
TCHZ
DATA VALID
DQ7-0
HIGH-Z
TCLZ
FIGURE READ CYCLE TIMING DIAGRAM
ADDRESS (EXCEPT
DQ7-0
VPPH OE#/Vpp VPPH TART TA9H TA9S TPRT TOES TOEH
F04.0
FIGURE ERASE TIMING DIAGRAM
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
ADDRESS
ADDRESS VALID
DQ7-0
HIGH-Z
DATA VALID
VPPH OE#/Vpp TPRT TOEH TOES
F05.0
FIGURE PROGRAM TIMING DIAGRAM
INPUT
REFERENCE POINTS
OUTPUT
F06.0
test inputs driven (2.4 VTTL) logic (0.4 VTTL) logic "0". Measurement reference points inputs outputs (2.0 VTTL) (0.8 VTTL). Inputs rise fall times (10% 90%) FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
TEST LOAD EXAMPLE
TESTER
HIGH
F07.0
FIGURE TEST LOAD EXAMPLE
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Start
OE#/VPP VPPH
Erase pulse (CE# VIL)
OE#/VPP
Wait OE#/VPP Recovery Time
Device into Read mode (CE# VIL)
Compare bytes
Device Passed Device Failed
F08.0
FIGURE ERASE ALGORITHM
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Start
Erase
OE#/VPP VPPH
Address First Location
Program pulse (CE# VIL)
OE#/VPP
Increment Address
Last Address?
Wait OE#/VPP Recovery time
Device into Read mode (CE# VIL)
Compare bytes original data
Device Failed
F09.0
Device Passed
FIGURE PROGRAMMING ALGORITHM
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Preliminary Specifications PRODUCT ORDERING INFORMATION
Device SST27XF512
Speed
Suffix1
Suffix2 Package Modifier leads, leads Numeric modifier Package Type PDIP PLCC TSOP (die Unencapsulated Operating Temperature Commercial 70°C Industrial -40° 85°C Minimum Endurance 1000 cycles Read Access Speed Read Voltage Volt Read Volt Read (2.7-3.6V)
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Preliminary Specifications 27SF512 Valid combinations SST27SF512- 55-3C-KG SST27SF512- 55-3C-NH SST27SF512- 70-3C-KG SST27SF512- 70-3C-NH SST27SF512- 55-3I-KG SST27SF512- 70-3I-KG SST27SF512- 55-3I-NH SST27SF512- 70-3I-NH SST27SF512- 55-3C-PG SST27SF512- 70-3C-PG
SST27SF512- 70-3C-U1
27VF512 Valid combinations SST27VF512- 120-3C-KG SST27VF512- 120-3C-NH SST27VF512- 150-3C-KG SST27VF512- 150-3C-NH SST27VF512- 120-3I-KG SST27VF512- 150-3I-KG SST27VF512- 120-3I-NH SST27VF512- 150-3I-NH
SST27VF512- 120-3C-PG SST27VF512- 150-3C-PG
SST27VF512-150-3C-U1
Example:Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
Preliminary Specifications PACKAGING DIAGRAMS
Note: Complies with JEDEC publication MO-183 dimensions, although some dimensions more stringent. linear dimensions metric (min/max). Coplanarity: (±.05) 28pn TSOP AC.3
28-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
Note: Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .010 inches.
28pn PDIP AC.2
28-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) PACKAGE CODE:
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
32pn PLCC AC.3 Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .008 inches.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
1998 Silicon Storage Technology, Inc.
320-04 11/97
Kilobit SuperFlash SST27SF512, SST27VF512
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Revised 3-12-98
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
1998 Silicon Storage Technology, Inc.
320-04 11/97
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