SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS LVTTL CLOCK GENERATOR Fully
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ICS87974I-01
SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS LVTTL CLOCK GENERATOR
Fully integrated single ended 3.3V LVCMOS LVTTL outputs Selectable CLK1 differential CLK0, nCLK0 inputs redundant clock applications CLK1 accepts LVCMOS LVTTL input levels CLK0, nCLK0 pair accept following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Maximum output frequency: 125MHz range: 250MHz 500MHz External feedback "zero delay" clock regeneration Cycle-to-cycle jitter: 50ps (maximum) Output skew: 200ps (maximum) Bank skew: 70ps (maximum) reference zero delay: CLK1: -150ps 150ps CLK0, nCLK0: -475ps -175ps 3.3V operating supply
GENERAL DESCRIPTION
ICS87974I-01 skew, jitter 1-to-15 Differential-to-LVCMOS LVTTL Clock Generator/ HiPerClockSZero Delay Buffer member HiPerClockSfamily High Performance Clock Solutions from ICS. device fully integrated three banks whose divider ratios independently controlled, providing output frequency relationships 1:1, 2:1, 3:1, 3:2, 3:2:1. addition, external feedback connection provides wide selection output-toinput frequency ratios. CLK1 CLK0, nCLK0 pins allow redundant clocking input dynamically switching between clock sources.
Guaranteed jitter output skew characteristics make ICS87974I-01 ideal those applications demanding well defined performance repeatability.
ASSIGNMENT
VCO_SEL VDDOC VDDOC VDDOB
-40°C 70°C ambient operating temperature
CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL CLK1 CLK0 nCLK0 VDDA
VDDOB VDDOB FB_IN VDDOFB
ICS87974I-01
VDDOA VDDOA FB_SEL0 FB_SEL1 VDDOA
52-Lead LQFP 10mm 10mm 1.4mm package body package View
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BLOCK DIAGRAM
SEL_A CLK_SEL
(Internal Pulldown) (Internal Pulldown)
CLK0 (Internal Pulldown) nCLK0 (Internal Pullup)
FB_IN (Internal Pullup) PLL_SEL (Internal Pullup) VCO_SEL (Internal Pulldown) SEL_B (Internal Pulldown)
CLK1 (Internal Pulldown)
QA0:QA4
QB0:QB4
QC0:QC3
SEL_C (Internal Pulldown)
(Internal Pullup) FB_SEL1 FB_SEL0
(Internal Pulldown)
(Internal Pulldown)
CLK_EN (Internal Pullup)
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SIMPLIFIED BLOCK DIAGRAM
CLK_EN SEL_A VCO_SEL
CLK_SEL CLK1 CLK0 nCLK0 FB_IN
SEL_A
QA0:QA4
SEL_B
PLL_SEL SEL_B
QB0:QB4
SEL_C
SEL_C
QC0:QC3
FB_0 FB_1
FB_SEL(0:1) nMR/OE
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SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS LVTTL CLOCK GENERATOR
Type Power Description Power supply ground. Active Master Reset. When logic LOW, internal dividers reset causing outputs low. when logic HIGH, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Clock enable. When LOW, outputs except low. LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects between reference clock input dividers. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Clock select input. LVCMOS LVTTL interface levels.
TABLE DESCRIPTIONS
Number Name
Input
Pullup
CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL CLK1 CLK0 nCLK0 VDDA FB_SEL0, FB_SEL1 QA4, QA3, QA2, QA1, VDDOA VDDOFB FB_IN
Input Input Input Input Input Input Input Input Input Unused Power Power Input Output Power Power Output Input Output Power Output Power Input
Pullup Pulldown Pulldown Pullup Pulldown Pulldown
Pulldown Clock input. LVCMOS LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input connect. Core supply pin. Analog supply pin. Selects divide value Bank feedback output described Pulldown Table LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank clock outputs. Output supply clock output. Clock output. LVCMOS LVTTL interface levels. Feedback input phase detector generating clocks with Pullup "zero delay". Connect LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank clock outputs. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank clock outputs. Selects when HIGH. Selects when LOW. Pulldown LVCMOS LVTTL interface levels.
QB4, QB3, QB2, QB1, VDDOB QC3, QC2, QC1, VDDOC VCO_SEL
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
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Test Conditions Minimum Typical Maximum Units
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
Output Impedance Power Dissipation Capacitance VDD, VDDA, VDDOx 3.465V; NOTE (per output) NOTE VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB.
TABLE OUTPUT CONTROL FUNCTION TABLE
Inputs CLK_EN QA0:QA4 Enable QB0:QB4 Enable Outputs QC0:QC3 Enable Enable Enable
TABLE OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL Operating Mode Bypass
TABLE INPUT FUNCTION TABLE
Inputs CLK_SEL Input CLK1 CLK0, nCLK0
TABLE SELECT FUNCTION TABLE
SEL_A SEL_B SEL_C
TABLE SELECT FUNCTION TABLE
Inputs FB_SEL1 FB_SEL0 Outputs
TABLE SELECT FUNCTION TABLE
Inputs VCO_SEL fVCO VCO/2 VCO/4
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4.6V -0.5V -0.5V VDDO 0.5V 73.2°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 70°C
Symbol VDDA VDDOx IDDO IDDA
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage; NOTE Power Supply Current Output Supply Current Analog Supply Current
Test Conditions
Minimum 3.135 3.135 3.135
Typical
Maximum 3.465 3.465 3.465
Units
NOTE VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB.
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 70°C
Symbol
Parameter Input High Voltage Input Voltage FB_SEL0, FB_SEL1, CLK1, SEL_A:SEL_C, Input High Current CLK_SEL, VCO_SEL FB_IN, nMR, PLL_SEL, CLK_EN FB_SEL0, FB_SEL1, CLK1, SEL_A:SEL_C, Input Current CLK_SEL, VCO_SEL FB_IN, nMR, PLL_SEL, CLK_EN Output High Voltage; NOTE Output Voltage; NOTE
Test Conditions
Minimum -0.3
Typical
Maximum
Units
3.465V 3.465V 3.465V 3.465V -150
NOTE Outputs terminated with VDDOx/2.
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TABLE DIFFERENTIAL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 70°C
Symbol Parameter Input High Current Input Current CLK0 nCLK0 CLK0 nCLK0 Test Conditions 3.465V 3.465V 3.465V 3.465V -150 0.15 -0.85 Minimum Typical Maximum Units
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE VCMR NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage CLK0, nCLK0 0.3V.
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 70°C
Symbol fMAX fVCO tsk(b)
Parameter Output Frequency Lock Range; NOTE Reference Zero Delay; NOTE Bank Skew; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter NOTE Lock Time Output Rise/Fall Time Output Duty Cycle Output Enable Time CLK1 CLK0, nCLK0
Test Conditions
Minimum
Typical
Maximum 62.5 41.67
Units
PLL_SEL -150 -475 -325
-175
tsk(o) tjit(cc)
500MHz,
Output Disable Time tDIS parameters measured fMAX unless noted otherwise. NOTE Measured from VDD/2 point input theVDDOx/2 output. NOTE Defined time difference between input reference clock averaged feedback input signal when locked input reference frequency stable. NOTE Defined skew within bank with equal load conditions. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDOx/2. NOTE This parameter defined accordance with JEDEC Standard NOTE Reference frequency 50MHz used with banks DIV4.
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PARAMETER MEASUREMENT INFORMATION
1.65V±5% VDD, VDDA, VDDO
SCOPE
nCLK0
LVCMOS
Cross Points
CLK0
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
DDOX
DDOX
DDOX
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
QX0:QXx
VDDOX
QX0:QXx
sk(b)
VDDOX
BANK SKEW (where denotes outputs same bank)
DDOX
QAx, QBx, QCx,
Pulse Width
PERIOD
PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87974AYI-01
QAx, QBx, QCx,
DDOX
tcycle
DDOX
sk(o)
OUTPUT SKEW
CLK1 nCLK0 CLK0
QAx, QBx, QCx,
VDDO
STATIC PHASE OFFSET
Clock Outputs
OUTPUT RIS/FALL TIME
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SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS LVTTL CLOCK GENERATOR APPLICATION INFORMATION
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VDD/2 generated bias resistors This bias circuit should located close possible input pin. ratio
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Single Ended Clock Input V_REF nCLK 0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87974I-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDOx should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA pin.
3.3V .01µF VDDA .01µF 10µF
FIGURE POWER SUPPLY FILTERING
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here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested
3.3V 3.3V
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V
LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
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example ICS87974I-01 LVCMOS clock generator. this example, input driven LVCMOS driver.
SCHEMATIC EXAMPLE
This application note provides general design guide using ICS87974I-01 LVCMOS buffer. Figure shows schematic
VDD=3.3V
VDDO
Space (i.e. intstalled)
VCO_SEL VDDOC VDDOC VDDOB
Driv er_LVCMOS_no_Ro
0.01u
0.01u
Logic Input Examples
Logic Input
Logic Input
Install
87974I-01
FB_SEL0 VDDOA FB_SEL1 VDDOA VDDOA
CLK_EN SELB SELC PLL_SEL SELA CLK_SEL CLK1 CLK0 nCLK0 VDDA
VDDOB VDDOB FB_IN VDDOFB
Logic Input pins
Install
Logic Input pins
(U1-17)
VDDO
(U1-22)
(U1-26)
(U1-28)
(U1-33)
(U1-37)
(U1-41)
(U1-45)
(U1-49)
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
FIGURE EXAMPLE ICS87974I-01 LVCMOS/LVTTL CLOCK OUTPUT BUFFER SCHEMATIC
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SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87974I-01 4225
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LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.22 0.09 MINIMUM NOMINAL -1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC -0.75 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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Marking ICS87974AYI-01 ICS87974AYI-01 Package Lead LQFP Lead LQFP Tape Reel Count tray Temperature -40°C 70°C -40°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87974AYI-01 ICS87974AYI-01T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87974AYI-01
REV. FEBRUARY 2004
ICS87974I-01
SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET Description Change Added schematic layout. Swichted labels FB_SEL0 FB_SEL1 Block Diagram Simplified Block Diagram. Date 11/13/03 2/9/04
Table
Page
87974AYI-01
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