VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR differenti
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ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
differential LVPECL outputs Selectable crystal oscillator interface TEST_CLK inputs TEST_CLK accepts following input levels: LVCMOS, LVTTL Output frequency: 400MHz (maximum) Crystal input frequency range: 10MHz 25MHz range: 200MHz 800MHz Output skew: 250ps (maximum) Cycle-to-cyle jitter: ±50ps (typical) LVPECL mode operating voltage supply range: 3.135V 3.465V, mode operating voltage supply range: -3.465V -3.135V 70°C ambient operating temperature Industrial temperature available upon request compatible with MPC990
GENERAL DESCRIPTION
ICS873990 voltage, skew, 3.3V LVPECL/ECL Clock Generator member HiPerClockSof HiPerClockSfamily High Performance Clock Solutions from ICS. ICS873990 selectable clock inputs. XTAL1 XTAL2 used interface crystal TEST_CLK accept LVCMOS LVTTL input. This device fully integrated along with frequency configurable outputs. external feedback input output regenerates clocks with "zero delay".
four independent banks outputs each have their output dividers, which allow device generate multitude different bank frequency ratios output-to-input frequency ratios. output frequency range 25MHz 400MHz input frequency range 6.25MHz 125MHz. PLL_SEL input used bypass test system debug purposes. bypass mode, input clock routed around into internal output dividers. ICS873990 also SYNC output which used system synchronization purposes. monitors Bank Bank outputs coincident rising edges signals pulse timing diagrams this data sheet. This feature used primarily applications where Bank Bank running different frequencies, particularly useful when they running non-integer multiples each other. Example Applications: Line Card Multiplier: Multiply 19.44MHz from back-plane 77.76MHz line card ASIC Serdes. Zero Delay Buffer: thirteen 100MHz copies from reference clock multiple processing units embedded system.
ASSIGNMENT
FSEL0 FSEL1 FSEL2
nQB3 VCCO nQA0 nQA1 nQA2 nQA3 SYNC_SEL VCO_SEL
FSEL3
nQC2
nQB2
nQB1
nQB0
VCCO
nQC1 nQC0 VCCO nQD1 nQD0 VCCO nQFB VCCA
ICS873990
PLL_EN
REF_SEL
FSEL_FB2
FSEL_FB1
FSEL_FB0 XTAL_OUT TEST_CLK EXT_FB nEXT_FB XTAL_IN
52-Lead LQFP 10mm 10mm 1.4mm package body package View
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REV. 2004
ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
BLOCK DIAGRAM
VCO_SEL Pulldown PLL_EN Pulldown REF_SEL Pulldown TEST_CLK Pulldown XTAL_IN XTAL_OUT nQA0
XTAL
nQA1
PHASE DETECTOR
nQA2 nQA3 nQB0 nQB1
EXT_FB nEXT_FB Pulldown
FREQUENCY GENERATOR
FSEL_0:3 Pulldown
nQB2 nQB3
SYNC
FSEL_FB0:2 Pulldown
nQC0 nQC1 nQC2 nQD0 nQD1 nQFB
SYNC_SEL Pulldown
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ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Type Power Input Description
TABLE DESCRIPTIONS
Number Name Negative supply pin. Active High Master Reset. When logic HIGH, internal dividers reset causing true outputs (Qx) inver outputs Pulldown (nQx) high. When logic LOW, internal dividers outputs enabled. LVCMOS/LVTTL interface levels. enable pin. When logic LOW, enabled. When logic HIGH, Pulldown bypass mode. LVCMOS/LVTTL interface levels. Selects between different reference inputs reference Pulldown source. When logic LOW, selects ystal inputs. When logic HIGH, selects TEST_CLK. LVCMOS/LVTTL interface levels. Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels. Pulldown LVCMOS/LVTTL test clock input. ystal oscillator interface. XTAL_IN input, XTAL_OUT output. Core supply pin. Pulldown External feedback input. Pullup/ External feedback input. default when left floating. Pulldown Analog supply pin. Differential feedback output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Sync output select pin. When LOW, SYNC output follows Pulldown timing diagram (page When HIGH, output follows output. Pulldown Selects range. LVCMOS/LVTTL interface levels.
PLL_EN REF_SEL FSEL_FB2 FSEL_FB1 FSEL_FB0 TEST_CLK XTAL_IN, XTAL_OUT EXT_FB nEXT_FB VCCA nQFB, VCCO nQD0, nQD1, nQC0, nQC1, FSEL3 FSEL2 FSEL1 FSEL0 nQC2, nQB0, nQB1, nQB2, nQB3, nQA0, nQA1, nQA2, nQA3, SYNC_SEL VCO_SEL
Input Input
Input Input Input Power Input Input Power Output Power Output Output Output Output Input Output Output Output Output Output Output Output Output Output Input Input
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
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ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Test Conditions Minimum Typical Maximum Units
TABLE CHARACTERISTICS
Symbol RPULLDOWN RPULLup Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor
TABLE SELECT FUNCTION TABLE
Inputs FSEL3 FSEL2 FSEL1 FSEL0 Outputs
TABLE FEEDBACK CONTROL FUNCTION TABLE
Inputs FSEL_FB2 FSEL_FB1 FSEL_FB0 Outputs
TABLE INPUT CONTROL FUNCTION TABLE
Control Input PLL_EN VCO_SEL REF_SEL SYNC_SEL Logic Enables fVCO Selects XTAL -Selects outputs Logic Bypasses fVCO/2 Selects TEST_CLK Resets outputs Match Outputs
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ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Mode
SYNC (QD)
Mode
SYNC (QD)
Mode
SYNC (QD)
Mode
SYNC (QD)
Mode
SYNC (QD)
FIGURE TIMING DIAGRAMS
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ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
4.6V -0.5V 50mA 100mA 42.3°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maxi-mum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V 70°C
Symbol VCCA VCCO ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA VCCO 3.3V 70°C
Symbol Parameter Input High Voltage REF_SEL, SYNC_SEL, FSEL_FB0:FB2, PLL_EN, FSEL0:3, VCO_SEL TEST_CLK REF_SEL, SYNC_SEL, FSEL_FB0:FB2, PLL_EN, FSEL0:3, VCO_SEL TEST_CLK 3.465V 3.465V Test Conditions Minimum -0.3 -0.3 Typical Maximum Units
Input Voltage
Input High Current Input Current
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V 70°C
Symbol VSWING Parameter Output High Voltage, NOTE Output Voltage, NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units
NOTE Outputs terminated with VCCO
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance
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Test Conditions
Minimum
Typical Maximum
Units
REV. 2004
Fundamental
ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Test Conditions TEST_CLK Feedback Feedback 66.66 16.66 12.5 33.33 12.5 8.33 6.25 Minimum Typical Maximum 133.33 33.33 66.66 16.66 12.5 Units
TABLE INPUT REFERENCE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input Rise/Fall Time
Reference Frequency VCO_SEL
Feedback Feedback Feedback
fREF Reference Frequency VCO_SEL
Feedback Feedback Feedback Feedback Feedback Feedback
fREFDC
Reference Input Duty Cycle
NOTE: These parameters guaranteed design, tested production.
TABLE CHARACTERISTICS, VCCA VCCO 3.3V 70°C
Symbol fMAX Parameter Output Frequency Static Phase Offset; TEST_CLK NOTE Output Skew; NOTE Multiple Frequency Skew; NOTE Cycle-to-Cycle Jitter; NOTE Lock Range; NOTE Lock Time Output Rise/Fall Time VCO_SEL VCO_SEL Test Conditions Minimum Typical Maximum -240 Units
tsk(o) sk(w) tjit(cc)
LOCK
Output Duty Cycle parameters measured fMAX unless noted otherwise. NOTE Defined time difference between input reference clock average feedback input signal when locked input reference frequency stable. NOTE 2:Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard NOTE When VCO_SEL will unstable with feedback configurations some When VCO_SEL will unstable with feedback configuration NOTE Static phase offset specified input frequency 50MHz with feedback NOTE Defined skew across banks outputs switching same direction operating different frequencies with same supply voltages equal load conditions. Measured VCCO/2.
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ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCCA, VCCO
SCOPE
LVPECL
sk(o)
-1.3V -0.165V
OUTPUT LOAD TEST CIRCUIT
OUTPUT SKEW
nQFB, nQAx:nQDx QFB, QAx:QDx
TEST_CLK nQFB, nQAx:nQDx QFB, QAx:QDx
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
STATIC PHASE OFFSET
CYCLE-TO-CYCLE JITTER
nQFB, nQAx:nQDx QFB, QAx:QDx
nQxx nQyy
tsk()
Pulse Width
PERIOD
PERIOD
MULTIPLE FREQUENCY SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Clock Outputs
OUTPUT RISE/FALL TIME
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tcycle
REV. 2004
ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS873990 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
3.3V .01µF .01µF 10µF
FIGURE POWER SUPPLY FILTERING
TERMINATION 3.3V LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
allel resonant crystal were chosen minimize error. optimum values slightly adjusted different board layouts.
CRYSTAL INPUT INTERFACE
ICS873990 been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF par-
XTAL_OUT 18pF Parallel Crystal XTAL_IN
Figure CRYSTAL INPUt INTERFACE
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REV. 2004
ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS873990. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS873990 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 165mA 571.7mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 420mW
Total Power_MAX (3.465V, with outputs switching) 571.7mW 420mW 991.7mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 47.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.992W 47.1°C/W 116.7°C. This below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
52-PIN LQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
0.9V
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 0.9V)/50] 0.9V 19.8mW ))/R
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
873990AY
REV. 2004
ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS873990 5788
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ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.22 0.09 MINIMUM NOMINAL -1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC -0.75 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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REV. 2004
ICS873990
VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Marking ICS873990AY ICS873990AY Package Lead LQFP Lead LQFP Tape Reel Count tray Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS873990AY ICS873990AYT
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 873990AY
REV. 2004
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