Flash Programmable System Devices with 8032 Microcontroller Core Kbit
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uPSD3234A, uPSD3234BV uPSD3233B, uPSD3233BV
Flash Programmable System Devices with 8032 Microcontroller Core Kbit SRAM
FAST 8-BIT 8032 40MHz 5.0V, 24MHz 3.3V Core, 12-clocks instruction DUAL FLASH MEMORIES WITH MEMORY MANAGEMENT Place either memory into 8032 program address space data address space READ-while-WRITE operation InApplication Programming EEPROM emulation Single voltage program erase 100K minimum erase cycles, 15-year retention CLOCK, RESET, SUPPLY MANAGEMENT SRAM Battery Backup capable Normal, Idle, Power Down Modes Power-on Voltage reset supervisor Programmable Watchdog Timer PROGRAMMABLE LOGIC, GENERAL PURPOSE macrocells Implements state machines, glue-logic, forth COMMUNICATION INTERFACES v1.1, low-speed 1.5Mbps, endpoints Master/Slave controller UARTs with independent baud rate ports with pins 8032 Address/Data available TQFP80 package outputs, 8-bit resolution JTAG IN-SYSTEM PROGRAMMING Program entire device little seconds
Figure Packages
TQFP52 52-lead, Thin, Quad Flat
TQFP80 80-lead, Thin, Qual Flat
CONVERTER Four channels, 8-bit resolution, 10µs TIMERS INTERRUPTS Three 8032 standard 16-bit timers Interrupt sources with external interrupt pins Single Supply Voltage 5.5V 3.6V
November 2004
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Table Device Summary
Part Number uPSD3233B-40T6 uPSD3233BV-24T6 uPSD3233B-40U6 uPSD3233BV-24U6 uPSD3234A-40T6 uPSD3234A-40U6 uPSD3234BV-24U6 SRAM Clock Flash Flash GPIO (bytes) (MHz) (bytes) (bytes) 128K 128K 128K 128K 256K 256K 256K 8032 4.5-5.5 3.0-3.6 4.5-5.5 3.0-3.6 4.5-5.5 4.5-5.5 3.0-3.6 Pkg. Temp.
TQFP52 -40°C 85°C TQFP52 -40°C 85°C TQFP80 -40°C 85°C TQFP80 -40°C 85°C TQFP52 -40°C 85°C TQFP80 -40°C 85°C TQFP80 -40°C 85°C
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TABLE CONTENTS
FEATURES SUMMARY SUMMARY DESCRIPTION 52-PIN PACKAGE PORT ARCHITECTURE OVERVIEW Memory Organization Registers Program Memory Data memory XRAM-DDC XRAM-PSD Addressing Modes Arithmetic Instructions Logical Instructions Data Transfers Boolean Instructions. Relative Offset Jump Instructions Machine Cycles uPSD3200 HARDWARE DESCRIPTION MODULE DISCRIPTION Special Function Registers INTERRUPT SYSTEM. External Int0 Timer Interrupts Timer Interrupt Interrupt External Int1 Interrupt Interrupt USART Interrupt Interrupt Priority Structure Interrupts Enable Structure Interrupts Handled
POWER-SAVING MODE. Idle Mode
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Power-Down Mode Power Control Register. Idle Mode Power-Down Mode
PORTS (MCU MODULE). PORT Type Description OSCILLATOR SUPERVISORY External Reset Voltage Reset Watchdog Timer Overflow Reset
WATCHDOG TIMER TIMER/COUNTERS (TIMER TIMER TIMER Timer Timer Timer STANDARD SERIAL INTERFACE (UART) Multiprocessor Communications. Serial Port Control Register ANALOG-TO-DIGITAL CONVERTOR (ADC) Interrupt PULSE WIDTH MODULATION (PWM). 4-channel Unit (PWM 0-3) Programmable Period 8-bit Channel Operation INTERFACE Serial Status Register (SxSTA: S1STA, S2STA) Data Shift Register (SxDAT: S1DAT, S2DAT) Address Register (SxADR: S1ADR, S2ADR). INTERFACE Special Function Register Interface Host Type Detection DDC1 Protocol DDC2B Protocol. HARDWARE
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related registers Transceiver Receiver Characteristics. External Pull-Up Resistor. MODULE Functional Overview In-System Programming (ISP) DEVELOPMENT SYSTEM MODULE REGISTER DESCRIPTION ADDRESS OFFSET MODULE DETAILED OPERATION MEMORY BLOCKS. Primary Flash Memory Secondary Flash memory Description Memory Block Select Signals. Instructions Power-down Instruction Power-up Mode READ Programming Flash Memory Erasing Flash Memory Specific Features SRAM Sector Select SRAM Select Page Register. PLDs Turbo Module Decode (DPLD) Complex (CPLD) Output Macrocell (OMC) Product Term Allocator. Input Macrocells (IMC) PORTS (PSD MODULE) General Port Architecture Port Operating Modes Mode Mode Address Mode. Peripheral Mode JTAG In-System Programming (ISP) Port Configuration Registers (PCR) Port Data Registers
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Ports Functionality Structure Port Functionality Structure Port Functionality Structure External Chip Select POWER MANAGEMENT Power Management. Chip Select Input (CSI, PD2) Input Clock Input Control Signals RESET TIMING DEVICE STATUS RESET Warm RESET Pin, Register Status RESET Reset Flash Memory Erase Program Cycles. PROGRAMMING IN-CIRCUIT USING JTAG SERIAL INTERFACE Standard JTAG Signals. JTAG Extensions Security Flash memory Protection. INITIAL DELIVERY STATE. AC/DC PARAMETERS MAXIMUM RATING. CHARACTERISTICS Functional (Electromagnetic Susceptibility) Designing Hardened Software Avoid Noise Problems Absolute Maximum Ratings (Electrical Sensitivity) PARAMETERS. PACKAGE MECHANICAL INFORMATION PART NUMBERING REVISION HISTORY.
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SUMMARY DESCRIPTION
uPSD323x Series combines fast 8051based microcontroller with flexible memory structure, programmable logic, rich peripheral including USB, form ideal embedded controller. core industry-standard 8032 operating 40MHz. JTAG serial interface used In-System Programming (ISP) little seconds, perfect manufacturing development. low-speed interface Control endpoint Interrupt endpoints suitable class drivers. 8032 core coupled Programmable System Device (PSD) architecture optimize 8032 memory structure, offering independent banks Flash memory that placed virtually address within 8032 program data address space, easily paged beyond bytes using on-chip programmable decode logic. Figure Block Diagram
uPSD323x
16-bit Timer/ Counters External Interrupts 8032 Core
Dual Flash memory banks provide robust solution remote product updates field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating need external EEPROM chips. General purpose programmable logic (PLD) included build endless variety glue-logic, saving external logic devices. configured using software development tool, PSDsoft Express, available from www.st.com/psm, charge. uPSD323x also includes supervisor functions such programmable watchdog timer lowvoltage reset.
Flash Memory: 128K 256K Bytes Programmable Decode Page Logic
P3.0:7
Flash Memory: Bytes SRAM: Bytes
UART0 GPIO, Port (80-pin only)
PA0:7 PB0:7 PD1:2
SYSTEM
GPIO, Port
P1.0:7
GPIO, Port
General Purpose Programmable Logic, Macrocells
GPIO, Port GPIO, Port GPIO, Port
8-bit
PC0:7
UART1 JTAG 8032 Address/Data/Control (80-pin device only) Supervisor: Watchdog Low-Voltage Reset VCC, VDD, GND, Reset, Crystal
8-bit
P4.0:7 USB+, USB-
GPIO, Port
v1.1
Dedicated Pins
AI10429
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Figure TQFP52 Connections
P1.7/ADC3 P1.6/ADC2 RESET_
VREF
PD1/CLKIN JTAG JTAG USB-(1) PC4/TERR_ USB+ PC3/TSTAT PC2/VSTBY JTAG JTAG
P1.5/ADC1 P1.4/ADC0 P1.3/TXD1 P1.2/RXD1 P1.1/T2X P1.0/T2 XTAL2 XTAL1 P3.7/SCL1 P3.6/SDA1 P3.5/T1 P3.4/T0
P4.7/PWM4
P4.6/PWM3
P4.5/PWM2
P4.4/PWM1
P4.3/PWM0
P4.2/DDC VSYNC
P4.1/DDC
P4.0/DDC
P3.0/RXD
P3.1/TXD
P3.2/EXINT0
P3.3/EXINT1
AI07423b
Note: Pull-up resistor required devices, 7.5k devices) 52-pin devices, with without function.
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Figure TQFP80 Connections
P3.2/EXINT0 P3.0/RXD0 P1.7/ADC3 P1.6/ADC2 P3.1/TXD0 RESET_
PSEN_
VREF
NC(2)
P3.3 /EXINT1 PD1/CLKIN JTAG/TDO JTAG/TDI USB-(1) PC4/TERR_ USB+ NC(2) PC3/TSTAT PC2/VSTBY JTAG NC(2) P4.7/PWM4 P4.6/PWM3 JTAG
P1.5/ADC1 P1.4/ADC0 P1.3/TXD1 P1.2/RXD1 P1.1/TX2 P1.0/T2 XTAL2 XTAL1 P3.7/SCL1 P3.6/SDA1 P3.5/T1
P4.5/PWM2
P4.4/PWM1
P4.3/PWM0
P4.2/DDC VSYNC
P4.1/DDC
P4.0/DDC
P3.4/T0
AI07424b
Note: Pull-up resistor required devices, 7.5k devices) 82-pin devices, with without function. Connected
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Table 80-Pin Package Description
Port Signal Name P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RxD1 TxD1 ADC0 ADC1 ADC2 ADC3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 RxD0 TxD0 EXINT0 EXINT1 SDA1 SCL1 VSYNC PWM0 Function In/Out Basic External Multiplexed Address/Data A1/D1 Multiplexed Address/Data A0/D0 Multiplexed Address/Data A2/D2 Multiplexed Address/Data A3/D3 Multiplexed Address/Data A4/D4 Multiplexed Address/Data A5/D5 Multiplexed Address/Data A6/D6 Multiplexed Address/Data A7/D7 General port General port General port General port General port General port General port General port External Bus, Address External Bus, Address External Bus, Address External Bus, Address General port General port General port General port General port General port General port General port General port General port General port General port 8-bit Pulse Width Modulation output UART Receive UART Transmit Interrupt input Timer gate control Interrupt input Timer gate control Counter input Counter input serial data clock Timer Count input Timer Trigger input UART Receive UART Transmit Channel input Channel input Channel input Channel input Alternate
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Signal Name PWM1 PWM2 PWM3 PWM4 USB- VREF PSEN_ RESET_ XTAL1 XTAL2 Function In/Out Basic General port General port General port General port Pull-up resistor required devices, 7.5k devices) Reference Voltage input READ signal, external WRITE signal, external PSEN signal, external Address Latch signal, external Active RESET input Oscillator input system clock Oscillator output system clock General port General port General port General port General port General port General port General port General port General port General port General port General port General port General port General port Macro-cell outputs inputs Latched Address (A0A7) Macro-cell outputs inputs Latched Address (A0A7) Peripheral Mode Alternate 8-bit Pulse Width Modulation output 8-bit Pulse Width Modulation output 8-bit Pulse Width Modulation output Programmable 8-bit Pulse Width modulation output
Port
P4.4 P4.5 P4.6 P4.7
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Signal Name JTAG JTAG VSTBY TSTAT TERR_ JTAG JTAG USB+ CLKIN Function In/Out Basic JTAG JTAG General port General port General port JTAG JTAG General port General port General port Clock input Chip select Module Macro-cell outputs inputs SRAM stand voltage input (VSTBY) SRAM battery-on indicator (PC4) JTAG pins dedicated pins Alternate
Port
52-PIN PACKAGE PORT
52-pin package members uPSD323X Devices have same port pins those 80-pin package except: Port (P0.0-P0.7, external address/data AD0-AD7) Port (P2.0-P2.3, external address A8A11)
Port (PA0-PA7) Port (PD2) control signal (RD,WR,PSEN,ALE) requires pull-up resistor devices, 7.5k devices) devices, with without function.
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ARCHITECTURE OVERVIEW
Memory Organization uPSD323X Devices's standard 8032 Core separate 64KB address spaces Program memory Data Memory. Program memory where 8032 executes instructions from. Data memory used hold data variables. Flash memory mapped either program data space. Flash memory consists flash memory blocks: main Flash 2Mbit) Secondary Flash (256Kbit). Except during flash memory programming update, Flash memory only read, written Page Register used access memory beyond bytes address space. Refer Module details mapping Flash memory. Figure Memory Address Space
MAIN FLASH EXT.
8032 core types data memory (internal external) that read written. internal SRAM consists bytes, includes stack area. (Special Function Registers) occupies upper bytes internal SRAM, registers accessed Direct addressing only. There separate blocks external SRAM inside uPSD323X Devices: bytes block assigned data storage. Another bytes resides Module that mapped address space defined user.
INT. SECONDARY FLASH 128KB 32KB 256KB Indirect Direct Addressing Indirect Addressing
FFFF Direct Addressing
EXT. (DDC)
256B
FF00
Flash Memory Space
Internal Space (256 Bytes)
External Space (MOVX)
AI06635
Registers 8032 several registers; these Program Counter (PC), Accumulator (A), Register (B), Stack Pointer (SP), Program Status Word (PSW), General purpose registers R7), DPTR (Data Pointer register).
Figure 8032 Registers
R0-R7 DPTR(DPH) DPTR(DPL) Accumulator Register Stack Pointer Program Counter Program Status Word General Purpose Register (Bank0-3) Data Pointer Register
AI06636
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Accumulator. Accumulator 8-bit general purpose register, used data operation such transfer, temporary saving, conditional tests. Accumulator used 16-bit register with Register shown below. Figure Configuration 16-bit Registers
8-bit Registers used "BA" 16-bit Registers
AI06637
Register. Register 8-bit general purpose register, used arithmetic operation such multiply, division with Accumulator Stack Pointer. Stack Pointer Register bits wide. incremented before data stored during PUSH CALL executions. While stack reside anywhere on-chip RAM, Stack Pointer initialized after reset. This causes stack begin location 08h. Figure Stack Pointer
Stack Area (30h-FFh) Hardware Fixed 00h-FFh
(Stack Pointer) could 00h-FFh
AI06638
Program Counter. Program Counter 16bit wide which consists 8-bit registers, PCL. This counter indicates address next instruction executed. RESET state, program counter reset routine address (PCH:00h, PCL:00h). Program Status Word. Program Status Word (PSW) contains several bits that reflect current state select Internal (00h 1Fh: Bank0 Bank3). described Figure page contains Carry flag, Auxiliary carry flag, Half Carry (for operation), general purpose flag, Register bank select flags, Overflow flag, Parity flag. [Carry Flag, CY]. This flag stores carry borrow from after arithmetic operation also changed Shift Instruction Rotate Instruction. [Auxiliary Carry Flag, AC]. After operation, this when there carry from there borrow from ALU. [Register Bank Select Flags, RS0, RS1]. This flags select four bank(00~07H:bank0, 08~0Fh:bank1, 10~17h:bank2, 17~1Fh:bank3) Internal RAM. [Overflow Flag, OV]. This flag when overflow occurs result arithmetic operation involving signs. overflow occurs when result addition subtraction exceeds +127 (7Fh) -128 (80h). CLRV instruction clears overflow flag. There instruction. When instruction executed, memory copied this flag. [Parity Flag, This flag reflect number Accumulator's number Accumulator's odd, P=0. otherwise P=1. adding Accumulator's always even. R0~R7. General purpose 8-bit registers that locked lower portion internal data area. Data Pointer Register. Data Pointer Register 16-bit wide which consists two-8bit registers, DPL. This register used data pointer data transmission with external data memory Module.
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Figure (Program Status Word) Register
Carry Flag Auxillary Carry Flag General Purpose Flag Register Bank Select Flags select Bank0-3)
Reset Value Parity Flag assigned Overflow Flag
AI06639
Program Memory program memory consists Flash memory: KByte KByte) Main Flash KByte Secondary Flash. Flash memory mapped address space defined user PSDsoft Tool. also mapped Data memory space during Flash memory update programming. After reset, begins execution from location 0000h. shown Figure each interrupt assigned fixed location Program Memory. interrupt causes jump that location, where commences execution service routine. External Interrupt example, assigned location 0003h. External Interrupt going used, service routine must begin location 0003h. interrupt going used, service location available general purpose Pro-gram Memory. interrupt service locations spaced 8byte intervals: 0003h External Interrupt 000Bh Timer 0013h External Interrupt 001Bh Timer forth. interrupt service routine short enough often case control applications), reside entirely within that 8-byte interval. Longer service routines jump instruction skip over subsequent interrupt locations, other interrupts use. Data memory internal data memory divided into four physically separated blocks: bytes internal RAM, bytes Special Function Registers (SFRs) areas, bytes external (XRAM-DDC) bytes (XRAM-PSD) Module. Four register banks, each registers wide, occupy locations through lower area. Only these banks enabled time. next bytes, locations through contain directly addressable locations. stack depth only limited available internal space bytes.
Figure Interrupt Location Program Memory
Interrupt Location
008Bh 0013h Bytes 000Bh 0003h
Reset
0000h
AI06640
XRAM-DDC bytes XRAM-DDC used support interface also available system usage indirect addressing through address pointer DDCADR data buffer RAMBUF. address pointer (DDCADR) equipped with post increment capability facilitate transfer data bulk (for details refer Interface part). However, also possible address through MOVX command normally used internal extension 80C51 derivatives. XRAM-DDC FF00 FFFF directly addressable external data memory locations FF00 FFFF MOVX-DPTR instruction MOVX-Ri instruction. When XRAM-DDC disabled, address space FF00 FFFF assigned other resources. XRAM-PSD bytes XRAM-PSD resides Module mapped address space through DPLD (Decoding PLD) defined user PSDsoft Development tool. XRAMPSD battery backup feature that allow data retained event power lost. battery connected Port pin. This must configured PSDSoft battery back-up.
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SFRs only addressed directly address range from FFh. Table 15., page gives overview Special Function Registers. Sixteen address SFRs space both-byte bit-addressable. bitaddressable SFRs those whose address ends addresses this area FFh. Table Address
Byte Address Hexadecimal) Register Bank Register Bank Register Bank Register Bank
AI06642
Addressing Modes addressing modes uPSD323X Devices instruction follows Direct addressing Indirect addressing Register addressing Register-specific addressing Immediate constants addressing Indexed addressing Direct addressing. direct addressing operand specified 8-bit address field instruction. Only internal Data SFRs (80~FFH RAM) directly addressed. Example: RAM[3E] Figure Direct Addressing
Program Memory
Byte Address Decimal) Address (Hex)
AI06641
Indirect addressing. indirect addressing instruction specifies register which contains address operand. Both internal external indirectly addressed. address register 8-bit addresses selected register bank, Stack Pointer. address register 16-bit addresses only 16-bit "data pointer" register, DPTR. Example: @R1, ;[R1] <-40H Figure Indirect Addressing
Program Memory
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Register addressing. register banks, containing registers through accessed certain instructions which carry 3-bit register specification within opcode instruction. Instructions that access registers this code efficient, since this mode eliminates address byte. When instruction executed, four banks selected execution time bank select bits PSW. Example: PSW, #0001000B select Bank0 #30H Register-specific addressing. Some instructions specific certain register. example, some instructions always operate Accumulator, Data Pointer, etc., address byte needed point opcode itself does that. Immediate constants addressing. value constant follow opcode Program memory. Example: #10H. Indexed addressing. Only Program memory accessed with indexed addressing, only read. This addressing mode intended reading look-up tables Program memory. 16-bit base register (either DPTR points base table, Accumulator with table entry number. address table entry Program memory formed adding Accumulator data base pointer. Example: movc @A+DPTR Figure Indexed Addressing
DPTR 1E73h Program Memory
Arithmetic Instructions arithmetic instructions listed Table page table indicates addressing modes that used with each instruction access <byte> operand. example, <byte> instruction written (direct addressing) (indirect addressing) (register addressing) #127 (immediate constant) Note: byte internal Data Memory space incremented without going through Accumulator. instructions operates 16-bit Data Pointer. Data Pointer used generate 16-bit addresses external memory, being able increment 16-bit operations useful feature. instruction multiplies Accumulator data register puts 16-bit product into concatenated Accumulator registers. instruction divides Accumulator data register leaves 8-bit quotient Accumulator, 8-bit remainder register. shift operations, dividing number shifts bits right. Using perform division completes shift leaves register holding bits that were shifted out. instruction arithmetic operations. arithmetic, ADDC instructions should always followed operation, ensure that result also BCD. Note: will convert binary number BCD. operation produces meaningful result only second step addition bytes.
AI06643
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Table Arithmetic Instructions
Addressing Modes Mnemonic A,<byte> ADDC A,<byte> SUBB A,<byte> <byte> DPTR <byte> Operation Dir. <byte> <byte> <byte> A=A+1 <byte> <byte> DPTR DPTR A=A-1 <byte> <byte> Int[ Mod[ Decimal Adjust Ind. Reg.
Accumulator only
Data Pointer only Accumulator only
Accumulator only Accumulator only Accumulator only
Logical Instructions Table page shows list uPSD323X Devices logical instructions. instructions that perform Boolean operations (AND, Exclusive NOT) bytes perform operation bitby-bit basis. That Accumulator contains 00110101B byte contains 01010011B, then: <byte> will leave Accumulator holding 00010001B. addressing modes that used access <byte> operand listed Table page <byte> instruction take forms: A,7FH(direct addressing) (indirect addressing) A,R6 (register addressing) A,#53H (immediate constant) Note: Boolean operations performed byte internal Data Memory space without going through Accumulator. <byte>, #data instruction, example, offers quick easy invert port bits, #0FFH.
operation response interrupt, using Accumulator saves time effort push onto stack service routine. Rotate instructions etc.) shift Accumulator left right. left rotation, rolls into position. right rotation, rolls into position. SWAP instruction interchanges high nibbles within Accumulator. This useful operation manipulations. example, Accumulator contains binary number which known less than 100, quickly converted following code: MOVE B,#10 SWAP Dividing number leaves tens digit nibble Accumulator, ones digit register. SWAP instructions move tens digit high nibble Accumulator, ones digit nibble.
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Table Logical Instructions
Addressing Modes Mnemonic A,<byte> <byte>,A <byte>,#data A,<byte> <byte>,A <byte>,#data A,<byte> <byte>,A <byte>,#data SWAP Operation Dir. .AND. <byte> <byte> .AND. <byte> .AND. #data .OR. <byte> <byte> .OR. <byte> .OR. #data .XOR. <byte> <byte> .XOR. <byte> .XOR. #data .NOT. Rotate Left Rotate Left through Carry Rotate Right Rotate Right through Carry Swap Nibbles Accumulator only Accumulator only Accumulator only Accumulator only Accumulator only Accumulator only Accumulator only Ind. Reg.
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Data Transfers Internal RAM. Table shows menu instructions that available moving data around within internal memory spaces, addressing modes that used with each one. <dest>, <src> instruction allows data transferred between internal locations without going through Accumulator. Remember, Upper bytes data accessed only indirect addressing, space only direct addressing. Note: uPSD323X Devices, stack resides on-chip RAM, grows upwards. PUSH instruction first increments Stack Pointer (SP), then copies byte into stack. PUSH only direct addressing identify byte being saved restored, stack itself accessed indirect addressing using register. This means stack into Upper bytes RAM, they implemented, into space. Data Transfer instructions include 16-bit that used initialize Data Pointer (DPTR) look-up tables Program Memory.
<byte> instruction causes Accumulator ad-dressed byte exchange data. XCHD instruction similar, only nibbles involved exchange. XCHD used facilitate data manipulations, consider first problem shifting 8-digit number digits right. Table page shows this done using instructions. understanding code works, contents registers that holding number content Accumulator shown alongside each instruction indicate their status after instruction been executed. After routine been executed, Accumulator contains digits that were shifted right. Doing routine with direct MOVs uses code bytes. same operation with XCHs uses only bytes executes almost twice fast. right-shift number digits, one-digit must executed. Table page shows sample code that will rightshift number digit, using XCHD instruction. Again, contents registers holding number accumulator shown alongside each instruction.
Table Data Transfer Instructions that Access Internal Data Memory Space
Addressing Modes Mnemonic A,<src> <dest>,A <dest>,<src> DPTR,#data16 PUSH <src> <dest> A,<byte> XCHD A,@Ri Operation Dir. <src> <dest> <dest> <src> DPTR 16-bit immediate constant "@SP",<src> <dest>,"@SP"; Exchange contents <byte> Exchange nibbles Ind. Reg.
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First, pointers point bytes containing last four digits. Then loop executed which leaves last byte, location 2EH, holding last digits shifted number. pointers decremented, loop repeated location 2DH. CJNE instruction (Compare Jump equal) loop control that will described later. loop executed from LOOP CJNE 2EH, 2DH, 2CH, 2BH. that point digit that originally shifted right propagated location 2AH. Since that location should left with lost digit moved Accumulator. Table Shifting Number Digits Right (using direct MOVs: bytes)
A,2Eh 2Eh,2Dh 2Dh,2Ch 2Ch,2Bh 2Bh,#0
Table Shifting Number Digits Right (using direct XCHs: bytes)
A,2Bh A,2Ch A,2Dh A,2Eh
Table Shifting Number Digit Right
R1,#2Eh R0,#2Dh
loop LOOP: XCHD SWAP CNJE A,@R1 A,@R0 @R1,A R1,#2Ah,LOOP
loop loop loop
A,2Ah
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External RAM. Table shows list Data Transfer instructions that access external Data Memory. Only indirect addressing used. choice whether one-byte address, @Ri, where either selected register bank, two-byte address, @DTPR. Note: external Data accesses, Accumulator always either destination source data. Lookup Tables. Table shows instructions that available reading lookup tables Program Memory. Since these instructions access only Program Memory, lookup tables only read, updated. mnemonic MOVC "move constant." first MOVC instruction Table accommodate table entries numbered through 255. number desired entry loaded into Accumulator, Data Pointer point beginning table. Then: MOVC @A+DPTR copies desired table entry into Accumulator. other MOVC instruction works same way, except Program Counter (PC) used table base, table accessed through subroutine. First number desired en-try loaded into Accumulator, subroutine called: ENTRY NUMBER CALL TABLE subroutine "TABLE" would look like this: TABLE: MOVC @A+PC table itself immediately follows (return) instruction Program Memory. This type table have entries, numbered through 255. Number cannot used, because time MOVC instruction executed, contains address instruction. entry numbered would opcode itself.
Table Data Transfer Instruction that Access External Data Memory Space
Address Width bits bits bits bits Mnemonic MOVX A,@Ri MOVX @Ri,A MOVX A,@DPTR MOVX @DPTR,a Operation READ external WRITE external READ external @DPTR WRITE external @DPTR
Table Lookup Table READ Instruction
Mnemonic MOVC A,@A+DPTR MOVC A,@A+PC Operation READ program memory (A+DPTR) READ program memory (A+PC)
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Boolean Instructions uPSD323X Devices contain complete Boolean (single-bit) processor. page internal contains address-able bits, space support addressable bits well. port lines bit-addressable, each treated separate singlebit port. instructions that access these bits just conditional branches, complete menu move, set, clear, complement, instructions. These kinds operations easily obtained other architectures with amount byte-oriented software. instruction Boolean processor shown Table bits accesses direct addressing. addresses through Lower 128, ad-dresses through space. Note easily internal flag moved port pin: C,FLAG P1.0,C this example, FLAG name addressable Lower space. line (the Port this case) cleared depending whether Flag '0.' Carry used single-bit Accumulator Boolean processor. instructions that refer Carry assemble Carry-specific instructions (CLR etc.). Carry also direct address, since resides register, which bit-addressable. Note: Boolean instruction includes operations, (Exclusive operation. operation simple implement software. Suppose, example, required form Exclusive bits: .XRL. bit2 software that could follows: bit1 bit2, OVER OVER: (continue) First, moved Carry. bit2 then contains correct result. That .XRL. bit2 bit1 bit2 other hand, bit2 contains complement correct result. need only inverted (CPL complete operation. This code uses instruction, series bit-test instructions which execute jump
addressed (JC, JBC) addressed (JNC, JNB). above case, being tested, bit2 instruction jumped over. executes jump addressed set, also clears bit. Thus flag tested cleared operation. bits directly addressable, Parity Bit, general-purpose flags, example, also available bit-test instructions. Table Boolean Instructions
Mnemonic C,bit C,/bit C,bit C,/bit C,bit bit,C SETB SETB bit,rel bit,rel bit,rel Operation .AND. .AND. .NOT. .OR. .OR. .NOT. .NOT. .NOT. Jump Jump Jump Jump Jump
Relative Offset destination address these jumps specified assembler label actual address Program memory. How-ever, destination address assembles relative offset byte. This signed (two's complement) offset byte which added two's complement arithmetic jump executed. range jump therefore -128 +127 Program Memory bytes relative first byte following instruction.
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Jump Instructions Table shows list unconditional jump instructions. table lists single "JMP add" instruction, fact there three SJMP, LJMP, AJMP, which differ format destination address. generic mnemonic which used programmer does care which jump en-coded. SJMP instruction encodes destination address relative offset, described above. instruction bytes long, consisting opcode relative offset byte. jump distance limited range -128 +127 bytes relative instruction following SJMP. LJMP instruction encodes destination address 16-bit constant. instruction bytes long, consisting opcode address bytes. destination address anywhere Program Memory space. AJMP instruction encodes destination address 11-bit constant. instruction bytes long, consisting opcode, which itself contains address bits, followed another byte containing bits destination address. When instruction executed, these bits simply substituted bits high bits stay same. Hence destination within same block instruction following AJMP. cases programmer specifies destination address assembler same way: label 16-bit constant. assembler will destination address into correct format given instruction. format required instruction will support distance specified destination address, "Destination range" message written into List file. @A+DPTR instruction supports case jumps. destination address computed execution time 16-bit DPTR register Accumulator. Typically. DPTR with address jump table. 5-way branch, ex-ample, integer through loaded into Accumulator. code executed might follows: DPTR,#JUMP TABLE A,INDEX_NUMBER @A+DPTR
instruction converts index number through even number range through because each entry jump table bytes long: JUMP TABLE: AJMP CASE AJMP CASE AJMP CASE AJMP CASE AJMP CASE Table shows single "CALL addr" instruction, there them, LCALL ACALL, which differ format which subroutine address given CPU. CALL generic mnemonic which used programmer does care which address encoded. LCALL instruction uses 16-bit address format, subroutine anywhere Program Memory space. ACALL instruction uses 11-bit format, subroutine must same block instruction following ACALL. case, programmer specifies subroutine address assembler same way: label 16-bit constant. assembler will address into correct format given instructions. Subroutines should with instruction, which returns execution instruction following CALL. RETI used return from interrupt service routine. only difference between RETI that RETI tells interrupt control system that interrupt progress done. there interrupt progress time RETI executed, then RETI functionally identical RET. Table Unconditional Jump Instructions
Mnemonic addr @A+DPTR CALL addr RETI Operation Jump addr Jump A+DPTR Call Subroutine addr Return from subroutine Return from interrupt operation
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Table shows list conditional jumps available uPSD323X Devices user. these jumps specify destination address relative offset method, limited jump distance -128 +127 bytes from instruction following conditional jump instruction. Important note, however, user specifies assembler actual destination address same other jumps: label 16-bit constant. There Zero PSW. instructions test Accumulator data that condition. DJNZ instruction (Decrement Jump Zero) loop control. execute loop times, load counter byte with terminate loop with DJNZ beginning loop, shown below COUNTER,#10 LOOP: (begin loop) (end loop) DJNZ COUNTER, LOOP (continue) CJNE instruction (Compare Jump Equal) also used loop control Table page bytes specified operand field instruction. jump executed only bytes equal. example Table page Shifting Number Digits Right, bytes were data constant 2Ah. initial data 2Eh. Every time loop executed, decremented, looping continue until data reached 2Ah. Another application this instruction "greater than, less than" comparisons. bytes operand field taken unsigned integers. first less than second, then Carry (1). first greater than equal second, then Carry cleared Machine Cycles machine cycle consists sequence states, numbered through Each state time lasts oscillator periods. Thus, machine cycle takes oscillator periods oscillator frequency 12MHz. Refer Figure 14., page Each state divided into Phase half Phase half. State Sequence uPSD323X Devices shows that retrieve/execute sequences states phases various kinds instructions. Normally program retrievals generated during each machine cycle, even instruction being executed does require instruction being executed does need more code bytes, simply ignores extra retrieval, Program Counter incremented. Execution one-cycle instruction (Figure 14., page begins during State machine cycle, when opcode latched into Instruction Register. second retrieve occurs during same machine cycle. Execution complete State this machine cycle. MOVX instructions take machine cycles execute. program retrieval generated during second cycle MOVX instruction. This only time program retrievals skipped. retrieve/execute sequence MOVX instruction shown Figure 14., page (d).
Table Conditional Jump Instructions
Addressing Modes Mnemonic DJNZ <byte>,rel CJNE A,<byte>,rel CJNE <byte>,#data,rel Operation Dir. Jump Jump Decrement jump zero Jump <byte> Jump <byte> #data Ind. Reg. Accumulator only Accumulator only
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Figure State Sequence uPSD323X Devices
Osc. (XTAL2)
Read opcode
Read next opcode discard
Read next opcode
1-Byte, 1-Cycle Instruction, e.g. Read Byte Read next opcode
Read opcode
2-Byte, 1-Cycle Instruction, e.g. adrs Read next opcode discard Read next opcode discard Read next opcode discard Read next opcode
Read opcode
1-Byte, 2-Cycle Instruction, e.g. DPTR Read next opcode discard Addr Fetch Fetch Read next opcode
Read opcode (MOVX)
Data
1-Byte, 2-Cycle MOVX Instruction
Access External Memory
AI06822
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uPSD3200 HARDWARE DESCRIPTION
uPSD323X Devices modular architecture with main functional modules: Module Module. Module consists standard 8032 core, peripherals other system supporting functions. Module provides configurable Program Data memories 8032 core. addition, ports with macrocells general logic implementation. Ports A,B,C, general purpose programmable ports Figure uPSD323X Devices Functional Modules
Port UART, Intr, Timers,I2C Port Timers UART Port Dedicated Pins
that have port architecture which different from Ports Module. Module communicates with Core through internal address, data (A0A15, D0-D7) control signals (RD_, WR_, PSEN_ ALE, RESET_). user defines Decoding PSDsoft Development Tool resources Module program data address space.
Port 8032 Core UARTs Interrupt
Port Timer Counters Byte SRAM Channel Channels Reset Logic Byte Transceiver SRAM
MODULE 8032 Internal A0-A15 RD,PSEN WR,ALE MODULE Page Register Decode Main Flash 256Kb Secondary Flash 64Kb SRAM Interface D0-D7 Reset Port Ext.
Internal
JTAG
CPLD MACROCELLS
VCC, GND, XTAL
Port JTAG, GPIO
Port GPIO
Port GPIO
Dedicated Pins
AI06619C
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MODULE DISCRIPTION
This section provides detail description Module system functions Peripherals, including: Special Function Registers Timers/Counter Interrupts Supervisory Function (LVD Watchdog) USART Power Saving Modes On-chip Oscillator Ports Special Function Registers on-chip memory area called Special Function Register (SFR) space shown Table Note: SFRs addresses occupied. Unoccupied addresses implemented chip. READ accesses these addresses will general return random data, WRITE accesses will have effect. User software should write '0s' these unimplemented locations.
Table Memory
B(1) UISTA(1) ACC(1) S1CON(1) PSW(1) T2CON(1) P4(1) IP(1) P3(1) IE(1) P2(1) SCON P1(1) TCON(1) P0(1) PWMCON SBUF P1SFS TMOD PSCL0L PSCL0H PWM4P PWM0 SCON2 PSCL1L PWM4W PWM1 SBUF2 P3SFS P4SFS ASCL PCON ADAT ACON PWM2 PWM3 PSCL1H WDKEY WDRST UIEN USCL S1STA S1SETUP T2MOD S1DAT S2SETUP RCAP2L RCAP2H S1ADR S2CON RAMBUF S2STA DDCDAT UCON0 UCON1 UCON2 USTA UADR UDT1 S2DAT UDR0 UDT0 S2ADR
DDCADR DDCCON
Note: Register addressing
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Table List
Name Addr PCON TCON SMOD SMOD1 LVREN ADSFINT RCLK1 TCLK1 IDLE Register Name Reset Comments Value Port Stack Data Data High Power Ctrl Timer Cntr Control Timer Cntr Mode Control Timer Timer Timer High Timer High Port Port Select Register Port Select Register Port Select Register 8-bit Prescaler clock Data Register Control Register Serial Control Register Serial Buffer UART Ctrl Register UART Serial Buffer Port Control Polarity
TMOD P1SFS P3SFS P4SFS
Gate
Gate
P1S7 P3S7 P4S7
P1S6 P3S6 P4S6
P1S5
P1S4
P4S5
P4S4
P4S3
P4S2
P4S1
P4S0
ASCL
ADAT ACON
ADAT7
ADAT6
ADAT5 ADEN
ADAT4
ADAT3 ADS1
ADAT2 ADS0
ADAT1 ADST
ADAT0 ADSF
SCON SBUF SCON2 SBUF2
PWMCON
PWML
PWMP
PWME
CFG4
CFG3
CFG2
CFG1
CFG0
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Name Addr Register Name Reset Comments Value PWM0 Output Duty Cycle PWM1 Output Duty Cycle PWM2 Output Duty Cycle PWM3 Output Duty Cycle Watch Reset Interrupt Enable (2nd) Interrupt Enable
PWM0
PWM1
PWM2
PWM3
WDRST EDDC EI2C EUSB
PWM4P PWM4W WDKEY PSCL0L PSCL0H PSCL1L PSCL1H T2CON T2MOD EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2 DCEN PDDC PI2C PUSB
Period Pulse Width Watch Register Port Prescaler (8-bit) Prescaler High (8-bit) Prescaler (8-bit) Prescaler High (8-bit) Interrupt Priority (2nd) Interrupt Priority Port Timer Control Timer Mode
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Name Addr RCAP2L RCAP2H Register Name Reset Comments Value EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT ENI1 Stop Intr TX-Md ADDR Bbusy Blost ACK_R Stop Intr TX-Md ADDR Bbusy Blost ACK_R Timer Reload Timer Reload High Timer byte Timer High byte Program Status Word (S1) Setup (S2) Setup Buffer Data xmit register Addr pointer register Control Register Control Status Data Hold Register address Control Status Data Hold Register address Accumulator 8-bit Prescaler logic Endpt1 Data Xmit
S1SETUP S2SETUP RAMBUF DDCDAT DDCADR DDCCON S1CON S1STA S1DAT S1ADR S2CON S2STA S2DAT S2ADR USCL
UDT1
UDT1.7
UDT1.6 UDT1.5 UDT1.4
UDT1.3 UDT1.2 UDT1.1 UDT1.0
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Name Addr UDT0 Register Name UDT0.7 Reset Comments Value Endpt0 Data Xmit Interrupt Status Interrupt Enable Endpt0 Xmit Control Endpt1 Xmit Control Control Register Endpt0 Status Address Register Endpt0 Data Recv Register
UDT0.6 UDT0.5 UDT0.4
UDT0.3 UDT0.2 UDT0.1 UDT0.0
UISTA
SUSPND
RSTF
TXD0F
RXD0F
RXD1F
EOPF RESUMF
UIEN
SUSPNDI TSEQ0 TSEQ1 RSEQ
RSTE
RSTFIE TXD0IE RXD0IE TXD1IE
EOPIE
RESUMI
UCON0 UCON1 UCON2 USTA
STALL0 EP12SEL SETUP
TX0E
RX0E
TP0SIZ3 TP0SiZ2 TP0SIZ1 TP0SIZ0
FRESUM TP1SIZ3 TP1SiZ2 TP1SIZ1 TP1SIZ0 SOUT EP2E EP1E STALL2 STALL1
RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0
UADR
USBEN
UADD6
UADD5 UADD4
UADD3 UADD2 UADD1
UADD0
UDR0
UDR0.7
UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0
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Table Module Register Address Offset
CSIOP Addr Offset Register Name Register Name Data (Port Reads Port pins input Reset Value Comments
Control (Port Configure between Address Mode. selects Data (Port Direction (Port Drive (Port Input Macrocell (Port Enable (Port Data (Port Control (Port Data (Port Direction (Port Drive (Port Input Macrocell (Port Enable (Port Data (Port Data (Port Direction (Port Drive (Port Input Macrocell (Port Enable (Port Data (Port Data (Port Direction (Port Drive (Port Enable (Port Output Macrocells Latched data output Port pins, Output Mode Configures Port input output. selects input Configures Port between CMOS, Open Drain Slew rate. selects CMOS Reads latched value Input Macrocells Reads status output enable control Port driver. indicates input mode.
Only used Only used Only used Only used Only used
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CSIOP Addr Offset Register Name Register Name Output Macrocells Mask Macrocells Mask Macrocells Primary Flash Protection Sec7_ Prot Sec6_ Sec5_ Sec4_ Sec3_ Sec2_ Sec1_ Prot Prot Prot Prot Prot Prot Mcells array Sec3_ Sec2_ Sec1_ Prot Prot Prot enable Sec0_ Prot Sec0_ Prot sector protected Security device secured Control power consumption Blocking inputs array Page Register Configure 8032 Program Data Space
Reset Value
Comments
Secondary Flash Security Protection _Bit
PMMR0
arrayTurbo array Cntl2 array Cntl1
array Cntl0
PMMR2 Page
Periphmode
data
Boot_ data
code
Boot_ code
code
Note: (Register address csiop address address offset; where csiop address defined user PSDsoft) indicates used need '0.'
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INTERRUPT SYSTEM
There interrupt requests from sources follows. INT0 external interrupt USART Interrupt Timer Interrupt Interrupt INT1 External Interrupt Interrupt) Interrupt Timer Interrupt Interrupt USART Interrupt Timer Interrupt External Int0 INT0 either level-active transition-active depending register TCON. flag that actually generates this interrupt TCON. When external interrupt generated, corresponding request flag cleared hardware when service routine vectored only interrupt transition activated. interrupt level activated then interrupt request flag remains until requested interrupt actually generated. Then deactivate request before interrupt service routine completed, else another interrupt will generated. Timer Interrupts Timer Timer Interrupts generated which overflow their respective Timer/Counter registers (except Timer Mode These flags cleared internal hardware when interrupt serviced. Timer Interrupt Timer Interrupt generated which overflow Timer This flag cleared software hardware. also generated T2EX signal (Timer External Interrupt P1.1) which controlled EXEN2 EXF2 Bits T2CON register. Interrupt interrupt generated INTR register S2STA. This flag cleared hardware. External Int1 INT1 either level active transition active depending register TCON. flag that actually generates this interrupt TCON. When external interrupt generated, corresponding request flag cleared hardware when service routine vectored only interrupt transition activated. interrupt level activated then interrupt request flag remains until requested interrupt actually generated. Then deactivate request before interrupt service routine completed, else another interrupt will generated. take over External INT1 generate interrupt conversion being completed Interrupt Interrupt generated either INTR S1STA register DC2B protocol Interrupt DDCCON register DDC1 protocol SWHINT DDCCON register when protocol changed from DDC1 DDC2. Flags except INTR have cleared software. INTR flag cleared hardware. Interrupt Interrupt generated when endpoint0 transmitted packet received packet, when endpoint1 endpoint2 transmitted packet, when suspend resume state detected every received. When Interrupt generated, corresponding request flag must cleared software. interrupt service routine will have check various registers determine source clear corresponding flag. Please dedicated interrupt control registers peripheral more information.
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USART Interrupt USART Interrupt generated (receive interrupt) (transmit interrupt). When USART Interrupt generated, corresponding request flag must cleared software. interrupt service routine will have check various USART registers Figure Interrupt System
Interrupt Sources INT0 USART Priority High
determine source clear corresponding flag. Both USART's identical, except additional interrupt controls additional interrupt control registers (A7H, B7H)
Timer Interrupt Polling INT1 Timer USART
Timer
Global Enable
AI06646
Table Register
Addr Name Register Name EDDC PDDC EI2C PI2C EUSB PUSB Reset Comments Value Interrupt Enable (2nd) Interrupt Enable Interrupt Priority (2nd) Interrupt Priority
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Interrupt Priority Structure Each interrupt source assigned priority levels. Interrupt priority levels defined interrupt priority special function register IPA. priority high priority priority interrupt interrupted high priority interrupt level interrupt. high priority interrupt routine cannot interrupted other interrupt source. interrupts different priority occur simultaneously, high priority level request serviced. requests same priority received simultaneously, internal polling sequence determines which request serviced. Thus, within each priority level, there second priority structure determined polling sequence. Interrupts Enable Structure Each interrupt source individually enabled disabled setting clearing interrupt enable special function register IEA. Table Description Bits
Symbol Function Disable interrupts: interrupt with acknowledged each interrupt source individually enabled disabled setting clearing enable Reserved Enable Timer Interrupt Enable USART Interrupt Enable Timer Interrupt Enable external Interrupt (Int1) Enable Timer Interrupt Enable external Interrupt (Int0)
interrupt source also globally disabled clearing Table Priority Levels
Source Int0 USART Timer Int1 Timer USART Timer 2+EXF2 Priority with Level (highest) (lowest)
Table Description Bits
Symbol EDDC EI2C EUSB Enable Interrupt used used Enable USART Interrupt used used Enable Interrupt Enable Interrupt Function
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Table Description Bits
Symbol Reserved Reserved Timer Interrupt priority level USART Interrupt priority level Timer Interrupt priority level External Interrupt (Int1) priority level Timer Interrupt priority level External Interrupt (Int0) priority level Function
Table Description Bits
Symbol PDDC PI2C PUSB Interrupt priority level used used USART Interrupt priority level used used Interrupt priority level Interrupt priority level Function
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Interrupts Handled interrupt flags sampled S5P2 every machine cycle. samples polled during following machine cycle. flags condition S5P2 preceding cycle, polling cycle will find interrupt system will generate LCALL appropriate service routine, provided this generated LCALL blocked following conditions: interrupt equal priority higher priority level already progress. current machine cycle final cycle execution instruction progress. instruction progress RETI access interrupt priority interrupt enable registers. polling cycle repeated with each machine cycle, values polled values that were present S5P2 previous machine cycle. Note: interrupt flag active being responded above mentioned conditions, flag still inactive when blocking condition removed, denied interrupt will serviced. other words, fact that interrupt flag once active serviced remembered. Every polling cycle new. processor acknowledges interrupt request executing hardware generated LCALL appropriate service routine. hardware generated LCALL pushes contents Program Counter stack (but does save PSW) reloads with address that depends source interrupt being vectored shown Table
Execution proceeds from that location until RETI instruction encountered. RETI instruction informs processor that interrupt routine longer progress, then pops bytes from stack reloads Program Counter. Execution interrupted program continues from where left off. Note: simple instruction would also return execution interrupted program, would have left interrupt control system thinking interrupt still progress, making future interrupts impossible. Table Vector Addresses
Source Int0 USART Timer Int1 Timer USART Timer 2+EXF2 Vector Address 0003h 004Bh 000Bh 0043h 0013h 003Bh 001Bh 0033h 0023h 002Bh
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POWER-SAVING MODE
software selectable modes reduced power consumption implemented. Idle Mode following Functions Switched Off. (Halted) following Function Remain Active During Idle Mode. External Interrupts Timer Timer Timer Interface Units Interface USART 8-bit Interface Note: Interrupt RESET terminates Idle Mode. Power-Down Mode System Clock Halted Logic Remains Active SRAM contents remains unchanged SFRs retain their value until RESET asserted Note: only exit Power-down Mode RESET.
Table Power-Saving Mode Power Consumption
Mode Idle Power-down Addr/Data Maintain Data Maintain Data Ports1,3,4 Maintain Data Maintain Data Active Disable Active Disable Active Disable Active Disable
Power Control Register Idle Power-down Modes activated software PCON register. Table Status During Idle Power-down Mode
Addr Name PCON Register Name SMOD TCLK1 IDLE Reset Comments Value Power Ctrl
SMOD1 LVREN ADSFINT RCLK1
Table Description PCON Bits
Symbol SMOD SMOD1 LVREN ADSFINT RCLK1(1) TCLK1(1) Double baud data rate UART Double baud data rate UART disable (active High) Enable Interrupt Received clock flag (UART Transmit clock flag (UART Activate Power-down Mode (High enable) Activate Idle Mode (High enable) Function
Note: T2CON register details flag description
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Idle Mode instruction that sets PCON.0 last instruction executed normal operating mode before Idle Mode activated. Once Idle Mode, status preserved entirety: Stack pointer, Program counter, Program status word, Accumulator, other registers maintain their data during Idle Mode. There three ways terminate Idle Mode. Activation enabled interrupt will cause PCON.0 cleared hardware terminating Idle mode. interrupt serviced, following return from interrupt instruction RETI, next instruction executed will which follows instruction that wrote logic PCON.0.
External hardware reset: hardware reset required active machine cycle complete RESET operation. Internal reset: microcontroller restarts after machine cycles cases. Power-Down Mode instruction that sets PCON.1 last executed prior going into Power-down Mode. Once Power-down Mode, oscillator stopped. contents on-chip Special Function Register preserved. Power-down Mode terminated external RESET.
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PORTS (MCU MODULE)
Module five ports: Port Port Port Port Port (Refer Module section ports A,B,C Ports dedicated external address data available 52-pin package devices. Port Port same standard 8032 micro-controllers, with exception additional special peripheral functions. ports bi-directional. Pins which alternative function used used normal bi-directional I/O. Port Port pins alternative functions carried automatically uPSD323X Devices provided associated HIGH. following registers (Tables used control mapping alternate functions onto port bits. Port alternate Table Port Functions
Port Name Port Main Function GPIO Alternate Timer Bits UART Bits Bits UART Bits Interrupt Bits Timers Bits Bits Bits Bits
functions controlled using P1SFS register, except Timer UART which enabled their configuration registers. P1.0 P1.3 default GPIO after reset. Port pins have been modified from standard 8032. These pins that were used READ WRITE control signals GPIO pins. READ WRITE pins assigned dedicated pins. Port (I2C) Port alternate functions controlled using P3SFS P4SFS Special Function Selection registers. After reset, pins default GPIO. alternate function enabled corresponding PXSFS register '1.' Other Port alternative functions (UART, Interrupt, Timer/Counter) enabled their configuration register require setting bits P3SFS.
Port
GPIO
Port
GPIO Only
Table P1SFS (91H)
0=Port 1=ACH3 0=Port 1=ACH2 0=Port 1=ACH1 0=Port 1=ACH0
Bits Reserved
Bits Reserved
Table P3SFS (93H)
Port Port from unit from unit
Bits reserved.
Table P4SFS (94H)
0=Port 1=PWM 0=Port 1=PWM 0=Port 1=PWM 0=Port 1=PWM 0=Port 1=PWM 0=Port 1=VSYNC 0=Port 1=DDC 0=Port 1=DDC
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PORT Type Description Figure PORT Type Description (Part
Symbol RESET Circuit Description Schmitt input with internal pull-up CMOS compatible interface 400ns
RD,ALE, PSEN
Output only
XTAL1, XTAL2
On-chip oscillator On-chip feedback resistor Stop power down mode External clock input available CMOS compatible interface
PORT0
Bidirectional port Schmitt input Address Output Push-Pull CMOS compatible interface
AI06653
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Figure PORT Type Description (Part
Symbol PORT1 <3:0>, PORT3, PORT4<7:3,1:0> PORT2 Circuit Function Bidirectional port with internal pull-ups Schmitt input CMOS compatible interface
PORT1
Bidirectional port with internal pull-ups Schmitt input CMOS compatible interface Analog input option
an_enb
PORT4.2
Bidirectional port with internal pull-ups Schmitt input. compatible interface Pull-up when reset Address Latch Enable Program Strobe Enable
Bidirectional port Schmitt input compatible interface
AI06654
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OSCILLATOR
oscillator circuit uPSD323X Devices single stage inverting amplifier Pierce oscillator configuration. circuitry between XTAL1 XTAL2 basically inverter biased transfer point. Either crystal ceramic resonator used feedback element complete Figure Oscillator oscillator circuit. Both operated parallel resonance. XTAL1 high gain amplifier input, XTAL2 output. drive uPSD323X Devices externally, XTAL1 driven from external source XTAL2 left open-circuit.
XTAL1
XTAL2
XTAL1
XTAL2
External Clock
AI06620
SUPERVISORY
There four ways invoke reset initialize uPSD323X Devices. external RESET internal Block. reset signaling. Watch timer Figure RESET Configuration RESET mechanism illustrated Figure Each RESET source will cause internal reset signal active. responds executing internal reset puts internal registers defined state. This internal reset also routed active reset input Module.
Reset Noise Cancel RSTE 10ms Timer 10ms 40Mhz 50ms 8Mhz Clock Sync
PERI.
PSD_RST "Active
Reset
AI06621
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External Reset RESET connected Schmitt trigger noise reduction. RESET accomplished holding RESET least power while oscillator running. Refer spec other RESET timing requirements. Voltage Reset internal reset generated circuit when drops below reset threshold. After reaching back reset threshold, RESET signal will remain asserted 10ms before released. initial power-up enabled (default). After power-up disabled LVREN PCON Register. Note: logic still functional both Idle Power-down Modes. reset threshold: operation: 0.25V 3.3V operation: 2.5V +/-0.2V This logic supports approximately 0.1V hysteresis noise-cancelling delay. Watchdog Timer Overflow Watchdog timer generates internal reset when 22-bit counter overflows. Watchdog Timer section details. Reset reset generated detection RESET signal. single-end zero upstream port times will RSTF UISTA register. (RSTE) UIEN Register set, detection will also generate RESET signal reset other peripherals MCU.
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WATCHDOG TIMER
hardware watchdog timer (WDT) resets uPSD323X Devices when overflows. intended recovery method situations where subjected software upset. prevent system reset timer must reloaded time application software. processor suffers hardware/software malfunction, software will fail reload timer. This failure will result reset upon overflow thus preventing processor running control. Idle Mode watchdog timer reset circuitry remain active. consists 22-bit counter, Watchdog Timer RESET (WDRST) Watchdog Register (WDKEY). Since automatically enabled while processor running. user only needs concerned with servicing 22-bit counter overflows when reaches 4194304 (3FFFFFH). increments once every machine cycle. This means user must reset least every 4194304 machine cycles (1.258 seconds 40MHz). reset user must write value between 00-7EH WDRST register. value that written WDRST loaded 7MSB 22-bit counter. This allows user pre-loaded counter initial value generate flexible Watchdog time period. Writing "00" WDRST clears counter. watchdog timer controlled watchdog register, WDKEY. Only pattern 01010101 (=55H), disables watchdog timer. rest pattern combinations will keep watchdog timer enabled. This security will prevent watchdog timer from being terminated abnormally when function watchdog timer needed. Idle Mode, oscillator continues run. prevent from resetting processor while Idle, user should always timer that will periodically exit Idle, service WDT, re-enter Idle Mode. Watchdog reset pulse width depends clock frequency. reset period TfOSC 222. RESET pulse width TfOSC 215.
Table Watchdog Timer Register (WDKEY: 0AEH)
WDKEY7 WDKEY6 WDKEY5 WDKEY4 WDKEY3 WDKEY2 WDKEY1 WDKEY0
Table Description WDKEY Bits
Symbol WDKEY7 WDKEY0 Function Enable disable watchdog timer. 01010101 (=55h): disable watchdog timer. Others: enable watchdog timer
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Figure RESET Pulse Width
Reset pulse width (about 10ms 40Mhz, about 50ms 8Mhz)
Reset period (1.258 second 40Mhz) (about 6.291 seconds 8Mhz)
AI06823
Table Watchdog Timer Clear Register (WDRST: 0A6H)
Reserved WDRST6 WDRST5 WDRST4 WDRST3 WDRST2 WDRST1 WDRST0
Table Description WDRST Bits
Symbol WDRST6 WDRST0 Reserved reset watchdog timer, write value beteen this register. This value loaded most significant bits 22-bit counter. example: WDRST,#1EH Function
Note: Watchdog Timer (WDT) enabled power-up reset must served disabled.
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TIMER/COUNTERS (TIMER TIMER TIMER
uPSD323X Devices three 16-bit Timer/ Counter registers: Timer Timer Timer them configured operate either timers event counters compatible with standard 8032 architecture. "Timer" function, register incremented every machine cycle. Thus, think counting machine cycles. Since machine cycle consists clock periods, count rate clock frequency 1/12 oscillator frequency (fOSC). "Counter" function, register incremented response 1-to-0 transition corresponding external input pin, this function, external input sampled during S5P2 every machine cycle. When samples show high cycle next cycle, count incremented. count value appears register during S3P1 cycle Table Control Register (TCON)
following which transition detected. Since takes machine cycles fOSC clock periods) recognize 1-to-0 transition, maximum count rate 1/24 fOSC. There restrictions duty cycle external input signal, ensure that given level sampled least once before changes, should held least full cycle. addition "Timer" "Counter" selection, Timer Timer have four operating modes from which select. Timer Timer "Timer" "Counter" function selected control bits Special Function Register TMOD. These Timer/Counters have four operating modes, which selected bit-pairs (M1, TMOD. Modes same Timers/ Counters. Mode different. four operating modes de-scribed following text.
Table Description TCON Bits
Symbol Function Timer Overflow Flag. hardware Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine Timer Control Bit. Set/cleared software turn Timer/Counter Timer Overflow Flag. hardier Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine Timer Control Bit. Set/cleared software turn Timer/Counter Interrupt Edge Flag. hardware when external interrupt edge detected. Cleared when interrupt processed Interrupt Type Control Bit. Set/cleared software specify falling-edge/low-level triggered external interrupt Interrupt Edge Flag. hardware when external interrupt edge detected. Cleared when interrupt processed Interrupt Type Control Bit. Set/cleared software specify falling-edge/low-level triggered external interrupt
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Mode Putting either Timer into Mode makes look like 8048 Timer, which 8-bit Counter with divide-by-32 prescaler. Figure 22., page shows Mode operation applies Timer1. this mode, Timer register configured 13-bit register. count rolls over from '1s' '0s,' sets Timer Interrupt Flag TF1. counted input enabled Timer when either GATE /INT1 (Setting GATE allows Timer controlled external input /INT1, facilitate pulse width measurements). control Special Function Register TCON (TCON Control Register). GATE TMOD. Table TMOD Register (TMOD)
Gate Gate
13-bit register consists bits lower bits TL1. upper bits indeterminate should ignored. Setting flag does clear registers. Mode operation same Timer0 Timer1. Substitute TR0, TF0, /INT0 corresponding Timer1 signals Figure 22., page There different GATE Bits, Timer1 Timer0. Mode Mode same Mode except that Timer register being with bits.
Table Description TMOD Bits
Symbol Gate Timer Timer Function Gating control when set. Timer/Counter enabled only while INT1 High control set. When cleared, Timer enabled whenever control Timer Counter selector, cleared timer operation (input from internal system clock); counter operation (input from input pin) (M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with 5-bit prescaler (M1,M0)=(0,1): 16-bit Timer/Counter. cascaded. There prescaler. (M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. holds value which reloaded into each time overflows (M1,M0)=(1,1): Timer/Counter stopped Gating control when set. Timer/Counter enabled only while INT0 High control set. When cleared, Timer enabled whenever control Timer Counter selector, cleared timer operation (input from internal system clock); counter operation (input from input pin) Timer (M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with 5-bit prescaler (M1,M0)=(0,1): 16-bit Timer/Counter. cascaded. There prescaler. (M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. holds value which reloaded into each time overflows (M1,M0)=(1,1): 8-bit Timer/Counter controlled standard TImer control bits. 8-bit timer only controlled Timer control bits
Gate
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Figure Timer/Counter Mode 13-bit Counter
fOSC
bits) Control bits) Interrupt
Gate INT1
AI06622
Figure Timer/Counter Mode 8-bit Auto-reload
fOSC
bits) Control Interrupt
Gate INT1 bits)
AI06623
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Figure Timer/Counter Mode 8-bit Counters
fOSC
bits) Control Interrupt
Gate INT0
fOSC
Control
bits)
Interrupt
AI06624
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Mode Mode configures Timer register 8-bit Counter (TL1) with automatic reload, shown Figure 23., page Overflow from only sets TF1, also reloads with contents TH1, which preset software. reload leaves unchanged. Mode operation same Timer/Counter Mode Timer Mode simply holds count. effect same setting Timer Mode establishes separate counters. logic Mode Timer shown Figure 24., page uses Timer control Bits: C/T, GATE, TR0, INT0, TF0. locked into timer function (counting machine cycles) takes over from Timer Thus, controls "Timer Interrupt. Mode provided applications requiring extra 8-bit timer counter. With Timer Mode uPSD323X Devices look like three Timer/Counters. When Timer Mode Timer turned switching into Mode still used serial port baud rate generator, fact, application requiring interrupt. Timer Like Timers Timer operate either event timer event counter. This selected C/T2 special function register T2CON. three operating modes: capture, autoload, baud rate generator, which selected bits T2CON shown Table 41., page Capture Mode there options which selected EXEN2 T2CON. EXEN2 then Timer 16-bit timer counter which upon overflowing sets TF2, Timer Overflow Bit, which used generate interrupt. EXEN2 then Timer still does above, with added feature that 1-to-0 transition external input T2EX causes current value Timer registers, TH2, captured into registers RCAP2L RCAP2H, respectively. addition, transition T2EX causes EXF2 T2CON set, EXF2 like generate interrupt. Capture Mode illustrated Figure 25., page Auto-reload Mode, there again options, which selected EXEN2 T2CON. EXEN2 then when Timer rolls over only sets also causes Timer registers reloaded with 16-bit value registers RCAP2L RCAP2H, which preset software. EXEN2 then Timer still does above, with added feature that 1-to-0 transition external input T2EX will also trigger 16-bit reload EXF2. Auto-reload Mode illustrated Standard Serial Interface (UART) Figure 26., page Baud Rate Generation Mode selected (RCLK, RCLK1)=1 and/or (TCLK, TCLK1)=1. will described conjunction with serial port.
Table Timer/Counter Control Register (T2CON)
EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2
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Table Description T2CON Bits
Symbol Function Timer overflow flag. Timer overflow, must cleared software. will when either (RCLK, RCLK1)=1 (TCLK, TCLK)=1 Timer external flag when either capture reload caused negative transition T2EX EXEN2=1. When Timer Interrupt enabled, EXF2=1 will cause vector Timer Interrupt routine. EXF2 must cleared software Receive clock flag (UART When set, causes serial port Timer overflow pulses receive clock Modes TCLK=0 causes Timer overflow used receive clock Transmit clock flag (UART When set, causes serial port Timer overflow pulses transmit clock Modes TCLK=0 causes Timer overflow used transmit clock Timer external enable flag. When set, allows capture reload occur result negative transition T2EX Timer being used clock serial port. EXEN2=0 causes Time ignore events T2EX Start/stop control Timer logic starts timer Timer Counter select Timer Cleared timer operation (input from internal system clock, tCPU); external event counter operation (negative edge triggered) Capture/reload flag. When set, capture will occur negative transition T2EX EXEN2=1. When cleared, auto-reload will occur either with TImer overflows, negative transitions T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 (TCLK, TCLK)=1, this ignored, timer forced auto-reload Timer overflow
EXF2
RCLK(1)
TCLK(1)
EXEN2 C/T2
CP/RL2
Note: RCLK1 TCLK1 Bits PCON Register control UART have same function RCLK TCLK.
Table Timer/Counter2 Operating Modes
T2CON Mode RxCLK TxCLK 16-bit Autoreload 16-bit Capture Baud Rate Generator T2MOD DECN T2CON EXEN P1.1 T2EX Remarks Internal reload upon overflow reload trigger (falling edge) Down counting counting 16-bit Timer/Counter (only counting) Capture (TH1,TL2) (RCAP2H,RCAP2L) overflow interrupt request (TF2) Extra External Interrupt (Timer Timer stops fOSC/12 fOSC/24 Input Clock External (P1.0/T2)
fOSC/12
fOSC/24
fOSC/12
fOSC/24
Note: falling edge
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Figure Timer Capture Mode
fOSC
C/T2 bits) Control bits)
C/T2
Capture RCAP2L RCAP2H Timer Interrupt
Transition Detector
T2EX Control
EXP2
EXEN2
AI06625
Figure Timer Auto-Reload Mode
fOSC
C/T2 bits) Control bits)
C/T2
Reload RCAP2L RCAP2H Timer Interrupt
Transition Detector
T2EX Control
EXP2
EXEN2
AI06626
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STANDARD SERIAL INTERFACE (UART)
uPSD323X Devices provides standard 8032 UART serial ports. first port connected P3.0 (RX) P3.1 (TX). second port connected P1.2 (RX) P1.3(TX). operation serial ports same controlled SCON SCON2 registers. serial port full duplex, meaning transmit receive simultaneously. also receivebuffered, meaning commence reception second byte before previously received byte been read from register. (However, first byte still been read time reception second byte complete, bytes will lost.) serial port receive transmit registers both accessed Special Function Register SBUF SBUF2 second serial port). Writing SBUF loads transmit register, reading SBUF accesses physically separate receive register. serial port operate modes: Mode Serial data enters exits through RxD. outputs shift clock. bits transmitted/received (LSB first). baud rate fixed 1/12 fOSC. Mode bits transmitted (through TxD) received (through RxD): start (0), data bits (LSB first), Stop (1). receive, Stop goes into Special Function Register SCON. baud rate variable. Mode bits transmitted (through TxD) received (through RxD): start (0), data bits (LSB first), programmable data bit, Stop (1). Transmit, data (TB8 SCON) assigned value '1.' example, Parity PSW) could moved into TB8. receive, data goes into Special Function Register SCON, while Stop ignored. baud rate programmable either 1/32 1/64 oscillator frequency. Mode bits transmitted (through TxD) received (through RxD): start (0), data bits (LSB first), programmable data bit, Stop (1). fact, Mode same Mode respects except baud rate. baud rate Mode variable. four modes, transmission initiated instruction that uses SBUF destination register. Reception initiated Mode condition Reception initiated other modes incoming start Multiprocessor Communications Modes have special provision multiprocessor communications. these modes, data bits received. goes into RB8. Then comes Stop Bit. port programmed such that when Stop received, serial port interrupt will activated only This feature enabled setting SCON. this feature multi-processor systems follows: When master processor wants transmit block data several slaves, first sends address byte which identifies target slave. address byte differs from data byte that address byte data byte. With slave will interrupted data byte. ad-dress byte, however, will interrupt slaves, that each slave examine received byte being addressed. addressed slave will clear prepare receive data bytes that will coming. slaves that weren't being addressed leave their SM2s about their business, ignoring coming data bytes. effect Mode Mode used check validity Stop Bit. Mode reception, receive interrupt will activated unless valid Stop received. Serial Port Control Register serial port control status register Special Function Register SCON (SCON2 second port), shown Figure 27., page This register contains only mode selection bits, also data transmit receive (TB8 RB8), Serial Port Interrupt Bits RI).
Table Serial Port Control Register (SCON)
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Table Description SCON Bits
Symbol Function (SM1,SM0)=(0,0): Shift Register. Baud rate fOSC/12 (SM1,SM0)=(1,0): 8-bit UART. Baud rate variable (SM1,SM0)=(0,1): 8-bit UART. Baud rate fOSC/64 fOSC/32 (SM1,SM0)=(1,1): 8-bit UART. Baud rate variable Enables multiprocessor communication features Mode Mode '1,' will activated received data (RB8) '0.' Mode SM2=1, will activated valid Stop received. Mode should Enables serial reception. software enable reception. Clear software disable reception data that will transmitted Modes clear software desired Modes this contains data that received. Mode SM2=0, Snap that received. Mode used Transmit Interrupt Flag. hardware time Mode beginning Stop other modes, serial transmission. Must cleared software Receive Interrupt Flag. hardware time Mode halfway through Stop other modes, serial reception (except SM2). Must cleared software
Baud Rates. baud rate Mode fixed: Mode Baud Rate fOSC baud rate Mode depends value SMOD (which value reset), baud rate 1/64 oscillator frequency. SMOD baud rate 1/32 oscillator frequency. Mode Baud Rate (2SMOD fOSC uPSD323X Devices, baud rates Modes determined Timer overflow rate. Using Timer Generate Baud Rates. When Timer used baud rate generator, baud rates Modes determined Timer overflow rate value SMOD follows (see: Mode Baud Rate (2SMOD (Timer overflow rate) Timer Interrupt should disabled this application. Timer itself configured either "timer" "counter" operation, running modes. most typical applications, configured "timer" operation, Auto-reload Mode (high nibble TMOD 0010B). that case baud rate given formula: Mode Baud Rate (2SMOD (fOSC [256 (TH1)]))
achieve very baud rates with Timer leaving Timer Interrupt enabled, configuring Timer 16-bit timer (high nibble TMOD 0001B), using Timer Interrupt 16-bit software reload. Figure 22., page lists various commonly used baud rates they obtained from Timer Using Timer/Counter Generate Baud Rates. uPSD323X Devices, Timer selected baud rate generator setting TCLK and/or RCLK (see Figure 22., page Timer/ Counter Control Register (T2CON)). Note: baud rate transmit receive simultaneously different. Setting RCLK and/or TCLK puts Timer into Baud Rate Generator Mode. RCLK TCLK Bits T2CON register configure UART RCLK1 TCLK1 Bits PCON register configure UART Baud Rate Generator Mode similar Auto-reload Mode, that roll over causes Timer registers reloaded with 16-bit value registers RCAP2H RCAP2L, which preset software. Now, baud rates Modes determined Timer overflow rate follows: Mode Baud Rate Timer Overflow Rate
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Table Timer 1-Generated Commonly Used Baud Rates
Baud Rate fOSC SMOD Mode Max: 1MHz Mode Max: 375K Modes 62.5K 19.2K 9.6K 4.8K 2.4K 1.2K 137.5 12MHz 12MHz 12MHz 11.059MHz 11.059MHz 11.059MHz 11.059MHz 11.059MHz 11.059MHz 6MHz 12MHz Timer Mode Reload Value FEEBh
timer configured either "timer" "counter" operation. most typical applications, configured "timer" operation (C/T2 "Timer" operation little different Timer when it's being used baud rate generator. Normally, timer would increment every machine cycle (thus clock frequency). case, baud rate given formula: Mode Baud Rate fOSC [65536 (RCAP2H, RCAP2L)] where (RCAP2H, RCAP2L) content RC2H RC2L taken 16-bit unsigned integer. Timer also used Baud Rate Generating Mode. This mode valid only RCLK TCLK T2CON PCON. Note: roll-over does TF2, will generate interrupt. Therefore, Timer Interrupt does have disabled when Timer Baud Rate Generator Mode. Note: EXEN2 set, 1-to-0 transition T2EX will EXF2 will cause reload from (RCAP2H, RCAP2L) (TH2, TL2). Thus when Timer baud rate generator, T2EX used extra external interrupt, desired. should noted that when Timer running (TR2 "timer" function Baud Rate Generator Mode, should READ WRITE TL2. Under these conditions
timer being incremented every state time, results READ WRITE accurate. registers read, should written because WRITE might overlap reload cause WRITE and/or reload errors. Turn timer (clear TR2) before accessing Timer registers, this case. More About Mode Serial data enters exits through RxD. outputs shift clock. bits transmitted/received: data bits (LSB first). baud rate fixed 1/12 fOSC. Figure 27., page shows simplified functional diagram serial port Mode associated timing. Transmission initiated instruction that uses SBUF destination register. "WRITE SBUF" signal S6P2 also loads into position transmit shift register tells Control block commence transmission. internal timing such that full machine cycle will elapse between "WRITE SBUF" activation SEND. SEND enables output shift register alternate out-put function line also enable SHIFT CLOCK alternate output function line TxD. SHIFT CLOCK during every machine cycle, high during S6P2 every machine cycle which SEND active, contents transmit shift shifted right position.
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data bits shift right, zeros come from left. When data byte output position shift register, then that initially loaded into position, just left MSB, positions left that contain zeros. This condition flags Control block last shift then deactivate SEND Both these actions occur S1P1. Both these actions occur S1P1 10th machine cycle after "WRITE SBUF." Reception initiated condition S6P2 next machine cycle, Control unit writes bits 11111110 receive shift register, next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK alternate output function line TxD. SHIFT CLOCK makes transitions S3P1 S6P1 every machine cycle which RECEIVE active, contents receive shift register shifted left position. value that comes from right value that sampled S5P2 same machine cycle. data bits come from right, '1s' shift left. When that initially loaded into right-most position arrives left-most position shift register, flags Control block last shift load SBUF. S1P1 10th machine cycle after WRITE SCON that cleared RECEIVE cleared set. More About Mode bits transmitted (through TxD), received (through RxD): start (0), data bits (LSB first). Stop (1). receive, Stop goes into SCON. uPSD323X Devices baud rate determined Timer Timer over-flow rate. Figure 29., page shows simplified functional diagram serial port Mode associated timings transmit receive. Transmission initiated instruction that uses SBUF destination register. "WRITE SBUF" signal also loads into position transmit shift register flags Control unit that transmission requested. Transmission actually commences S1P1 machine cycle following next rollover divide-by-16 counter. (Thus, times synchronized divide-by-16 counter, "WRITE SBUF" signal.) transmission begins with activation SEND which puts start TxD. time later, DATA activated, which enables output transmit shift register TxD. first shift pulse occurs time after that. data bits shift right, zeros clocked from left. When data byte output position shift register, then that initially loaded into position just left MSB, positions left that contain zeros. This condition flags Control unit last shift then deactivate SEND This occurs 10th divide-by-16 rollover after "WRITE SBUF." Reception initiated detected 1-to-0 transition RxD. this purpose sampled rate times whatever baud rate been established. When transition detected, divide-by-16 counter immediately reset, 1FFH written into input shift register. Resetting divide-by-16 counter aligns roll-overs with boundaries incoming times. states counter divide each time into 16ths. 7th, 8th, counter states each time, detector samples value RxD. value accepted value that seen least samples. This done noise rejection. value accepted during first time '0,' receive circuits reset unit goes back looking an-other 1-to0 transition. This provide rejection false start bits. start proves valid, shifted into input shift register, reception reset rest frame will proceed. data bits come from right, '1s' shift left. When start arrives left-most position shift register (which Mode 9-bit register), flags Control block last shift, load SBUF RB8, signal load SBUF RB8, will generated only following conditions time final shift pulse generated: Either received Stop either these conditions met, received frame irretrievably lost. both conditions met, Stop goes into RB8, data bits into SBUF, activated. this time, whether above conditions not, unit goes back looking 1-to-0 transition RxD.
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More About Modes Eleven bits transmitted (through TxD), received (through RxD): Start (0), data bits (LSB first), programmable data bit, Stop (1). transmit, data (TB8) assigned value '1.' receive, data goes into SCON. baud rate programmable either 1/16 1/32 clock frequency Mode Mode have variable baud rate generated from Timer Figure 31., page Figure 33., page show functional diagram serial port Modes receive portion exactly same Mode transmit portion differs from Mode only transmit shift register. Transmission initiated instruction that uses SBUF destination register. "WRITE SBUF" signal also loads into position transmit shift register flags Control unit that transmission requested. Transmission commences S1P1 machine cycle following next roll-over divide-by16 counter. (Thus, times synchronized divide-by-16 counter, "WRITE SBUF" signal.) transmission begins with activation SEND, which puts start TxD. time later, DATA activated, which enables output transmit shift register TxD. first shift pulse occurs time after that. first shift clocks (the Stop Bit) into position shift register. There-after, only zeros clocked Thus, data bits shift right, zeros clocked from left. When out-put position shift register, then Stop just left TB8, positions left that contain zeros. This condition flags Control unit last shift then deactivate SEND This occurs 11th divide-by rollover after "WRITE SUBF." Reception initiated detected 1-to-0 transition RxD. this purpose sampled rate times whatever baud rate been established. When transition detected, divide-by-16 counter immediately reset, 1FFH written input shift register. 7th, 8th, counter states each time, detector samples value R-D. value accepted value that seen least samples. value accepted during first time '0,' receive circuits reset unit goes back looking another 1-to-0 transition. Start proves valid, shifted into input shift register, reception rest frame will proceed. data bits come from right, '1s' shift left. When Start arrives left-most position shift register (which Modes 9-bit register), flags Control block last shift, load SBUF RB8, signal load SBUF RB8, will generated only following conditions time final shift pulse generated: Either received data either these conditions met, received frame irretrievably lost, set. both conditions met, received data goes into RB8, first data bits into SBUF. time later, whether above conditions were not, unit goes back looking 1-to-0 transition input.
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Figure Serial Port Mode Block Diagram
Internal Write SBUF
SBUF
P3.0 Output Function
Zero Detector
Start Control Serial Port Interrupt Clock Start Clock
Shift Send
Shift Clock Receive Shift Control P3.0 Input Function Shift SBUF Read SBUF Internal
P3.1 Output Function
Input Shift Register Load SBUF
AI06824
Figure Serial Port Mode Waveforms
Write SBUF Send Shift (Data Out) (Shift Clock) Write SCON Receive Shift (Data (Shift Clock)
Clear
S6P2
S3P1
S6P1
Transmit
Receive
AI06825
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Figure Serial Port Mode Block Diagram
Timer1 Overflow Timer2 Overflow Write SBUF SMOD TCLK Serial Port Interrupt Sample 1-to-0 Transition Detector Clock Start Control 1FFh Load SBUF Shift Start Control Clock Shift Data Send Internal
SBUF
Zero Detector
RCLK
Detector Input Shift Register Load SBUF SBUF Read SBUF Internal
AI06826
Shift
Figure Serial Port Mode Waveforms
Clock Write SBUF Send Data Shift Clock Detector Sample Times Shift
Start Stop S1P1
Transmit
Reset Start Stop
Receive
AI06843
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Figure Serial Port Mode Block Diagram
Phase2 Clock 1/2*fOSC Write SBUF SMOD Start Control Serial Port Interrupt Sample 1-to-0 Transition Detector Clock Start Control 1FFh Load SBUF Shift Clock Shift Data Send Internal
SBUF
Zero Detector
Detector Input Shift Register Load SBUF SBUF Read SBUF Internal
AI06844
Shift
Figure Serial Port Mode Waveforms
Clock Write SBUF Send Data Shift Stop Generator Clock Detector Sample Times Shift
Start Stop S1P1
Transmit
Reset Start Stop
Receive
AI06845
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Figure Serial Port Mode Block Diagram
Timer1 Overflow Timer2 Overflow Write SBUF SMOD TCLK Serial Port Interrupt Sample 1-to-0 Transition Detector Clock Start Control 1FFh Load SBUF Shift Start Control Clock Shift Data Send Internal
SBUF
Zero Detector
RCLK
Detector Input Shift Register Load SBUF SBUF Read SBUF Internal
AI06846
Shift
Figure Serial Port Mode Waveforms
Clock Write SBUF Send Data Shift Stop Generator Clock Detector Sample Times Shift
Start Stop S1P1
Transmit
Reset Start Stop
Receive
AI06847
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ANALOG-TO-DIGITAL CONVERTOR (ADC)
analog digital (A/D) converter allows conversion analog input corresponding 8-bit digital value. module four analog inputs, which multiplexed into sample hold. output sample hold input into converter, which generates result successive approximation. analog supply voltage connected AVREF ladder resistance module. module registers which control register ACON result register ADAT. register ACON, shown Table 47., page controls operation converter module. analog inputs, selected P1SFS register. Also 8-bit prescaler ASCL divides main system clock input down approximately 6MHz clock that required logic. Appropriate values need loaded into prescaler based upon main clock frequency prior use. processing conversion starts when Start ADST '1.' After cycle, cleared hardware. register ADAT contains results conversion. When conversion completed, result loaded into ADAT Conversion Status ADSF '1.' block diagram module shown Figure Status ADSF automatically when conversion completed, cleared when conversion process. ASCL should loaded with value that results clock rate approximately 6MHz using following formula: clock input (fOSC (Prescaler register value Where fOSC clock input frequency conversion time calculated follows: Conversion Time clock 8bits (ADC Clock) 10.67usec 6MHz) Interrupt ADSF ACON register when conversion complete. status driven MCU, configured generate falling edge interrupt when conversion complete. ADSF Interrupt enabled setting ADSFINT PCON register. Once set, external INT1 Interrupt disabled ADSF Interrupt takes over INT1. INT1 must configured edge interrupt input. INP1 (p3.3) available general functions, Timer1 gate control.
Figure Block Diagram
AVREF
Ladder Resistor
Decode
ACH0 ACH1 ACH2 ACH3
Input
Successive Approximation Circuit
Conversion Complete Interrupt
ACON
ADAT
INTERNAL
AI06627
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Table Memory
Addr Name Register Name Reset Comments Value 8-bit Prescaler clock Data Register Control Register
ASCL
ADAT ACON
ADAT7
ADAT6
ADAT5 ADEN
ADAT4
ADAT3 ADS1
ADAT2 ADS0
ADAT1 ADST
ADAT0 ADSF
Table Description ACON Bits
Symbol ADEN Reserved Enable Bit: shut consumes operating current enable Reserved Function
ADS1, ADS0 Analog channel select Channel0 Channel1 Channel2 Channel3 (ACH0) (ACH1) (ACH2) (ACH3) force zero start ADC; after cycle, cleared conversion process conversion completed, process
ADST ADSF
Start Bit: Status Bit:
Table Clock Input
Clock Frequency 40MHz 36MHz 24MHz 12MHz Prescaler Register Value Clock 6.7MHz 6MHz 6MHz 6MHz
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PULSE WIDTH MODULATION (PWM)
block following features: Four-channel, 8-bit unit with 16-bit prescaler One-channel, 8-bit unit with programmable frequency pulse width Output with programmable polarity 4-channel Unit (PWM 0-3) 8-bit counter counts module (i.e., from 255, inclusive). value held 8-bit counter compared contents Special Function Register (PWM 0-3) corresponding PWM. polarity outputs programmable selected PWML PWMCON register. Provided contents register greater than counter value, corresponding output HIGH (with PWML When contents this register less than equal counter value, corresponding output (with PWML pulse-width-ratio therefore deFigure Four-Channel 8-bit Block Diagram
DATA
fined contents corresponding Special Function Register (PWM 0-3) PWM. loading corresponding Special Function Register (PWM 0-3) with either FFH, output retained constant HIGH level respectively (with PWML each unit, there 16-bit Prescaler that used divide main system clock form input clock corresponding unit. This prescaler used define desired repetition rate unit. registers used hold 16-bit divisor values. repetition frequency output given fPWM8 (fOSC prescaler0) 256) input clock frequency counters fOSC (prescaler data value PORTS (MCU MODULE), page more information configure Port output.
rd/wr
8-bit PWM0-PWM3 Data Registers
rd/wr
16-bit Prescaler Register (B2h,B1h)
fOSC/2
16-bit Prescaler Counter clock load
load 8-bit PWM0-PWM3 Comparators Registers
Port4.3 Port4.4 Port4.5 Port4.6
8-bit PWM0-PWM3 Comparators
8-bit Counter Overflow
PWMCON bit7 (PWML)
PWMCON bit5 (PWME)
AI06647
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Table Memory
Name Addr Register Name PWML PWMP PWME CFG4 CFG3 CFG2 CFG1 CFG0 Reset Value Comment Control Polarity PWM0 Output Duty Cycle PWM1 Output Duty Cycle PWM2 Output Duty Cycle PWM3 Output Duty Cycle Period Pulse Width Prescaler (8-bit) Prescaler High (8-bit) Prescaler (8-bit) Prescaler High (8-bit)
PWMCON
PWM0
PWM1
PWM2
PWM3
PWM4P
PWM4W
PSCL0L PSCL0H PSCL1L PSCL1H
PWMCON Register Definition: PWML polarity control PWMP polarity control PWME enable disabled, enabled)
CFG3.CFG0 Output Open Drain; Push-Pull) CFG4 Output Open Drain; Push-Pull)
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Programmable Period 8-bit channel programmed provide output with variable pulse width period. 16-bit Prescaler, 8bit Counter, Pulse Width Register, Period Register. Pulse Width Register defines
pulse width time, while Period Register defines period PWM. input clock Prescaler fOSC/2. channel assigned Port 4.7.
Figure Programmable Channel Block Diagram
DATA
RD/WR
8-bit PWM4P Register (Period)
8-bit PWM4W Register (Width)
RD/WR
16-bit Prescaler Register (B4h, B3h)
8-bit PWM4 Comparator Register PWM4 Control
8-bit PWM4 Comparator Register
Load
Port
fOSC 16-bit Prescaler Counter Load PWMCON (PWME) 8-bit Counter Clock Reset
AI07091
8-bit PWM4 Comparator
Match
8-bit PWM4 Comparator
PWMCON (PWMP)
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Channel Operation 16-bit Prescaler1 divides input clock (fOSC/2) desired frequency, resulting clock runs 8-bit Counter channel. input clock frequency Counter PWM4 (fOSC/2)/(Prescaler1 data value When Prescaler1 Register (B4h, B3h) data value '0,' maximum input clock frequency Counter fOSC/2 high 20MHz. Counter free-running, 8-bit counter. output counter compared Compare Registers, which loaded with data from Pulse Width Register (PWM4W, ABh) Period Register (PWM4P, AAh). Pulse Width Register defines pulse duration Pulse Width, while Period Register defines period PWM. When channel enabled, register values loaded into Comparator Registers compared
Counter output. When content counter equal greater than value Pulse Width Register, sets output (with PWMP When Period Register equals PWM4 Counter, Counter cleared, channel output logic 'high' level (beginning next pulse). Period Register cannot have value "00" content should always greater than Pulse Width Register. Prescaler1 Register, Pulse Width Register, Period Register modified while channel active. values these registers automatically loaded into Prescaler Counter Comparator Registers when current period ends. PWMCON Register (Bits controls enable/disable polarity channel.
Figure With Programmable Pulse Width Frequency
Defined Period Register
PWM4
Defined Pulse Width Register
Switch Level
RESET Counter
AI07090
70/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
INTERFACE
There serial ports implemented uPSD323X Devices. serial port supports twin line I2C-bus, consists data line (SDAx) clock line (SCLx). Depending configuration, lines require pull-up resistors. SDA1, SCL1: serial port line Protocol SDA2, SCL2: serial port line general connection both interfaces, these lines also function port lines follows. SDA1 P4.0, SCL1 P4.1, SDA2 P3.6, SCL2 P3.7 system unique because data transport, clock generation, address recognition control arbitration controlled hardware. Figure Block Diagram Serial serial complete autonomy byte handling operates modes. Master transmitter Master receiver Slave transmitter Slave receiver These functions controlled SFRs. SxCON: control byte handling operation mode. SxSTA: contents register also used vector various service routines. SxDAT: data shift register. SxADR: slave address register. Slave address recognition performed On-Chip H/W.
Slave Address SDAx Shift Register Arbitration Sync. Logic
Internal
SCLx
Clock Generator Control Register Status Register
AI06649
Table Serial Control Register (SxCON: S1CON, S2CON)
ENII ADDR
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Table Description SxCON Bits
Symbol ENII Function This along with Bits CR1and determines serial clock frequency when Master Mode. Enable IIC. When ENI1 disabled. outputs high impedance state. START flag. When this set, checks status I2C-bus generates START condition free. busy, will generate repeated START condition when this set. STOP flag. With this while Master Mode STOP condition generated. When STOP condition detected I2C-bus, hardware clears flag. Note: This have before cycle interrupt period STOP. That this set, STOP condition Master Mode generated after cycle interrupt period. This when address byte received. Must cleared software. Acknowledge enable signal. this set, acknowledge (low level SDA) returned during acknowledge clock pulse line when: slave address received data byte received while device programmed Master Receiver data byte received while device selected Slave Receiver. When this reset, acknowledge returned. release line high during acknowledge clock pulse. These bits along with determine serial clock frequency when Master Mode.
ADDR
Table Selection Serial Clock Frequency Master Mode
fOSC Divisor 12MHz 12.5 6.25 Rate (kHz) fOSC 24MHz 12.5 36MHz 37.5 18.75 40MHz
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Serial Status Register (SxSTA: S1STA, S2STA) SxSTA "Read-only" register. contents this register used vector service routine. This optimized response time software consequently that I2C-bus. status codes possible modes I2Cbus interface given Table This flag set, interrupt generated, after following events occur. slave address been received during ack_int general call address been received while GC(SxADR.0) Table Serial Status Register (SxSTA)
STOP INTR TX_MODE BBUSY BLOST /ACK_REP
data byte been received transmitted Master Mode (even arbitration lost): ack_int data byte been received transmitted selected slave: ack_int stop condition received selected slave receiver transmitter: stop_int Data Shift Register (SxDAT: S1DAT, S2DAT) SxDAT contains serial data transmitted data which just been received. (Bit transmitted received first; that data shifted from right left.
Table Description SxSTA Bits
Symbol STOP INTR(1,2) TX_MODE BBUSY BLOST General Call Flag Stop Flag. This when STOP condition received Interrupt Flag. This when Interrupt condition requested Transmission Mode Flag. This when transmitter; otherwise this reset Busy Flag. This when being used another master; otherwise, this reset Lost Flag. This when master loses contention; otherwise this reset Acknowledge Response Flag. This when receiver transmits acknowledge signal This reset when receiver transmits acknowledge signal Slave Mode Flag. This when plays role Slave Mode; otherwise this reset Function
/ACK_REP
Note: Interrupt Flag (INTR, SxSTA cleared Hardware reading SxSTA register. Interrupt Flag (INTR) occur below case. (except DDC2B Mode SWENB=0)
Table Data Shift Register (SxDAT: S1DAT, S2DAT)
SxDAT7 SxDAT6 SxDAT5 SxDAT4 SxDAT3 SxDAT2 SxDAT1 SxDAT0
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Address Register (SxADR: S1ADR, S2ADR) This 8-bit register loaded with 7-bit slave address which controller will respond when programmed slave receive/transmitter. Start/Stop Hold Time Detection System Clock registers (Tables included Table Address Register (SxADR)
SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0
unit specify start/stop detection time work with large range frequency values supported. example, with system clock 40MHz.
Note: SLA6 SLA0: slave address.
Table Start /Stop Hold Time Detection Register (S1SETUP, S2SETUP)
Address S2SETUP control start/stop hold time detection multi-master module Slave Mode Register Name S1SETUP Reset Value Note control start/stop hold time detection module Slave Mode
Table System Cock 40MHz
S1SETUP, S2SETUP Register Value Number Sample Clock (fOSC/2 50ns) 12EA 128EA Required Start/ Stop Hold Time 50ns 50ns 100ns 150ns 600ns 6000ns Fast Mode Start/Stop hold time specification Note When (enable bit) number sample clock (ignore
Table System Clock Setup Examples
System Clock 40MHz (fOSC/2 50ns) 30MHz (fOSC/2 66.6ns) 20MHz (fOSC/2 100ns) 8MHz (fOSC/2 250ns) S1SETUP, S2SETUP Register Value Number Sample Clock Required Start/Stop Hold Time 600ns 600ns 600ns 750ns
74/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
INTERFACE
basic unit consists interface bytes SRAM data storage. 8032 core responsible loading contents SRAM with data. unit following features: Supports both DDC1 DDC2b Modes. Features bytes data initialized 8032 Supports fully automatic operation DDC1 DDC2b Modes operates Slave Mode only. Interrupt Mode available (existing design) interface signals mapped pins Port interface consists standard VSYNC (P4.2), (P4.0) (P4.1) signals. conceptual block diagram illustrated Figure
Figure Interface Block Diagram
DDC2B/DDC2AB DDC2B+Interface
Monitor Address S1ADR0 Monitor Address S1ADR1
SDA1 S1DAT Arbitration Logic SCL1
Shift Register
Clock Generator
Internal
SICON
RAMBUF
SISTA DDC1/DDC2 Detection
DDC1 Hold Register DDCDAT DDC1 Transmitter
Buffer
VSYNCEN Address Pointer Initialization Synchronization DDCADR
DDC1 DDC1
INTR (from SISTA)
DDCCON
AI06628
75/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Special Function Register Interface There eight interface: RAMBUF, DDCCON, DDCADR, DDCDAT registers. S1CON, S1STA, S1DAT, S1ADR Interface registers, same ones described standalone bus. DDCDAT Register. DDC1 DATA register transmission (DDCDAT: 0D5H) 8-bit READ WRITE register. Indicates DATA BYTE transmitted DDC1 protocol. Table Memory
Addr Name Register Name Reset Comments Value EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT Buffer Data xmit register Addr pointer register Control Register
DDCADR Register. Address pointer interface (DDCADR: 0D6H) 8-bit READ WRITE register. Address pointer with capability post increment. After each access RAMBUF register (either software hardware DDC1 interface), content this register will increased one. It's available both DDC1, DDC2 (DDC2B, DDC2B+, DDC2AB) system operation.
RAMBUF DDCDAT
DDCADR DDCCON
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Table Description DDCON Register Bits
Symbol EX_DAT Reserved SRAM bytes (Default) SRAM bytes Note: This valid DDC1 DDC2b Modes Data automatically read from SRAM current location DDCADR sent current protocol. (Default) interrupted during current data byte transmission period load next byte data send out. Note: This valid DDC1 DDC2b Modes Data automatically read from SRAM current location DDCADR sent current protocol. (Default) interrupted during current data byte transmission period load next byte data send out. This only affects DDC2b Mode Operation: DDC2b Address A0/A1 (default) DDC2b Address Least significant address bits ignored. DDC1 Mode Operation Only: DDC1 Interrupt DDC1 Interrupt request. should cleared interrupt service routine. Note1: This VCLK DDC1 Enable Mode. (SWENB=1) DDC1 Mode disabled VSYNC ignored. unit will still respond DDC2b requests. -provided enabled.(Default) DDC1 Mode enabled. hardware when unit switches from DDC1 DDC2b Modes. interrupt request. Switch DDC2b Mode (Interrupt pending) should cleared interrupt service routine. Note1: This connection with SWENB. Current Mode Indication Bit: Unit DDC1 Mode Unit DDC2b Mode Note: When unit transitions DDC2b Mode, unit will stay DDC2b Mode until unit disabled, system reset. Function
SWENB
DDC_AX
DDC1_Int
DDC1EN
SWHINT
Mode
77/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Table SWNEB Function
DDC1 DDC2b Mode Disabled SWENB DDCCON.bit2 (DDC1 Mode Disable) S1CON.bit6 (I2C Mode Disable) this state, unit disabled. SRAM cannot accessed MCU. interrupt activity will occur. cannot access internal SRAM: SRAM address space re-assigned external data space. this state, unit disabled, with SWENB=1, access SRAM. This state used load SRAM with correct data automatic modes. interrupt activity will occur. access SRAM: data space FF00hFFFFh dedicated SRAM. DDC1 DDC2b Mode Enabled DDCCON.bit2 (DDC1 Mode Enable) S1CON.bit6 (I2C Mode Enable) this state, enabled unit automatic mode. SRAM cannot accessed only unit access. cannot access internal SRAM: data space FF00h-FFFFh dedicated SRAM. this state, SRAM accessed MCU. unit does SRAM when SWENB=1. Since unit manual mode, unit generates interrupt each byte transferred. byte transferred held S1DAT register. access SRAM.
78/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Host Type Detection detection procedure conforms sequences proposed VESA Monitor Display Data Channel (DDC) specification. monitor needs determine type host system: Figure Host Type Detection
DDC1 type host. DDC2B host (Host master, monitor always slave) DDC2B+/DDC2AB(ACCESS.bus) host.
Power
Communication isidle
VSYNC present?
EDID sent continously using VSYNC clock
DDC2 clock present?
Stop sending EDID switch DDC2 communication mode
DDC2 communication idle.
command been received?
2B+/A.B command detected? DDC2B command?
DDC2B+/DDC2AB?
Respond DDC2B command
Respond DDC2B+/ DDC2AB command
AI06644
79/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
DDC1 Protocol DDC1 primitive point point interface. monitor always "Transmit only" mode. initialization phase, clock cycles VCLK will given internal synchronization. During this period, will kept high impedance state. DDC1 hardware mode used, following procedure recommended proceed DDC1 operation. Reset DDC1 enable default, DDC1 enable cleared after Power-on Reset). SWENB high (the default value zero.) Depending data size EDID data, EX_DAT (128 bytes) HIGH (256 bytes). using bulky moving commands (DDCADR, RAMBUF involved) move entire EDID data buffer. Reset SWENB LOW. Reset DDCADR 00h. DDC1 enable HIGH. case SWENB high, interrupt service routine finished within machine cycle 40MHz System clock.
maximum VSYNC (VCLK) frequency 25Khz (40µs). clock VSYNC (VCLK) interrupt period. machine cycle needed calculated below. example, When 40MHz system clock, 40µs (25ns 12); machine cycle. 12MHz system clock, 40µs (83.3ns 12); machine cycle. 8MHz system clock, 40µs (125ns 12); machine cycle. Note: EX_DAT equals LOW, meant lower part occupied DDC1 operation upper part still free system. Nevertheless, effect post increment just applies part related DDC1 operation. other words, system program still able address locations from buffer through MOVX command without facility post increment. example, case accessing Buffer: #200, MOVX
Figure Transmission Protocol DDC1 Interface
Max=40us VCLK DDC1INT DDC1EN Hi-Z
tSU(DDC1)
H(VCLK)
L(VCLK)
AI06652
80/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
DDC2B Protocol DDC2B constructed based Philips interface. However, level DDC2B, host fixed master monitor always regarded slave. Both master slave operated transmitter receiver, master device determines which mode activated. this protocol, address pointer also used. According DDC2B specification, (for WRITE Mode) (for READ Mode) assigned default address monitors.
reception incoming data WRITE Mode updating outgoing data READ Mode should finished within specified time limit. software slave's side cannot react master time, based protocol, stretched inhibit further action from master. transaction proceeded either byte burst format.
Figure Conceptual Structure Interface
Interrupt vector address 0023H
Check Mode flag DDCCON Mode Mode Mode DDC2B/DDC2AB command received SWENB DDC2B/DDC2AB Utilities DDC2B SWENB DDC2B Utilities SWENB DDC1.DDC2B Utilities
ServiceRoutines
Transmitter (H/W)
interface (H/W)
AI06645
81/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
HARDWARE
characteristics hardware follows: Complies with Universal Serial specification Rev. Integrated (Serial Interface Engine), FIFO memory transceiver speed (1.5Mbit/s) device capability Supports control endpoint0 interrupt endpoint1 clock input must 6MHz (requires clock frequency 36MHz). analog front-end on-chip generic transceiver. designed allow voltage levels equal from standard logic interface with physical layer Universal Serial Bus. capable receiving transmitting serial data speed (1.5Mb/s). digital-front-end block. This module recovers 1.5MHz clock, detects sync word handles low-level protocols error checking. bit-clock recovery circuit recovers clock from incoming Table Address Register (UADR: 0EEh)
USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
data stream able track jitter frequency drift according specification. also translates electrical signals into bytes signals. Depending upon device address endpoint. Address, data directed correct endpoint interface. data transfer this could type control interrupt. device's address enabling endpoints programmable configuration header. related registers block controlled seven reg
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