Performs framing monitoring functions Supports Superframe Extended Sup

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Performs framing monitoring functions Supports Superframe Extended Sup

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DS2182A Line Monitor
Performs framing monitoring functions Supports Superframe Extended Superframe formats Four onboard error counters 16-bit bipolar violation 8-bit 8-bit 8-bit frame error Indication following yellow blue alarms incoming B8ZS code words zero strings change frame alignment loss sync carrier loss Simple serial interface used configuration, control status monitoring Burst mode allows quick access counters status updates Automatic counter reset feature Single supply; low-power CMOS technology Available 28-pin 28-pin PLCC DS2182A upward-compatible from original DS2182
updated DS2182A includes following changes from original DS2182: Ability count excessive zeros Severely Errored Framing Event indication Updated detection Updated detection alarm clear indications
ASSIGNMENT
SCLK RYEL RLINK RLCLK RCLK RCHCLK RSER RLOS RFER RNEG RPOS TEST RSIGSEL RSIGFR RABCD RMSYNC RFSYNC
28-Pin (600-mil)
DESCRIPTION
DS2182A Line Monitor Chip monolithic CMOS device designed monitor real-time performance lines. DS2182A frames data line, counts errors, supplies detailed information about status condition line. Large on-board counters allow accumulation errors extended periods, which permits single monitor number lines. Output clocks that synchronized incoming data stream provided easy extraction S-Bits, bits, signaling bits, channel data. DS2182A meets requirements ANSI T1.231.
092299
DS2182A
DS2182A BLOCK DIAGRAM Figure
DS2182A
DESCRIPTION Table
SYMBOL RYEL RLINK TYPE DESCRIPTION Connect. internal connection. This tied either VDD, floated. Receive Yellow Alarm. Transitions high when yellow alarm detected; goes when alarm clears. Receive Link Data. Updated with extracted data RCLK before start frames (193E) held until next update. Updated with extracted S-bit data RCLK before start even frames (193S) held until next update. Receive Link Clock. demand clock RLINK. Receive Clock. 1.544 primary clock. Receive Channel Clock. clock; identifies time slot (channel) boundaries. Receive Serial Data. Received serial data; updated rising edges RCLK. Connect. internal connection. This tied either VDD, floated. Receive Frame Sync. Extracted clock, RCLK wide; Fbit position each frame. Receive Multiframe Sync. Extracted multiframe sync; positivegoing edge indicates start multiframe; duty cycle. Receive ABCD Signaling. Extracted signaling data output; valid each channel signaling frames. non-signaling frames, RABCD outputs each channel word. Receive Signaling Frame. High during signaling frames; during non-signaling frames (and during resync). Receive Signaling Select. 193E framing, .667 clock that identifies signaling frames 1.33 clock 193S. Reset. high-low transition clears internal registers resets counters. high-low-high transition initiates resync. Receive Bipolar Data Inputs. Sampled falling RCLK. together receive data disable bipolar violation monitoring circuitry. Receive Carrier Loss. High consecutive appear RPOS RNEG; goes upon seeing 12.5% one's density. Receive Bipolar Violation. High during accused time RSER. bipolar violation detected, otherwise. Receive Frame Error. High during F-bit time when errors occur (193S), when errors occur (193E). during resync. Receive Loss Sync. Indicates sync status; high when internal resync progress, otherwise.
RLCLK RCLK RCHCLK RSER RFSYNC RMSYNC RABCD
ESIGFR RSIGSEL
RPOS RNEG RFER
RLOS
DS2182A
DESCRIPTION Table
SYMBOL
TYPE
DESCRIPTION
Receive Alarm Interrupt. Flags host controller during alarm conditions. Active low; open drain output. Serial Data Data onboard registers. Sampled rising edge SCLK. Serial Data Out. Control status information from onboard registers. Updated falling edge SCLK; tri-stated during serial port write when high. Chip Select. Must read write serial port. Serial Data Clock. Used read write serial port registers.
SCLK
POWER TEST DESCRIPTION Table
SYMBOL
TEST
TYPE
DESCRIPTION
Signal Ground. volts. Test Mode. normal operation. Positive Supply. volts.
REGISTER SUMMARY Table
REGISTER
BVCR2 BVCR1 CRCCR OOFCR FECR RSR1 RIMR1 RSR2 RIMR2 RCR1 RCR2
ADDRESS
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
DESCRIPTION/FUNCTION
Bipolar Violation Count Register 16-bit presettable counter that records individual bipolar violations. Bipolar Violation Count Register 16-bit presettable counter that records individual bipolar violations. Error Count Register. 8-bit presettable counter that records CRC6 errored words 193E frame mode. Count Register. 8-bit presettable counter that records events. events defined RCR1.5 RCR1.6. Frame Error Count Register. 8-bit presettable counter that records individual errors framing pattern. Receive Status Register Reports alarm conditions. Receive Interrupt Mask Register Allows masking individual alarmgenerated interrupts from RSR1. Receive Status Register Reports alarm conditions. Receive Interrupt Mask Register Allows masking individual alarmgenerated interrupts from RSR2. Receive Control Register Programs device operating characteristics. Receive Control Register Programs device operating characteristics.
SERIAL PORT INTERFACE
port pins DS2182A serve microprocessor/ microcontroller-compatible serial port. Eleven on-board registers allow user update operational characteristics monitor device status host controller, minimizing hardware interfaces. port DS2182A read from written time. Serial port reads writes independent line timing signals RCLK, RPOS, RNEG. However, RCLK needed order clear RSR1 RSR2 after reads.
ADDRESS/COMMAND
Reading writing control, configuration status registers requires writing address/command byte prior transferring register data. first written (LSB) address/command word specifies
DS2182A
register read write. following bits identify register address. next bits reserved must proper operation. last address/ command word enables burst mode when set; burst mode causes registers consecutively read written Data read written DS2182A first.
CHIP SELECT CLOCK CONTROL
data transfers initiated driving input low. Input data latched rising edge SCLK must valid during previous period SCLK prevent momentary corruption register data during writes. Data output falling edge SCLK held next falling edge. data transfers terminated input transitions high. Port control logic disabled tri-stated when high.
DATA
Following eight SCLK cycles that input address/command byte write, data byte strobed into addressed register rising edge next eight SCLK cycles. Following address/command word read, contents selected register output falling edges next eight SCLK cycles. tri-stated during device write tied applications where host processor bi-directional pin.
BURST MODE
burst mode allows onboard registers consecutively written read host processor. burst read used poll registers; RSR1 RSR2 contents will unaffected. This feature minimizes device initialization time system power-up reset. Burst mode initiated when ACB.7 address 0000. burst terminated low-high transition
ACB: ADDRESS COMMAND BYTE Figure
ADD3 ADD2 ADD1 ADD0
SYMBOL
ADD3 ADD0
POSITION
ACB.7 ACB.6 ACB.5 ACB.4 ACB.1 ACB.0
NAME DESCRIPTION
Burst Mode. (and register address 0000) burst read write enabled. Reserved, must operation. Reserved, must operation. register address. register address. Read/Write Select. write addressed register read addressed register
DS2182A
SERIAL PORT READ/WRITE Figure
NOTES:
sampled rising edge SCLK. updated falling edge SCLK.
OPERATION COUNTERS
four counters DS2182A preset user establish event count interrupt threshold. counters count from preset value until they reach saturation. saturation, each additional event occurrence sets appropriate RSR2 generates interrupt enabled RIMR2. DS2182A contains auto counter reset feature burst read mode. RCR1.4 set, then user burst read four counters (five registers), four counters will automatically reset after read takes place. Since burst mode terminated time taking high, user option reading registers only counters. RCR1.4 set, then read registers, burst mode not, will clear count four counters. user wishes read port clear counters, then RCR1.4 must cleared first. counter registers read written time with serial port, which operates totally asynchronously with monitoring line. Reading register will affect count long RCR1.4 cleared. dual buffer architecture DS2182A insures that error events will missed while serial port being accessed reads.
BVCR1: BIPOLAR VIOLATION COUNT REGISTER BVCR2: BIPOLAR VIOLATION COUNTER REGISTER Figure
SYMBOL
POSITION
BVCR.7 BVCR.0
NAME DESCRIPTION
bipolar violation count bipolar violation count
Bipolar Violation Count Register (BVCR1) most significant word BVCR2 least significant word presettable 16-bit counter that records individual bipolar violations. B8ZS mode enabled (RCR2.2 then B8ZS code words counted. BVCR also programmed count excessive zeros setting RCR2.5 bit. this mode, BVCR will count
DS2182A
occurrences consecutive zeros when B8ZS enabled consecutive zeros when B8Z5 disabled. This counter increments times disabled loss sync condition (RLOS counter saturates 65,535 generates interrupt each occurrence after saturation RIMR2.0 set.
NOTE:
order properly preset Bipolar Violation Count Register, BVCR2 must written before BVCR1 written
CRCCR: COUNT REGISTER Figure
CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1
CRC0
SYMBOL
CRC7 CRC0
POSITION
CRCCR.7 CRCCR.0
NAME DESCRIPTION
CRC6 word error count CRC6 word error count
Count Register (CRCCR) 8-bit presettable counter that records word errors Cyclic Redundancy Check (CRC). This 8-bit binary counter saturates generates interrupt each occurrence after saturation RIMR2.1 set. count this register only valid 193E framing mode (RCR2.4 reset disabled 193S framing mode (RCR2.4 count disabled during loss sync condition (RLOS
OOFCR: COUNT REGISTER Figure
OOF7 OOF6 OOF5 OOF4 OOF3 OOF2 OOF1
OOF0
SYMBOL
OOF7 OFF0
POSITION
OOFCR.7 OOFCR.0
NAME DESCRIPTION
event count event count
Count Register (OOFCR) 8-bit presettable counter that records Frame (OOF) events. events defined RCR1.5 RCR1.6. This 8-bit counter saturates generates interrupt each occurrence after saturation RIMR2.2 set. count disabled during loss sync condition (RLOS
DS2182A
FECR: FRAME ERROR COUNT REGISTER Figure
SYMBOL
FFE0
POSITION
FECR.7 FECR.0
NAME DESCRIPTION
frame error count frame error count
Frame Error Count Register (FECR) 8-bit pre-settable counter that records individual frame errors. 193E mode (RCR2.4 FECR records errors framing pattern (001011). 193S mode (RCR2.4 FECR records errors both (101010) (001110) framing patterns RCR1.3 set. RCR1.3 cleared, then FECR only records errors pattern. This 8-bit counter saturates generates interrupt each occurrence after saturation RIMR2.3 set. count disabled during loss sync condition (RLOS
RSR1: RECEIVE STATUS REGISTER Figure
16ZD RYEL RLOS B8ZSD
COFA
SYMBOL
16ZD
POSITION
RSR1.7 RSR1.6 RSR1.5
NAME DESCRIPTION
Zero Detect. when string eight consecutive been received RPOS RNEG. Zero Detect. when string consecutive been received RPOS RNEG. Receive Carrier Loss. when string consecutive been received RPOS RNEG. Cleared when more ones possible positions received. Receive Yellow Alarm. when yellow alarm detected. format yellow alarm determined RCR2.3 RCR2.4. Receive Loss Sync. when resync progress. B8ZS Code Word Detect. when B8ZS code word received RPOS RNEG independent whether B8ZS mode enabled (RCR2.2). Receive Blue Alarm. when over window, less zeros received. Cleared when over window, more zeros received. Change Frame Alignment. when last resync resulted change frame multiframe alignment.
RYEL
RSR1.4
RLOS B8ZSD
RSR1.3 RSR1.2
RSR1.1
COFA
RSR1.0
NOTE:
Alarm 16ZD cleared next occurrence RPOS RNEG.
DS2182A
RECEIVE STATUS REGISTERS
receive status registers (RSR1 RSR2) used either polled interrupt configuration. polled configuration, user reads regular intervals check alarms. interrupt configuration, user monitors pin. When goes low, alarm condition occurred been reported RSRs. processor then read RSRs find which bits have been set. bits RSRs operate latched fashion. That once set, they remain until read. bits cleared when read unless read performed burst mode alarm condition still exists.
YELLOW ALARM
193S RCR2.4 RCR2.3 then DS2182A examines incoming channels presence yellow alarm. consecutive channels, then reception yellow alarm declared. alarm considered cleared when first channel with received. 193S S-BIT. RCR2.4 RCR2.3 then DS2182A examines S-bit position frame presence yellow alarm. DS2182A declares presence yellow alarm first occurrence S-bit frame being alarm considered cleared when this S-bit returns 193E FDL. RCR2.4 then DS2182A examines repeating 00FF pattern. this pattern received consecutive times without error, then yellow alarm declared. alarm considered cleared soon pattern other than 00FF received.
DS2182A
RIMR1: RECEIVE INTERRUPT MASK REGISTER Figure
16ZD RYEL RLOS B8ZSD
COFA
SYMBOL
POSITION
RIMR1.7
NAME DESCRIPTION
Zero Detect Mask. interrupt enabled. interrupt masked. Zero Detect Mask. interrupt enabled. interrupt masked. Receive Carrier Loss Mask. interrupt enabled. interrupt masked. Receive Yellow Alarm Mask. interrupt enabled. interrupt masked. Receive Loss Sync Mask. interrupt enabled. interrupt masked. B8ZS Code Word Detect Mask. interrupt enabled. interrupt masked. Receive Blue Alarm Mask. interrupt enabled. interrupt masked. Change Frame Alignment Mask. interrupt enabled. interrupt masked.
16ZD
RIMR1.6
RIMR1.5
RYEL
RIMR1.4
RLOS
RIMR1.3
B8ZSD
RIMR1.2
RIMR1.1
COFA
RIMR1.0
DS2182A
RSR2: RECEIVE STATUS REGISTER Figure
SEFE RCLC RBLC FERR FECS OOFS CRCCS
BPVCS
SYMBOL
SEFE RCLC RBLC FERR FECS OOFCS CRCCS BPVCS
POSITION
RSR2.7 RSR2.6 RSR2.5 RSR2.4 RSR2.3 RSR2.2 RSR2.1 RSR2.0
NAME DESCRIPTION
Severely Errored Framing Event. when framing bits FPS) received error. Receive Carrier Loss Clear. when carrier signal restored; will remain until read. Receive Blue Alarm Clear. when Blue Alarm (AIS) longer detected; will remain until read. Frame Error. when (193S) (193E) errors occur. Frame Error Count Saturation. next frame error event after 8-bit Frame Error Count Register (FECR) saturates 255. Frame Count Saturation. next event after 8-bit Count Register (OOFCR) saturates 255. Count Saturation. next error event after 8-bit Count Register (CRCCR) saturates 255. Bipolar Violation Count Saturation. next error event after 16-bit Bipolar Violation Count Register (BVCR) saturates 65,535.
RIMR2: RECEIVE INTERRUPT MASK REGISTER Figure
SEFE RCLC RBLC FERR FECS OOFS CRCCS
BPVCS
SYMBOL
SEFE
POSITION
RIMR2.7
NAME DESCRIPTION
Severely Errored Framing Event Mask. interrupt masked interrupt enabled Receive Carrier Loss Clear Mask. interrupt masked interrupt enabled Receive Blue Alarm Clear Mask. interrupt masked interrupt enabled
RCLC
RIMR2.6
RBLC
RIMR2.5
DS2182A
SYMBOL
FERR
POSITION
RIMR2.4
NAME DESCRIPTION
Frame Error Mask. interrupt enabled interrupt masked Frame Error Count Saturation Mask. interrupt enabled interrupt masked Frame Count Saturation Mask. interrupt enabled interrupt masked Count Saturation Mask. interrupt enabled interrupt masked Bipolar Violation Count Saturation Mask. interrupt enabled interrupt masked
FECS
RIMR2.3
OOFCS
RIMR2.2
CRCCS
RIMR2.1
BPVCS
RIMR2.0
RCR1: RECEIVE CONTROL REGISTER Figure
OOF1 OOF2 SYNCC SYNCT SYNCE
RESYNC
SYMBOL
POSITION
RCR1.7
NAME DESCRIPTION
Auto Resync Criteria. resync event only resync event Receive Carrier Loss (RCL) Frame event description. Valid when RCR1.5 cleared frame bits FPS) error frame bits FPS) error Frame event description. frame bits FPS) error follow event described RCR1.6 Auto Counter Reset. When set, four counters will reset when read.
OOF1
RCR1.6
OOF2
RCR1.5
RCR1.4
DS2182A
SYMBOL
SYNCC
POSITION
RCR1.3
NAME DESCRIPTION
Sync Criteria. Determines type algorithm utilized receive synchronizer; differs each frame mode. 193S Framing (RCR2.4 synchronize frame boundaries using pattern, then search multiframe using cross couple patterns sync algorithm. 193E Framing (RCR2.4 normal sync (utilizes only). validate alignment with before declaring sync. Sync Time. validate consecutive F-bits before declaring sync. validate consecutive F-bits before declaring sync. Sync Enable. clear, DS2182A automatically begins resync conditions described RCR1.7 met. set, auto resync occurs. Resync. When toggled high, DS2182A initiates resync immediately. must cleared again subsequent resyncs.
SYNCT
RCR1.2
SYNCE
RCR1.1
RESYNC
RCR1.0
SYNCHRONIZER
heart monitor receive synchronizer. This circuit serves purposes: monitors incoming data stream loss frame multiframe alignment, searches frame alignment pattern when sync loss detected. When sync loss detected, synchronizer begins off-line search alignment; output timing signals remain alignment with exception RSIGFR, which forced during resync. When only candidate qualified, output timing moves alignment beginning next multiframe. frame later, RLOS will transition low, indicating valid sync resumption normal sync monitoring mode. Several bits RCR1 allow tailoring resync algorithm user. These bits described below.
SYNC CRITERIA (RCR1.3)
193E. RCR1.3 determines which sync algorithm utilized when resync progress (RLOS 193E framing, when RCR1.3 synchronizer will lock only pattern will move frame multiframe alignment after framing candidate qualified. RLOS will frame after move alignment. When RCR1.3 alignment further tested CRC6 code match. RLOS will transition after CRC6 match occurs. CRC6 match occurs three attempts (three multiframes), algorithm resets search pattern begins. takes synchronizer check first CRC6 code after alignment been loaded. Each additional CRC6 test takes Regardless state RCR1.3, more than candidate exists after synchronizer begins eliminating emulators testing their CRC6 codes order find true framing candidate. 193S. 193S framing, when RCR1.3 synchronizer cross-checks pattern with pattern help eliminate false framing candidates such digital milliwatts. patterns compared repeating pattern .00111000111000.(00111x0 RCR2.3 this mode, must correctly identified synchronizer before sync declared. Clearing RCR1.3 causes synchronizer search pattern (101010.) without cross-coupling pattern. Frame sync
DS2182A
established using information, while multiframe sync established only valid information present. valid pattern identified, synchronizer moves alignment, RLOS goes low, false multiframe position indicated RMSYNC. RFER indicates when received S-bit pattern does match assumed internal multiframe alignment. This mode will used applications where non-standard S-bit patterns exist. such applications, multiframe alignment information decoded externally using S-bits present RLINK.
SYNC TIME (RCR1.2)
RCR1.2 determines number consecutive framing pattern bits qualified before SYNC declared. RCR1.2 algorithm validates bits; RCR1.2 bits validated. Validating bits results superior false framing protection while 10-bit testing minimizes reframe time. either case, synchronizer only establishes resync when only candidate found (see Table
AVERAGE REFRAME TIME Table
FRAME MODE 193S 193E 3.0ms 6.0ms RCR1.2=0 AVG. 3.75ms 7.5ms MAX. 4.5ms 9.0ms MIN. 6.5ms 13.0ms RCR1.2=1 AVG. 7.25ms 14.5ms 8.0ms 16.0ms
NOTE:
Average reframe time defined here average time takes from start resync (rising edge RLOS) actual loading alignment multiframe edge) into output receive timing.
SYNC ENABLE (RCR1.1)
When RCR1.1 cleared, receiver initiates automatic resync event occurs carrier loss (192 consecutive occurs (depends RCR1.7). When RCR1.1 set, automatic resync circuitry disabled. this case, resync only initiated setting RCR1.0 externally transitioning from high. Note that using initiate resync resets output timing while low; RCR1.1 will affect output timing until alignment located.
RESYNC (RCR1.0)
0-to-1 transition RCR1.0 causes synchronizer search framing pattern sequence immediately, regardless internal sync status. order initiate another resync command, this must cleared then again.
DS2182A
RCR2: RECEIVE CONTROL REGISTER Figure
BVCRF SFYEL B8ZS
SYMBOL
BVCRF
POSITION
RCR2.7 RCR2.6 RCR2.5
NAME DESCRIPTION
Reserved; must proper operation. Reserved; must proper operation. Bipolar Violation Count Register Function Select. count excessive count excessive Frame Mode. Extended Superframe (193E, frames Superframe). Superframe (193S frames Superframe). Yellow Mode Select. S-bit position frame channels. Bipolar Eight Zero Substitution. B8ZS enabled. B8ZS disabled. Reserved; must proper operation. Reserved; must proper operation.
RCR2.4
SFYEL
RCR2.3
B8ZS
RCR2.2
RCR2.1 RCR2.10
193S RECEIVE MULTIFRAME TIMING Figure
NOTES:
Signaling data updated during signaling frames channel boundaries. RABCD each channel word non-signaling frames. RLINK data (S-bit) updated bit-time prior S-bit frames held frames.
DS2182A
193E RECEIVE MULTIFRAME TIMING Figure
NOTES:
Signaling data updated during signaling frames channel boundaries. RABCD each channel word non-signaling frames. RLINK data (FDL data) updated bit-time prior frames held frames.
RECEIVE MULTIFRAME BOUNDARY TIMING Figure
NOTES:
RLINK timing shown 193E; 193S, RLINK updated even frame boundaries held across multiframe edges. Total delay from RPOS RNEG RSER output RCLK periods.
DS2182A
ALARM OUTPUTS
transceiver also provides direct alarm outputs applications when additional decoding demuxing required supplement onboard alarm logic.
RLOS OUTPUT
receive loss sync output indicates status receiver synchronizer circuitry; when high, off-line resynchronization progress high-low transition indicates that resync complete. RLOS (RSR1.3) latched version RLOS output. auto-resync mode selected (RCR1.1 RLOS real-time indication carrier loss event occurrence.
RYEL OUTPUT
yellow alarm output transitions high when yellow alarm detected. high-low transition indicates alarm condition been cleared. RYEL (RSR1.4) latched version RYEL output.
OUTPUT
bipolar violation output transitions high when accused emerges RSER. goes next time additional violations detected.
RFER OUTPUT
receive frame error output transitions high F-bit time held high periods when frame error occurs. 193S, framing patterns tested. pattern tested 193E framing. Additionally, 193E framing, RFER reports CRC6 code word errors low-high-low transition period-wide) one-half RCLK period before low-high transition RMSYNC (see Figure 17).
RESET
high-low transition clears registers forces immediate resync when returns high. must held system power-up insure proper initialization counters registers. Following reset, host processor should restore control modes writing appropriate registers with control data.
ALARM OUTPUT TIMING Figure
DS2182A
NOTES:
RFER transitions high during F-bit time received framing pattern error. (Frame F-bits 193S ignored RCR2.3 Also, 193E, RFER transitions high bit-time before rising edge RMSYNC indicate CRC6 error previous multiframe. indicates received bipolar violation transitions high when accused emerges from RSER. B8ZS enabled, will report replacement code. transitions high when consecutive bits transitions upon reception 12.5% ones density. RLOS transitions high during F-bit time that caused event auto-resync enabled (RCR1.1 Resync also occurs when loss carrier detected (RCL RCR1.7 When RCR1.1 RLOS remains until resync occurs, regardless carrier loss flags. this situation, resync initiated only when RCR1.0 transitions low-to-high transitions high-lowhigh.
DS2182A
ABSOLUTE MAXIMUM RATINGS*
Voltage Relative Ground Operating Temperature Storage Temperature Soldering Temperature -0.1V +7.0V 70°C -55°C +125°C 260°C seconds
This stress rating only functional operation device these other conditions above those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods time affect reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER Input Logic Input Logic Supply SYMBOL -0.3 4.50 VCC+0.3 +0.8 5.50
(0°C 70°C)
UNITS NOTES
ELECTRICAL CHARACTERISTICS
PARAMETER Supply Current Input Leakage Output Current (2.4V) Output Current (0.4V) Output Leakage SYMBOL -1.0 -1.0 +4.0 -1.0
(0°C 70°C; 10%)
+1.0 UNITS +1.0 NOTES
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL COUT
(tA=25°C)
UNITS NOTES
NOTES:
RCLK 1.544 MHz. Outputs open. VDD. outputs except which open collector. outputs. Applies when tri-stated.
DS2182A
CHARACTERISTICS
PARAMETER SCLK Setup SCLK Hold
SERIAL PORT
SYMBOL tCHD tCCH tCWH tCDV tCDZ
(0°C 70°C; 10%)
UNITS NOTES
SCLK Falling Edge SCLK Time SCLK High Time SCLK Rise Fall Times
SCLK Setup
SCLK Hold
Inactive Time
SCLK Valid
High
NOTES:
Measured 10ns maximum rise fall time. Output load capacitance
DS2182A
ELECTRICAL CHARACTERISTICS
PARAMETER Propagation delay RCLK RMSYNC, RFSYNC, RSISEL, RSIGFR, RLCLK, RCHCLK Propagation delay RCLK RSER, RABCD, RLINK Transition Time Outputs RCLK Period RCLK Pulse Width RCLK Rise Fall Times RPOS, RNEG Setup RCLK Falling RPOS, RNEG Hold RCLK Falling Propagation delay RCLK RLOS, RYEL, RBV, RCL, RFER Minimum Pulse Width SYMBOL tPRS
RECEIVE (0°C 70°C; 5.0V 10%)
UNITS NOTES
tPRD tTTR tCCH tSRD tHRD tPRA
tRST
NOTES:
Measured 10ns maximum rise fall time. Output load capacitance
DS2182A
SERIAL PORT WRITE TIMING DIAGRAM Figure
NOTES:
Data byte bits must valid across clock periods prevent transients operating modes. Shaded regions indicate "don't care" states input.
SERIAL PORT READ1 TIMING DIAGRAM Figure
NOTES:
Serial port write must precede port read provide address information.
DS2182A
RECEIVE TIMING DIAGRAM Figure
DS2182A
DS2182A LINE MONITOR 28-PIN
INCHES MIN. MAX.
1.445 0.530 0.140 0.600 0.015 0.120 0.090 0.600 0.008 0.015 1.470 0.550 0.160 0.625 0.040 0.145 0.110 0.680 0.012 0.022
DS2182A
DS2182AQ LINE MONITOR 28-PIN PLCC
INCHES MIN. MAX.
0.165 0.180 0.090 0.120 0.020 0.026 0.033 0.013 0.021 0.009 0.012 0.485 0.495 0.450 0.456 0.390 0.430 0.485 0.495 0.450 0.456 0.390 0.430 0.060 0.050 0.042 0.048

Performs framing monitoring functions Supports Superframe Extended Sup

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