Application Note 642: 2001 Analog-to-Digital Converter Captures 1

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Application Note 642: 2001 Analog-to-Digital Converter Captures 1

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CONVERSION/SAMPLING CIRCUITS HIGH-SPEED SIGNAL PROCESSING
Application Note 642: 2001
Analog-to-Digital Converter Captures 1Gsps
industry's first ultra high-speed, 8-bit data converters with highest performance input bandwidth, MAX104/6/8 family data converters offers both sampling speed signal bandwidth applications where these parameters utmost importance. their introduction 1999, this family high-speed analog-to-digital converters (ADCs) standard dynamic performance requirements high-frequency, wide-bandwidth applications. following article outlines advantages this family ADCs describes their impact importance digital communications, DSOs fast data acquisition systems. MAX104 processes analog input bandwidths that exceed 2.2GHz with 8-bit resolution. sets standard performance high-frequency, high-bandwidth digital communications receivers, digital oscilloscopes, high-speed data-acquisition systems. MAX104 fast silicon monolithic analog-to-digital converter (ADC) that integrates highbandwidth track/hold (T/H) amplifier (Figure with high-speed quantizer that supports accurate digitizing wideband analog input signals from 2.2GHz. based Maxim's GST-2 Giga-Speed silicon-bipolar process technology. This high-speed, self-aligned double-polysilicon process been developed high-density, high-performance circuits. employs many features, such trench isolation, that incorporated Maxim's lower performance GST-1 process.
Figure This simplified block diagram shows MAX104 integrates high-bandwidth amplifier with high-speed quantizer. Although many outstanding performance parameters MAX104 possible with integrated-circuit process (such transition frequency 27GHz transistors, three-metal interconnect system, small geometry, precision laser-trimmed nickel-chrome (NiCr) thin-film
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resistors), additional credit goes MAX104's design team creating efficient effective architecture. Most high-speed ADCs that sample more than several hundred megahertz have input bandwidths that limited more than their maximum sampling frequency improve noise performance. example signal-to-noise ratio (SNR). This limited input bandwidth rule applications where bandwidths interest input spectrum higher, undersampling approach needed. Also, input signal changing rapidly during conversion, effective number bits (ENOB) will reduced. MAX104's on-chip 2.2GHz full-power-bandwidth amplifier (Figure increases dynamic performance significantly supports more precise capture fast analog data extremely high conversion rates.
Figure MAX104's full-power bandwidth shown function input amplitude.
Bandgap reference
MAX104 features on-board +2.5V precision bandgap reference, which activated connecting bandgap reference's output contact (REFOUT) in-phase input (REFIN) internal reference amplifier. negative input this amplifier internally tied reference ground (GNDR). REFOUT port provide current 2.5mA external devices. This enough drive MAX104s configured interleaved operation achieve sampling rate gigasamples second, 2Gsps). Since bandgap reference source internally compensated, external bypass components needed with REFOUT connections. overdrive internal reference, external precision reference connected REFIN with REFOUT left floating. external reference then used adjust full-scale range MAX104. MAX104's amplifier input circuit design reduces input signal requirement supports fullscale signal input range 500mV peak-to-peak. Obtaining full-scale digital output with differential input requires 250mV applied between positive (VIN+) negative input (VIN-) pins. Midscale digital output codes occur input zero-scale digital output code, negative input (VIN-) must 250mV above positive input (VIN+). high-performance differential amplifier enables MAX104 used single-ended input configurations without degradation dynamic performance. typical single-ended configuration, analog input signal coupled amplifier stage in-phase input (VIN+), while inverted phase input (VIN-) referenced ground. Single-ended operation supports input amplitude 500mV peak-to-peak, centered approximately minimizing www.maxim-ic.com/an642 Page
reflections improving performance, MAX104 inputs feature impedance-matched, on-chip, lasertrimmed NiCr termination resistors. Demonstrating almost identical dynamic performance analog input frequencies 125MHz (Figure 250MHz, 500MHz (Figure 1GHz (Figure with sampling rate 1Gsps differential single-ended analog input operation, MAX104 solves most perplexing problems highspeed applications-the need costly, space-consuming, single-ended-to-differential signalconversion circuitry. Now, applications requiring single-ended signal sources just feed this signal into VIN+ terminate VIN- through resistor connected ground.
Figure This fast Fourier transform (FFT) demonstrates over-sampled performance MAX104 sampling rate 1Gsps analog input frequency 125MHz.
Figure This taken Nyquist frequency 500MHz sampling rate 1Gsps.
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Figure This measured with MAX104 undersampling analog input frequency 1GHz sampling rate 1Gsps. Similar analog input structure, MAX104 features clock inputs designed either single-ended differential operation with very flexible input-drive requirements. Each clock input terminated with on-chip, laser-trimmed, precision NiCr resistor clock-termination return. This termination connected anywhere between ground compatibility with standard emitter-coupled-logic (ECL) drive levels. clock inputs internally buffered with amplifier ensure proper operation even with small-amplitude sine-wave sources. MAX104 designed single-ended operation, maintaining superior dynamic performance when using low-phase-noise sine-wave clock input signals with little 100mV amplitude. obtain lowest jitter clock drive, low-phase-noise sine-wave source DC-coupled into single clock input. MAX104 accommodate clock amplitudes peak-to-peak) with clock-termination return connected ground. dynamic performance essentially unaffected clock signal amplitudes from 100mV driven from standard differential clock source simply setting clocktermination voltage -2V. maintain best performance, very- high-speed differential driver should used. Clock inputs CLK+ CLK- also driven with positive referenced (PECL) logic levels clock inputs coupled. single-ended drive also used undriven clock input connected voltage (nominally -1.3V). Another useful feature MAX104 internal output demultiplexer (demux) circuitry. This circuitry provides three different modes operation. demux operation controlled transistortransistor-logic (CMOS)-compatible digital inputs: DEMUXEN, which activates deactivates internal demux, DIVSELECT, which selects three demux modes (DIV1, DIV2, DIV4). DIV2 (demux) mode reduces output data rate one-half sample clock rate. demuxed outputs presented dual 8-bit format with consecutive samples primary auxiliary output www.maxim-ic.com/an642 Page
ports rising edge data-ready clock. DIV1 nondemultiplexed (nondemux) mode supports operation MAX104 sampling speeds megasamples second (Msps). this mode, internal demux disabled sampled data presented primary output port only. consume less power, auxiliary port shut down separate inputs (AUXEN1 AUXEN2). save additional power, external termination resistors connected logic PECL power supply (VCCO -2V) removed from auxiliary output ports. special decimated, demuxed output mode (DIV4), MAX104 discards every other input sample outputs data quarter input sampling rate. This mode particularly useful system debugging using resulting slower output data rates. With input clock 1GHz, effective output data rate will reduced 250MHz this mode. Along with on-chip demux, MAX104 provides internal demux reset circuitry that enables multiple ADCs synchronized proper interleaving operation. addition, reset signal appears external demux reset output synchronizing external demuxes. Furthermore, MAX104 provides latched, differential PECL outputs, which make ideal driving controlled low-impedance lines. PECL outputs powered from +5.25V supply voltages. PECL outputs MAX104 typically terminated with parallel termination resistor into VCCO (the PECL termination voltage). Primary port outputs labeled P0-P7 (LSB MSB), while auxiliary ports labeled A0-A7. Outputs DREADY+ DREADY- data-ready true complementary outputs, supplying data clock. These signal lines used latch output data from primary auxiliary output ports, well supplying synchronous clock downstream digital circuitry, such demuxes high-speed memory devices. Data changes triggered rising edge DREADY clock. Outputs overrange true complementary outputs. Outputs RSTOUT+ RSTOUTare reset-out true complementary outputs provided reset downstream circuitry. MAX104 supplied 192-contact enhanced-super-ball-grid-array (ESBGA) package from Amkor/Anam (Chandler, that measures 25mm 25mm. MAX104 provides on-board demux function, slowing data rates 500Mbps supplied ports. package features microstrip interconnects from solder balls bond wires, which support high input/output (I/O) operating frequencies. addition, package enables large number solder balls dedicated power supplies ground. With thickness only 1.4mm, this 1.27mm pitch ESBGA package saves circuit-board space while providing excellent thermal performance. many applications, MAX104 used without heat sink. MAX104 ideal many applications where high sampling rates required either capture instantaneous value from fast-moving signal, such high-speed data acquisition (DAQ) application, digitize complex high-frequency, high-bandwidth signal. example this wideband digital receivers digital base stations. this case, signal bandwidths that exceed 300MHz allowed pass through receiver intermediate-frequency (IF) stages demodulator. this point, information bandwidth filtered amplified before being presented front end. This approach, known block direct downconversion, requires that input bandwidth sufficiently flat prevent distortions nonlinearities resulting digital representation. high-speed data stream thus created then presented digital demodulator which separates individual channels extracts modulated information.
Applying
exceptional spurious-free dynamic-range (SFDR) performance MAX104 input frequencies below (e.g., 125MHz 250MHz) well above Nyquist frequency (e.g., operating www.maxim-ic.com/an642 Page
1GHz) make MAX104 converter choice oversampled well undersampled 8-bit digital communications applications. instance, MAX104 delivers 47.4dB 68.9dB SFDR analog input frequency 125MHz. two-tone performance impressive -57.7dB same test frequency. Another ideal application instruments systems. These systems that designed sample, analyze, display signal waveforms detected various nodes within circuit under analysis (e.g., high-speed, multichannel digital oscilloscopes). ADCs used front-end circuitry digital sampling oscilloscopes (DSOs). Often, multiple converters time interleaved increase effective sampling frequency. Maxim's 600Msps/1.5Gsps converter, MAX106, provides designers with options lower even higher sampling speeds. Important data-converter specifications applications include analog signal input bandwidth, gain flatness, ENOB performance, occurrence metastable states. differential comparator design decoding circuitry reduce out-of-sequence code errors, such thermometer bubbles sparkle codes, provide excellent metastable performance less than error 1016 clock cycles. Unlike other ADCs, which have errors that result false full-scale zero-scale outputs, MAX104 keeps error magnitude more than 1LSB. Furthermore, this fast accomplishes outstanding numbers integral-nonlinearity (INL) differential-nonlinearity (DNL) parameters, ensuring monotonic operation. After trimming, MAX104 displays parameters ±0.25LSB (Figures
Figure MAX104's typical integral nonlinearity.
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Figure MAX104's typical differential nonlinearity. similar version this article appeared March 1999 issue Microwaves
MORE INFORMATION MAX104: QuickView MAX105: QuickView MAX106: QuickView MAX107: QuickView MAX108: QuickView
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Application Note 642: 2001 Analog-to-Digital Converter Captures 1

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