IDT7015S/L True Dual-Ported memory cells which allow simultaneous
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HIGH-SPEED DUAL-PORT STATIC
IDT7015S/L
True Dual-Ported memory cells which allow simultaneous access same memory location High-speed access Military: 20/25/35ns (max.) Commercial: 12/15/17/20/25/35ns (max.) Low-power operation IDT7015S Active: 750mW (typ.) Standby: (typ.) IDT7015L Active: 750mW (typ.) Standby: (typ.) IDT7015 easily expands data width bits more using Master/Slave select when cascading more than device BUSY output flag Master BUSY input Slave
Interrupt Busy Flags On-chip port arbitration logic Full on-chip hardware support semaphore signaling between ports Fully asynchronous operation from either port Devices capable withstanding greater than 2001V electrostatic discharge TTL-compatible, single (±10%) power supply Available ceramic 68-pin PGA, 68-pin PLCC, 80-pin TQFP Industrial temperature range (-40°C +85°C) available, tested military electrical specifications
DESCRIPTION:
IDT7015 high-speed Dual-Port Static RAMs. IDT7015 designed used stand-alone Dual-Port combination MASTER/SLAVE DualPort 18-bit-or-more word systems. Using
FUNCTIONAL BLOCK DIAGRAM
I/O0L- I/O8L Control Control
I/O0R-I/O8R
BUSYL
(1,2)
BUSYR
Address Decoder
(1,2)
A12L
MEMORY ARRAY
Address Decoder
A12R
ARBITRATION INTERRUPT SEMAPHORE LOGIC
SEMR
INTR
SEML
INTL
2954
NOTES: MASTER mode: BUSY output push-pull driver SLAVE mode: BUSY input. BUSY outputs outputs non-tri-stated push-pull drivers.
logo registered trademark
MILITARY COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc. latest information contact IDT's site www.idt.com fax-on-demand 408-492-8391.
OCTOBER 1996
DSC-2954/2
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
MASTER/SLAVE Dual-Port approach 18-bit wider memory system applications results full-speed, error-free operation without need additional discrete logic. This device provides independent ports with separate control, address, pins that permit independent, asynchronous access reads writes location memory. automatic power down feature controlled permits on-chip circuitry each port enter very standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate only 750mW power. IDT7015 packaged ceramic 68-pin PGA, 64pin PLCC 80-pin TQFP (Thin Quad FlatPack). Military grade product manufactured compliance with latest revision MIL-STD-883, Class making ideally suited military temperature applications demanding highest level performance reliability.
CONFIGURATIONS (1,2)
I/O1L I/O0L I/O8L
SEML
INDEX I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
A12L A11L A10L
IDT7015 J68-1 PLCC VIEW
INTL
BUSYL BUSYR
INTR
I/O7R I/O8R
SEMR
A12R A11R A10R
NOTES: pins must connected power supply. pins must connected ground supply. This text does imply orientation Part-Mark.
2954
NAMES
Left Port R/WL Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master Slave Select Power Ground
2954
R/WR
A12R I/O0R I/O8R
A12L I/O0L I/O8L
SEML INTL BUSYL
SEMR INTR BUSYR
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
CONFIGURATIONS (CON'T.) (1,2)
I/O0L I/O8L I/O1L
SEML
A12L A11L A10L
INDEX
I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
INTL
IDT7015 PN-80 TQFP VIEW
BUSYL
INTR
BUSYR
I/O7R I/O8R
A11R
A10R
SEMR
A12R
2954
BUSYL
INTL
INTR
BUSYR
A11L A10L A12L
IDT7015 G68-1 68-PIN VIEW
A11R A10R A12R
SEML R/WL
SEMR
I/O0L I/O8L I/O1L I/O2L I/O4L I/O3L I/O5L I/O7L I/O1R I/O4R I/O6L I/O0R I/O2R I/O3R I/O5R
I/O7R I/O8R I/O6R
2954
NOTES: must connected power supply. must connected ground supply. This text does imply orientation Part-Mark.
INDEX
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
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TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
Inputs(1) Outputs
I/O0-8 High-Z DATAIN DATAOUT High-Z Deselected: Power-Down Write Memory Read Memory Outputs Disabled
Mode
NOTE: Condition: A12L equal A12R.
2954
TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL Inputs Outputs
I/O0-8 DATAOUT DATAIN Write I/O0 into Semaphore Flag Allowed
Mode Read Semaphore Flag Data (I/O0-8)
NOTE: There eight semaphore flags written I/O0 read from I/O0-8 These eight semaphores addressed
2954
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM
Rating
Commercial
Military -0.5 +7.0
Unit
RECOMMENDED OPERATING TEMPERATURE SUPPLY VOLTAGE
Grade Military Commercial Ambient Temperature -55°C +125°C +70°C 5.0V 5.0V
2954
Terminal Voltage -0.5 +7.0 with Respect Operating Temperature Temperature Under Bias Storage Temperature Output Current +125 +125
TBIAS TSTG IOUT
+125 +135 +150
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Supply Voltage Supply Voltage Input High Voltage Input Voltage Min. -0.5
Typ.
Max. Unit 6.0(2)
2954
NOTES: 2954 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. VTERM must exceed 0.5V more than cycle time 10ns maximum, limited 20mA period VTERM 0.5V.
NOTES: -1.5V pulse width less than 10ns. VTERM must exceed 0.5V.
CAPACITANCE(1)
+25°C, 1.0MHz) TQFP ONLY
Symbol COUT Parameter Input Capacitance Output Capacitance Conditions(2) VOUT Max. Unit
2954 NOTES: This parameter determined device characteristics production tested. references interpolated capacitance when input output signals switch from from
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE (VCC 5.0V 10%)
7015S Symbol |ILI| |ILO| Parameter Input Leakage Current
7015L Min. Max. Unit
2954
Test Conditions 5.5V,
Min.
Max.
Output Leakage Current Output Voltage Output High Voltage
VIH, VOUT
-4mA
NOTE: 2.0V, Input leakages undefined.
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(1) (VCC 5.0V 10%)
Symbol Parameter Dynamic Operating Current (Both Ports Active) ISB1 Standby Current (Both Ports Level Inputs) ISB2 Standby Current (One Port Level Inputs) ISB3 Full Standby Current (Both Ports CMOS Level Inputs) Test Condition Version MIL. COM'L. MIL. COM'L. 7015X12 Com'l. Only Typ.(2) Max. 7015X15 Com'l. Only Typ.(2) Max. 7015X17 Com'l. Only Typ.(2) Max. Unit
VIL, Outputs Open
fMAX(3)
SEMR SEML
fMAX(3)
CE"A"=VIL CE"B" VIH(5) MIL. Active Port Outputs Open SEMR SEML Both Ports 0.2V CE"A"< 0.2V CE"B" 0.2V(5) SEMR SEML 0.2V
0.2V 0.2V Active Port Outputs Open, fMAX(3) 0.2V 0.2V, 0(4) SEMR SEML 0.2V fMAX(3) COM'L. MIL. COM'L.
ISB4
Full Standby Current (One Port CMOS Level Inputs)
MIL.
COM'L.
NOTES: 2954 part numbers indicates power rating +25°C, production tested. ICCDC 120mA(typ.) fMAX, address I/O'S cycling maximum frequency read cycle 1/tRC, using Test Conditions" input levels means address control lines change. Port either left right port. Port opposite port "A".
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(1)(Cont'd) (VCC 5.0V 10%)
7015X20 Symbol Parameter Dynamic Operating Current (Both Ports Active) ISB1 Standby Current (Both Ports Level Inputs) ISB2 Standby Current (One Port Level Inputs) ISB3 Full Standby Current (Both Ports CMOS Level Inputs) Test Condition Version MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. Typ.(2) Max. 7015X25 7015X35 Typ.(2) Max. Typ.(2) Max. Unit
VIL, Outputs Open
fMAX(3)
SEMR SEML
fMAX(3)
CE"A"=VIL CE"B"=VIH(5)
Active Port Outputs Open fMAX(3)
ISB4
Full Standby Current (One Port CMOS Level Inputs)
Both Ports 0.2V 0.2V 0.2V, 0(4) SEMR SEML 0.2V CE"A"< 0.2V CE"B" 0.2V(5) SEMR SEML 0.2V 0.2V 0.2V Active Port Outputs Open, fMAX(3)
SEMR SEML
MIL.
COM'L.
NOTES: part numbers indicates power rating +25°C, production tested. ICCDC 120mA(typ.) fMAX, address I/O'S cycling maximum frequency read cycle tRC, using Test Conditions" input levels means address control lines change. Port either left right port. Port opposite port "A".
2954
OUTPUT LOADS TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times(1) Output Reference Levels Output Load
NOTE: Max. tAA=12ns
DATAOUT
DATAOUT
3.0V Max. 1.5V Figure
Input Timing Reference Levels 1.5V
BUSY
30pF
2954
2954
Figure Output Test Load
Figure Output Test Load (For tLZ, tHZ, tWZ, tOW) Including scope jig.
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(4)
Symbol READ CYCLE tACE tAOE tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time(3) Output Enable Access Time Output Hold from Address Change Output Low-Z Time
Parameter
IDT7015X12 Com'l. Only Min. Max.
IDT7015X15 Com'l. Only Min. Max.
IDT7015X17 Com'l. Only Min. Max.
Unit
Output High-Z Time(1, Chip Enable Power Time(2) Chip Disable Power Down Time Semaphore Address Access Time Semaphore Flag Update Pulse SEM)
IDT7015X20 Symbol READ CYCLE tACE tAOE tSOP tSAA NOTES:
IDT7015X25 Min. Max.
IDT7015X35 Min. Max. Unit
2954
Parameter Read Cycle Time Address Access Time Chip Enable Access Time(3) Output Enable Access Time Output Hold from Address Change Output Low-Z Time
Min.
Max.
Output High-Z Time
Chip Enable Power Time(2) Chip Disable Power Down Time(2) Semaphore Flag Update Pulse SEM) Semaphore Address Access Time
Transition measured ±200mV from Low- High-impedance voltage with Output test load (Figure This parameter guaranteed device characterization tested. access RAM, VIH. access semaphore, VIL. part numbers indicates power rating
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
WAVEFORM READ CYCLES(5)
ADDR tACE tAOE
VALID DATA
DATAOUT
tHZ(2)
BUSYOUT
tBDD
2954
NOTES: Timing depends which signal asserted last, Timing depends which signal de-asserted first, tBDD delay required only cases where opposite port completing write operation same address location. simultaneous read operations BUSY relation valid output data. Start valid data depends which timing becomes effective last tAOE, tACE, tBDD. VIH.
TIMING POWER-UP POWER-DOWN
2954
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE(5)
Symbol WRITE CYCLE tSWRD tSPS Write Cycle Time Chip Enable End-of-Write Address Set-up Time(3) Write Pulse Width Write Recovery Time Data Valid End-of-Write Output High-Z Time Data Hold Time
Parameter
IDT7015X12 Com'l. Only Min. Max.
IDT7015X15 Com'l. Only Min. Max.
IDT7015X17 Com'l. Only Min. Max.
Unit
Address Valid End-of-Write
Write Enable Output High-Z(1, Output Active from End-of-Write(1,
Flag Write Read Time Flag Contention Window
IDT7015X20 Symbol WRITE CYCLE tSWRD tSPS Write Cycle Time Chip Enable End-of-Write(3) Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid End-of-Write Output High-Z Time(1, Data Hold Time
IDT7015X25 Min. Max.
IDT7015X35 Min. Max. Unit
Parameter
Min.
Max.
Write Enable Output High-Z
Output Active from End-of-Write(1,
Flag Write Read Time Flag Contention Window
NOTES: 2954 Transition measured ±200mV from High-impedance voltage with Output test load (Figure This parameter guaranteed device characterization tested. access RAM, VIH. access semaphore, VIL. Either condition must valid entire time. specification must device supplying write data under operating conditions. Although values will vary over voltage temperature, actual will always smaller than actual tOW. part numbers indicates power rating
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM WRITE CYCLE CONTROLLED TIMING(1,5,8)
ADDRESS
DATA
DATA
2954
TIMING WAVEFORM WRITE CYCLE CONTROLLED TIMING(1,5)
ADDRESS
tWR(3)
DATAIN
2954
NOTES: must High during address transitions. write occurs during overlap (tEW tWP) memory array writing cycle. measured from earlier R/W) going High write cycle. During this period, pins output state input signals must applied. transition occurs simultaneously with after transition, outputs remain High-impedance state. Timing depends which enable signal asserted last, R/W. This parameter guaranteed device characterization production tested, transition measured +/-200mV from steady state with Output Test load (Figure during controlled write cycle, write pulse width must larger (tWZ tDW) allow drivers turn data placed required tDW. High during controlled write cycle, this requirement does apply write pulse short specified tWP. access RAM, VIH. access Semaphore, VIL. must either condition.
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tSAA A0-A2 VALID ADDRESS DATAIN VALID VALID ADDRESS tACE tSOP DATAOUT VALID(2)
tSWRD
tAOE
Write Cycle Read Cycle
2954
NOTES: duration above timing (both write read cycle). "DATAOUT VALID" represents I/O's (I/O0-I/O8) equal semaphore value.
TIMING WAVEFORM SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2 MATCH
SIDE(2)
W"A"
tSPS MATCH
SEM"A"
A0"B"-A2
SIDE(2)
W"B"
SEM"B"
2954
NOTES: =VIH, =VIH. timing same left right ports. Port either left right port. opposite port from "A". This parameter measured from R/W"A" SEM"A" going high R/W"B" SEM"B" going High. tSPS satisfied, there guarantee which side will obtain semaphore flag.
6.12
IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(6)
Symbol BUSY TIMING (M/S VIH) tBAA tBDA tBAC tBDC tAPS tBDD Parameter IDT7015X12 Com'l. Only Min. Max. IDT7015X15 Com'l. Only Min. IDT7015X17 Com'l. Only Max. Unit
BUSY Access Time from Address Match BUSY Disable Time from Address Matched BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable Valid Data Write Hold After BUSY(5) BUSY TIMING (M/S VIL) BUSY Input Write(4) Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING tWDD tDDD
Write Pulse Data Delay(1) Write Data Valid Read Data Delay(1)
IDT7015X20 Symbol BUSY TIMING (M/S VIH) tBAA tBDA tBAC tBDC tAPS tBDD Parameter Min. Max.
IDT7015X25 Min. Max.
IDT7015X35 Min. Max. Unit
BUSY Access Time from Address Match BUSY Disable Time from Address Matched BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time
BUSY Disable Valid Data Write Hold After BUSY(5) BUSY TIMING (M/S VIL) BUSY Input Write(4) Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING tWDD
Write Pulse Data Delay(1) Write Data Valid Read Data Delay
2940
tDDD
NOTES: Port-to-port delay through cells from writing port reading port, refer "Timing Wave form Write with Port-to-Port Read ensure that earlier ports wins. tBDD calculated parameter greater tWDD (actual), tDDD (actual). ensure that write cycle inhibited port during contention port "A". ensure that write cycle completed port after contention port "A". part numbers indicates power rating
BUSY (M/S VIH)".
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM READ WITH BUSY (M/S VIH)(2,4,5)
ADDR"A" MATCH
W"A"
VALID tAPS
DATAIN
ADDR"B"
MATCH tBDA tBDD
BUSY"B"
tWDD DATAOUT tDDD
2954
VALID
NOTES: ensure that earlier ports wins. tAPS ignored M/S=VIL. VIL. reading port. (slave), BUSY input. Then this example BUSY"A" BUSY"B" input shown above. timing same left right ports. Port either left right port. Port port opposite from port "A".
TIMING WAVEFORM WRITE WITH BUSY
W"A"
tWH(
BUSY"B"
W"B"
NOTES: 2954 must both BUSY input (SLAVE) output (MASTER). BUSY asserted port blocking R/W"B", until BUSY"B" goes High. timing same left right ports. Port either left right port. Port port opposite from port "A".
6.12
IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
WAVEFORM BUSY ARBITRATION CONTROLLED TIMING (M/S VIH)(1)
ADDR"A" ADDRESSES MATCH
CE"A"
tAPS
CE"B"
tBAC tBDC
BUSY"B"
2954
WAVEFORM BUSY ARBITRATION CYCLE CONTROLLED ADDRESS MATCH TIMING (M/S VIH)(1)
ADDR"A" tAPS ADDR"B" tBAA
ADDRESS
MATCHING ADDRESS tBDA
BUSY"B"
2954
NOTES: timing same left right ports. Port either left right port. Port port opposite from "A". tAPS satisfied, busy signal will asserted side another there guarantee which side busy will asserted.
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(1)
Symbol INTERRUPT TIMING tINS tINR Address Set-up Time Write Recovery Time Interrupt Time Interrupt Reset Time IDT7015X20 Symbol INTERRUPT TIMING tINS tINR Address Set-up Time Write Recovery Time Interrupt Time Interrupt Reset Time
2739
Parameter
IDT7015X12 Com'l. Only Min. Max.
IDT7015X15 Com'l. Only Min. Max.
IDT7015X17 Com'l. Only Max. IDT7015X35 Min. Max.
Unit
IDT7015X25 Min. Max.
Parameter
Min.
Max.
Unit
NOTE: part numbers indicates power rating
6.12
IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
WAVEFORM INTERRUPT TIMING(1)
ADDR"A"
INTERRUPT ADDRESS
CE"A"
W"A"
tINS
INT"B"
2954
ADDR"B"
INTERRUPT CLEAR ADDRESS
CE"B"
OE"B"
tINR
INT"B"
2954
NOTES: timing same left right ports. Port either left right port. Port port opposite from "A". Interrupt truth table. Timing depends which enable signal R/W) asserted last. Timing depends which enable signal R/W) de-asserted first.
TRUTH TABLES TRUTH TABLE INTERRUPT FLAG(1)
Left Port R/WL Right Port A12L-A0L 1FFF 1FFE
INTL
L(3)
R/WR
A12R-A0R 1FFF 1FFE
INTR
Function Right INTR Flag Left INTL Flag Reset Right INTR Flag Reset Left INTL Flag
2954
NOTES: Assumes BUSYL BUSYR VIH. BUSYL VIL, then change. BUSYR VIL, then change.
6.12
IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE ADDRESS BUSY ARBITRATION
Inputs
Outputs
BUSYL
A0L-A12L A0R-A12R
MATCH MATCH MATCH MATCH
BUSYR
Function Normal Normal Normal Write Inhibit(3)
NOTES: 2954 Pins BUSYL BUSYR both outputs when part configured master. Both inputs when configured slave. BUSYX outputs IDT7015 push-pull, open drain outputs. slaves BUSYX input internally inhibits writes. inputs opposite port were stable prior address enable inputs this port. inputs opposite port became stable after address enable inputs this port. met, either BUSYL BUSYR will result. BUSYL BUSYR outputs simultaneously. Writes left port internally ignored when BUSYL outputs driving regardless actual logic level pin. Writes right port internally ignored when BUSYR outputs driving regardless actual logic level pin.
TRUTH TABLE EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions Action Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Left Right Semaphore free Left port semaphore token change. Right side write access semaphore Right port obtains semaphore token change. Left port write access semaphore Left port obtains semaphore token Semaphore free Right port semaphore token Semaphore free Left port semaphore token Semaphore free
2954
Status
NOTES: This table denotes sequence events only eight semaphores IDT7015. There eight semaphore flags written I/O0 read from I/O0-8. These eight semaphores addressed
FUNCTIONAL DESCRIPTION
IDT7015 provides ports with separate control, address pins that permit independent access reads writes location memory. IDT7015 automatic power down feature controlled controls on-chip power down circuitry that permits respective port into standby mode when selected High). When port enabled, access entire memory array permitted. memory location 1FFF clear interrupt flag (INTR), right port must access memory location 1FFF. message bits) 1FFE 1FFF user-defined since addressable SRAM location. interrupt function used, address locations 1FFE 1FFF used mail boxes still part random access memory. Refer Truth Table interrupt operation.
BUSY LOGIC INTERRUPTS
user chooses interrupt function, memory location (mail message center) assigned each port. left port interrupt flag (INTL) asserted when right port writes memory location 1FFE where write defined Truth Table. left port clears interrupt address location 1FFE access when =OER =VIL, "don't care". Likewise, right port interrupt flag (INTR) asserted when left port writes Busy Logic provides hardware indication that both ports have accessed same location same time. also allows accesses proceed signals other side that "Busy". busy then used stall access until operation other side completed. write operation been attempted from side that receives busy indication, write signal gated internally prevent write from proceeding. busy logic required desirable
6.12
IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
MASTER Dual Port BUSY
BUSY
SLAVE Dual Port BUSY
BUSY
BUSY
MASTER Dual Port BUSY
BUSY
SLAVE Dual Port BUSY
BUSY BUSY
2954
Figure Busy chip enable routing both width depth expansion with IDT7015 RAMs.
applications. some cases useful logically busy outputs together busy indication interrupt source flag event illegal illogical operation. write inhibit function busy logic desirable, busy logic disabled placing part slave mode with pin. Once slave mode BUSY operates solely write inhibit input pin. Normal operation programmed tying BUSY pins high. desired, unintended write operations prevented port tying busy that port low. busy outputs IDT7015 master mode, push-pull type outputs require pull resistors operate. these RAMs being expanded depth, then busy indication resulting array requires external gate.
initiated with signal. Failure observe this timing result glitched internal write inhibit signal corrupted data slave.
SEMAPHORES
IDT7015 extremely fast Dual-Port 8Kx9 Static RAMs with additional address locations dedicated binary semaphore flags. These flags allow either processor left right side Dual-Port claim privilege over other processor functions defined system designer's software. example, semaphore used processor inhibit other from accessing portion Dual-Port other shared resource. Dual-Port features fast access time, both ports completely independent each other. This means that activity left port slows access time right port. Both ports identical function standard CMOS Static read from, written same time with only possible conflict arising from simultaneous writing simultaneous READ/WRITE non-semaphore location. Semaphores protected against such ambiguous situations used system program avoid conflicts non-semaphore portion Dual-Port RAM. These devices have automatic power-down feature controlled Dual-Port enable, SEM, semaphore enable. pins control on-chip power down circuitry that permits respective port into standby mode when selected. This condition which shown Truth Table where both high. Systems which best IDT7015 contain multiple processors controllers typically very high-speed systems which software controlled software intensive. These systems benefit from performance increase offered IDT7015's hardware semaphores, which provide lockout mechanism without requiring complex programming.
WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS
When expanding IDT7015 array width while using busy logic, master part used decide which side array will receive busy indication, output that indication. number slaves addressed same address range master, busy signal write inhibit signal. Thus IDT7015 busy output part used master (M/S busy input part used slave (M/S shown Figure more master parts were used when expanding width, split decision could result with master indicating busy side array another master indicating busy other side array. This would inhibit write operations from port part word inhibit write operations from other port other part word. busy arbitration, master, based chip enable address signals only. ignores whether access read write. master/slave array, both address chip enable must valid long enough busy flag output from master before actual write pulse
6.12
DECODER
IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
Software handshaking between processors offers maximum system flexibility permitting shared resources allocated varying configurations. IDT7015 does semaphore flags control resources through hardware, thus allowing system designer total flexibility system architecture. advantage using semaphores rather than more common methods hardware arbitration that wait states never incurred either processor. This prove major advantage very high-speed systems.
SEMAPHORE FLAGS WORK
semaphore logic eight latches which independent Dual-Port RAM. These latches used pass flag, token, from port other indicate that shared resource use. semaphores provide hardware assist assignment method called "Token Passing Allocation." this method, state semaphore latch used token indicating that shared resource use. left processor wants this resource, requests token setting latch. This processor then verifies success setting latch reading successful, proceeds assume control over shared resource. successful setting latch, determines that right side processor latch first, token using shared resource. left processor then either repeatedly request that semaphore's status remove request that semaphore perform another task occasionally attempt again gain control token test sequence. Once right side relinquished token, left side should succeed gaining control. semaphore flags active low. token requested writing zero into semaphore latch released when same side writes that latch. eight semaphore flags reside within IDT7015 separate memory space from Dual-Port RAM. This address space accessed placing input (which acts chip select semaphore flags) using other control pins (Address, R/W) they would used accessing standard static RAM. Each flags unique address which accessed either side through address pins When accessing semaphores, none other address pins effect. When writing semaphore, only data used. level written into unused semaphore location, that flag will zero that side other side (see Table III). That semaphore only modified side showing zero. When written into same location from same side, flag will both sides (unless semaphore request from other side pending) then written both sides. fact that side which able write zero into semaphore subsequently locks writes from other side what makes semaphore flags useful interprocessor communications. thorough discussing this feature follows shortly.) zero written into same location from other side will stored semaphore request latch that side
until semaphore freed first side. When semaphore flag read, value spread into data bits that flag that reads data bits flag containing zero reads zeros. read value latched into side's output register when that side's semaphore select (SEM) output enable (OE) signals active. This serves disallow semaphore from changing state middle read cycle write cycle from other side. Because this latch, repeated read semaphore test loop must cause either signal (SEM inactive output will never change. sequence WRITE/READ must used semaphore order guarantee that system level contention will occur. processor requests access shared resources attempting write zero into semaphore location. semaphore already use, semaphore request latch will contain zero, semaphore flag will appear one, fact which processor will verify subsequent read (see Table III). example, assume processor writes zero left port free semaphore location. subsequent read, processor will verify that written successfully that location will assume control over resource question. Meanwhile, processor right side attempts write zero same semaphore flag will fail, will verified fact that will read from that semaphore right side during subsequent read. sequence READ/WRITE been used instead, system contention problems could have occurred during between read write cycles. important note that failed semaphore request must followed either repeated reads writing into same location. reason this easily understood looking simple logic diagram semaphore flag Figure semaphore request latches feed into semaphore flag. Whichever latch first present zero semaphore flag will force side semaphore flag other side high. This condition will continue until written same semaphore request latch. Should other side's semaphore request latch have been written zero meantime, semaphore flag will flip over other side soon written into first side's request latch. second side's flag will stay until semaphore request latch written one. From this easy understand that, semaphore requested processor which requested longer needs resource, entire system hang until written into that semaphore request latch. critical case semaphore timing when both sides request single token attempting write zero into same time. semaphore logic specially designed resolve this problem. simultaneous requests made, logic guarantees that only side receives token. side earlier than other making request, first side make request will receive token. both requests arrive same time, assignment will arbitrarily made port other. caution that should noted when using semaphores that semaphores alone guarantee that access
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
resource secure. with powerful programming technique, semaphores misused misinterpreted, software error easily happen. Initialization semaphores automatic must handled initialization program power-up. Since semaphore request flag which contains zero must reset one, semaphores both sides should have written into them initialization from both sides assure that they will free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps simplest application semaphores their application resource markers IDT7015's Dual-Port RAM. divided into blocks which were dedicated time servicing either left right port. Semaphore could used indicate side which would control lower section memory, Semaphore could defined indicator upper section memory. take resource, this example lower Dual-Port RAM, processor left port could write then read zero Semaphore this task were successfully completed zero read back rather than one), left processor would assume control lower Meanwhile right processor attempting gain control resource after left processor, would read back response zero attempted write into Semaphore this point, software could choose gain control second section writing, then reading zero into Semaphore succeeded gaining control, would lock left side. Once left side finished with task, would write Semaphore then gain access Semaphore Semaphore still occupied right side, left side could undo semaphore request perform other tasks until able write, then read zero
into Semaphore right processor performs similar task with Semaphore this protocol would allow processors swap blocks Dual-Port with each other. blocks have particular size even variable, depending upon complexity software using semaphore flags. eight semaphores could used divide Dual-Port other shared resources into eight parts. Semaphores even assigned different meanings different sides rather than being given common meaning shown example above. Semaphores useful form arbitration systems like disk interfaces where must locked section memory during transfer device cannot tolerate wait states. With semaphores, once devices determined which memory area "off-limits" CPU, both devices could access their assigned portions memory continuously without wait states. Semaphores also useful applications where memory "WAIT" state available both sides. Once semaphore handshake been performed, both processors access their assigned segments full speed. Another application area complex data structures. this case, block arbitration very important. this application processor responsible building updating data structure. other processor then reads interprets that data structure. interpreting processor reads incomplete data structure, major error condition exist. Therefore, some sort arbitration must used between different processors. building processor arbitrates block, locks then able update data structure. When update completed, data structure block released. This allows interpreting processor come back read complete data structure, thereby guaranteeing consistent data structure.
PORT SEMAPHORE REQUEST FLIP FLOP WRITE SEMAPHORE READ
PORT SEMAPHORE REQUEST FLIP FLOP
WRITE
SEMAPHORE READ
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Figure IDT7015 Semaphore Logic
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IDT7015S/L HIGH-SPEED DUAL-PORT STATIC
MILITARY COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXXX Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0°C +70°C) Military (-55°C +125°C) Compliant MIL-STD-883, Class
7015
80-pin TQFP (PN80-1) 68-pin (G68-1) 68-pin PLCC (J68-1) Commercial Only Commercial Only Commercial Only
Speed nanoseconds
Standard Power Power Dual-Port
2954
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