16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,1
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M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
DESCRIPTION MITSUBISHI M6MGB/T166S4BWG Stacked Chip Scale Package (S-CSP) that contents 16M-bits flash memory 4M-bits Static 72-pin S-CSP. 16M-bits Flash memory 1,048,576 words, 3.3V-only, high performance non-volatile memory fabricated CMOS technology peripheral circuit DINOR(DIvided bit-line NOR) architecture memory cell. 4M-bits SRAM 262,144words unsynchronous SRAM fabricated silicon-gate CMOS technology. M6MGB/T166S4BWG suitable application mobile-communication-system reduce both mount space weight
FEATURES Access time Flash Memory 90ns (Max.) SRAM 85ns (Max.) Supply voltage Vcc=2.7 3.6V Ambient temperature version Ta=-20 85°C Package 72-pin S-CSP 0.8mm ball pitch
APPLICATION Mobile communication products
CONFIGURATION (TOP VIEW) INDEX
F-A18 S-LB# F-WP# F-WE# FRY/BY#
DQ15
F-GND
F-A17
S-UB#
F-A19
F-RP#
F-VCC S-VCC F-GND A0-A16
SCE1#
S-OE#
DQ12 SCE2 S-VCC
S-A17
DQ11
11.0
F-CE#
DQ10
DQ13
:Vcc Flash :Vcc SRAM :GND Flash :Flash/SRAM common :Flash/SRAM common Address F-A17-F-A19 :Address Flash :Address SRAM S-A17 DQ0-DQ15 :Flash/SRAM common Data F-CE# S-CE1# S-CE2 F-OE# S-OE# F-WE# S-WE# F-WP# F-RP# F-RY/BY# S-LB# S-UB# :Flash Chip Enable :SRAM Chip Enable :SRAM Chip Enable :Flash Output Enable :SRAM Output Enable :Flash Write Enable :SRAM Write Enable :Flash Write Protect :Flash Reset Power Down :Flash Ready /Busy :SRAM Lower Byte :SRAM Upper Byte
F-GND
S-WE#
F-OE#
DQ14
F-VCC
NC:Non Connection DU:Don't (Note: Should open)
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
BLOCK DIAGRAM
16Mb Flash Memory
F-A19 F-A18 F-A17 ADDRESS INPUTS
F-CE# F-OE# F-WE# F-WP# F-RP#
WORD PAGE BUFFER Main Block 32KW
F-VCC(3.3V)
Bank(II)
F-GND/GND (0V)
Main Block
Parameter Block7 Parameter Block6 Parameter Block5 Parameter Block4 Parameter Block3 Parameter Block2 Parameter Block1 Boot Block
X-DECODER Bank(I)
32KW
16KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW
Y-DECODER
Y-GATE SENSE AMP.
STATUS REGISTER
MULTIPLEXER
CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT WRITE PROTECT INPUT RESET/POWER DOWN INPUT
INPUT/OUTPUT BUFFERS
READY/BUSY OUTPUT
F-RY/BY# DQ15 DQ14DQ13 DQ12 DQ3DQ2DQ1DQ0
SRAM
ADDRESS INPUT BUFFER SENSE AMP.
DATA INPUTS/OUTPUTS
DECODER
262144 WORD BITS
OUTPUT BUFFER
SENSE AMP.
OUTPUT BUFFER
S-A17 S-CE1# S-CE2 S-LB# S-UB# S-WE# S-OE#
CLOCK GENERATOR
DQ15
DATAINPUT BUFFER
S-VCC
DATAINPUT BUFFER
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
Flash Memory
DESCRIPTION
Flash Memory M6MGB/T166S4BWG 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating (Back Ground Operation) feature. feature device allows Program Erase operations performed bank while device simultaneously allows Read operations performed other bank. This feature suitable mobile personal computing, communication products. Flash Memory M6MGB/T166S4BWG fabricated CMOS technology peripheral circuits DINOR(Divided line NOR) architecture memory cells.
FEATURES
Organization
.1048,576 word 16bit
Boot Block M6MGB166S4BWG Bottom Boot M6MGT166S4BWG Boot Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) Bank(II)
2.7~3.6V Supply voltage
Access time
90ns (Max.)
Power Dissipation (Max. 5MHz) Read (After Automatic Power saving) 0.33µW (typ.) Program/Erase .126 (Max.) 0.33µW (typ.) Standby Deep power down mode 0.33µW (typ.) Auto program Bank(I) (typ.) Program Time Program Unit .1word (Byte Program) (Page Program) 128word Auto program Bank(II) (typ.) Program Time 128word Program Unit Auto Erase (typ.) Erase time Erase Unit Bank(I) Boot Block 16Kword Parameter Block 16Kword 32Kword Bank(II) Main Block Program/Erase cycles
100Kcycles
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
FUNCTION
Flash Memory M6MGB/T166S4BWG includes on-chip program/erase control circuitry. Write State Machine (WSM) controls block erase byte/page program operations. Operational modes selected commands written Command User Interface (CUI). Status Register indicates status when successfully completes desired program block erase operation. Deep Powerdown mode enabled when F-RP# GND, minimizing power consumption. Read Flash Memory M6MGB/T166S4BWG three read modes, which accesses memory array, Device Identifier Status Register. appropriate read command required written CUI. Upon initial device powerup after exit from deep powerdown, Flash Memory automatically resets read array mode. read array mode, level input F-CE# F-OE#, high level input F-WE# F-RP#, address signals address inputs (F-A19-F-A17,A16-A0) output data addressed location data input/output D15-D0). Write Writes enables reading memory array data, device identifiers reading clearing Status Register. They also enable block erase program. written bringing F-WE# level, while F-CE# level F-OE# high level. Address data latched earlier rising edge F-WE# F-CE#. Standard micro-processor write timings used. Alternating Background Operation (BGO) Flash Memory M6MGB/T166S4BWG allows read array from bank while other bank operates software command write cycling erasing programming operation background. Read array operation with other bank performed changing bank address without additional command. When bank address points bank software command write cycling erasing programming operation, data read from status register. access time with same normal read operation. Output Disable When F-OE# VIH, output from devices disabled. Data input/output high-impedance(High-Z) state. Standby When F-CE# VIH, device standby mode power consumption reduced. Data input/output high-impedance(High-Z) state. memory deselected during block erase program, internal control circuits remain active device consume normal active power until operation completes.
Deep Power-Down When F-RP# VIL, device deep powerdown mode power consumption substantially low. During read modes, memory deselected data input/output high-impedance(High-Z) state. After return from powerdown, reset Read Array Status Register cleared value 80H. During block erase program modes, F-RP# will abort either operation. Memory array data block being altered become invalid. Automatic Power-Saving (APS) Automatic Power-Saving minimizes power consumption during read mode. device automatically turns this mode when addresses F-CE# isn't changed more than 200ns after last alternation. power consumption becomes same stand-by mode. While this mode, output data latched read out. data read correctly when addresses changed.
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
C)Single Data Load Page Buffer (74H) Page Buffer Flash (0EH/D0H) Single data load page buffer performed writing followed second write specifying column address data. Distinct data 128word loaded page buffer this two-command sequence. other hand, loaded data page buffer programed simultaneously writing Page Buffer Flash command followed confirm command D0H. After completion programing data page buffer cleared automatically. This command valid only Bank(I) alike Word Program. Clear Page Buffer Command (55H) Loaded data page buffer cleared writing Clear Page Buffer command followed Confirm command D0H. This command valid clearing data loaded Single Data Load Page Buffer command. Suspend/Resume Command (B0H/D0H) Writing Suspend command during block erase operation interrupts block erase operation allows read from another block memory. Writing Suspend command during program operation interrupts program operation allows read from another block memory. Bank address required when writing Suspend/Resume Command. device continues output Status Register data when read, after Suspend command written Polling Status Suspend Status bits will determine when erase operation program operation been suspended. this point, writing Read Array command enables reading data from blocks other than that which suspended. When Resume command written CUI, will continue with erase program processes.
SOFTWARE COMMAND DEFINITIONS device operations selected writing specific software command into Command User Interface. Read Array Command (FFH) device Read Array mode initial device power after exit from deep powerdown, writing Command User Interface. After starting internal operation device read status register mode automatically. Read Device Identifier Command (90H) normally read device identifier codes when Read Device Identifier Code Command(90H) written command latch. Following command write, manufacturer code device code read from address 00000H 00001H, respectively. Read Status Register Command (70H) Status Register read after writing Read Status Register command Command User Interface. Also, after starting internal operation device Read Status Register mode automatically. contents Status Register latched later falling edge F-OE# F-CE#. F-CE# F-OE# must toggled every status read. Clear Status Register Command (50H) Erase Status, Program Status Block Status bits "1"s Write State Machine only reset Clear Status Register command 50H. These bits indicates various failure conditions.
DATA PROTECTION Block Erase Confirm Command (20H/D0H) Automated block erase initiated writing Block Erase command followed Confirm command D0H. address within block erased required. executes iterative erase pulse application erase verify operation. Program Commands A)Word Program (40H) Word program executed two-command sequence. Word Program Setup command written Command Interface, followed second write specifying address data written. controls program pulse application verify operation. Word Program Command Valid only Bank(I). B)Page Program Data Blocks (41H) Page Program Bank(I) Bank(II) allows fast programming 128words data. Writing initiates page program operation Data area. From cycle 129th cycle, write data must serially inputted. Address A6-A0 have incremented from 7FH. After completion data loading, controls program pulse application verify operation. Flash Memory M6MGB/T166S4BWG provides selectable block locking memory blocks. Each block associated nonvolatile lock-bit which determines lock status block. addition, Flash Memory master Write Protect (F-WP#) which prevents modifications memory blocks whose lock-bits "0", when F-WP# low. When F-WP# high, blocks programmed erased regardless state lock-bits, lock-bits cleared erase. BLOCK LOCKING table details. Power Supply Voltage When power supply voltage (F-VCC) less than VLKO, Lock-Out voltage, device Read-only mode. Regarding electrical characteristics VLKO, P.10. delay time required before device operation initiated. delay time measured from time F-Vcc reaches F-Vccmin (2.7V). During power F-RP#=GND recommended. Falling Busy status recommended possibility damaging device. MEMORY ORGANIZATION Flash Memory M6MGB/T166S4BWG 16Kword boot block, seven 16Kword parameter blocks, Bank(I) twenty-eight 32Kword main blocks Bank(II). block erased independently other blocks array.
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
MEMORY ORGANIZATION
F8000H-FFFFFH F0000H-F7FFFH E8000H-EFFFFH E0000H-E7FFFH D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 1C000H-1FFFFH 18000H-1BFFFH 14000H-17FFFH 10000H-13FFFH 0C000H-0FFFFH 08000H-0BFFFH 04000H-07FFFH 00000H-03FFFH F-A19-F-A17,A16-A0 (Word Mode)
32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK BANK(II) BANK(I) 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK
16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK 16Kword PARAMETER BLOCK
FC000H-FFFFFH
16Kword BOOT BLOCK
F8000H-FBFFFH 16Kword PARAMETER BLOCK F4000H-F7FFFH 16Kword PARAMETER BLOCK
BANK(I)
F0000H-F3FFFH 16Kword PARAMETER BLOCK EC000H-EFFFFH 16Kword PARAMETER BLOCK E8000H-EBFFFH 16Kword PARAMETER BLOCK E4000H-E7FFFH 16Kword PARAMETER BLOCK E0000H-E3FFFH 16Kword PARAMETER BLOCK D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 00000H-07FFFH F-A19-F-A17,A16-A0 (Word Mode)
32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK BANK(II) 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK
16Kword BOOT BLOCK
Flash Memory M6MGB166S4BWG Memory
Flash Memory M6MGT166S4BWG Memory
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
OPERATIONS Operations Word-Wide Mode
Pins
Mode Read
F-CE#
F-OE#
F-WE#
F-RP#
DQ0-15 Data Status Register Data Lock Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data Command Command Hi-Z
F-RY/BY# (Hi-Z) (Hi-Z) (Hi-Z)
Array Status Register Lock Status Identifier Code Output disable Stand Program Write Erase Others Deep Power Down
F-RY/BY# VOH(Hi-Z). *The F-RY/BY# open drain output indicates status internal WSM. When low,it indicates that Busy performing operation. pull-up resistor 10K-100K Ohms required allow F-RY/BY# signal transition high indicating Ready condition. control pins.
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
SOFTWARE COMMAND DEFINITION Command List
cycle Command Mode Read Array Device Identifier Read Status Register Clear Status Register Clear Page Buffer Word Program Page Program Single Data Load Page Buffer Page Buffer Flash Block Erase Confirm Suspend Resume Read Lock Status Lock Program Confirm Erase Unlocked Blocks Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address Bank3) Bank(I) Bank Bank(I) Bank(I) Bank Bank Bank Bank Data
(DQ15-0)
cycle Mode Address Bank Data
(DQ15-0)
~129th cycles (Word Mode)
Mode
Address
Data
(DQ15-0)
Read Read Write Write Write Write Write Write
SRD4)
Write
Read Write Write
word-wide version, upper byte data (DQ8-DQ15) ignored. IA=ID Code Address A0=VIL (Manufacturer's Code) A0=VIH (Device Code), ID=ID Code Bank Bank Address (Bank(I) Bank(II)) F-A19-F-A17. Status Register Data Word Program, Single Data Load Page Buffer Flash Command valid only Bank(I). Write Address,WD Write Data WA0,WAn=Write Address, WD0,WDn=Write Data. Write Address Write Data must provided sequentially from A6-A0. Page size 128word (128word 16bit). also F-A19-F-A17,A16-A7(Block Address, Page Address) must valid. Write Address Upper page address, F-A19-F-A17,A16-A7(Block Address, Page Address) must valid. Block Address Block Address F-A19-F-A17,A16-A14(Bank1) F-A19-F-A17,A16-A15(Bank2) provides Block Lock Status, Block Unlock, Block Locked.
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) BLOCK LOCKING
Lock F-RP# F-WP# (Internally) Write Protection Provided BANK(I) BANK(II) Note Lock Boot Parameter Data Locked Locked Locked Locked Deep Power Down Mode Locked Locked Locked Locked Locked Locked Unlocked Unlocked Unlocked Unlocked Unlocked Unlocked Blocks Unlocked
provides Lock Status each block after writing Read Lock Status command (71H). F-WP# pins must switched during performing Erase Write operations Busy (WSMS Erase/Write command locked blocks aborted. this time read mode array read mode status read mode 00B0H read. Please issue Clear Status Register command plus Read Array command change mode from status read mode array read mode.
STATUS REGISTER
Symbol SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 (DQ7) (DQ6) (DQ5) (DQ4) (DQ3) (DQ2) (DQ1) (DQ0) Status Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Reserved Definition Ready Suspended Error Error Error Busy Operation Progress Completed Successful Successful Successful
*The F-RY/BY# open drain output indicates status internal WSM. When low,it indicates that Busy performing operation. pull-up resistor 10K-100K Ohms required allow F-RY/BY# signal transition high indicating Ready condition. *DQ3 indicates block status after page programming, word programming page buffer flash. When "1", page over-programed cell over-program occurs, device block fail. However "1", please block erase block. block revive.
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) DEVICE IDENTIFIER CODE
Code Manufacturer Code Device Code (-T166S4BWG) Device Code (-B166S4BWG)
upper data(D15-8) "0".
Pins
Hex. Data
ABSOLUTE MAXIMUM RATINGS
Symbol F-Vcc Tstg Parameter Flash voltage input output voltage Ambient temperature Temperature under bias Storage temperature Output short circuit current Conditions
With respect Ground
-0.2 -0.6
Unit
Minimum voltage -0.5V input/output pins. During transitions, this level undershoot -2.0V periods <20ns. Maximum voltage input/output pins F-VCC+0.5V which, during transitions, overshoot F-VCC+1.5V periods <20ns.
CAPACITANCE
Symbol COUT Parameter Input capacitance (Address, Control Pins) Output capacitance Test conditions 25°C, 1MHz, Vout Limits Unit
Note: value common pins Flash Memory Flash Memory SRAM.
ELECTRICAL CHARACTERISTICS -20~ 85°C, F-Vcc 2.7V 3.6V, unless otherwise noted)
Symbol ISB1 ISB2 ISB3 ISB4 ICC1 ICC2 ICC3 ICC4 ICC5 VOH1 VOH2 VLKO Parameter Input leakage current Output leakage current F-VCC standby current Test conditions 0VVINF-VCC 0VVOUTF-VCC
F-VCC 3.6V, VIN=VIL/VIH, F-CE# F-RP# =F-WP#
Limits Typ1)
±2.0
(F-Vcc)+0.5
Unit
F-VCC 3.6V, VIN=GND F-VCC, F-CE# F-RP# F-WP# F-VCC±0.3V F-VCC 3.6V, VIN=VIL/VIH, F-RP#
F-VCC 3.6V, VIN=GND F-VCC, F-RP# =GND±0.3V
F-VCC deep powerdown current F-VCC
F-VCC 3.6V, VIN=VIL/VIH, F-CE# VIL, read current Word Byte F-RP#=F-OE#=VIH, IOUT
5MHz 1MHz
F-VCC Write current Word Byte F-VCC program current F-VCC erase current F-VCC suspend current Input voltage Input high voltage Output voltage Output high voltage Lock-Out voltage
F-VCC 3.6V,VIN=VIL/VIH, F-CE# =F-WE#= VIL, F-RP#=F-OE#=VIH
F-VCC 3.6V, VIN=VIL/VIH, F-CE# F-RP# =F-WP# F-VCC 3.6V, VIN=VIL/VIH, F-CE# F-RP# =F-WP# F-VCC 3.6V, VIN=VIL/VIH, F-CE# F-RP# =F-WP#
4.0mA -2.0mA -100µA
0.85(F-Vcc)
(F-Vcc)-0.4
0.45
currents unless otherwise noted. Typical values F-Vcc=3.3V, Ta=25°C protect against initiation write cycle during F-Vcc power-up/ down, write cycle locked F-Vcc less than VLKO. F-Vcc less than VLKO, Write State Machine reset read mode. When Write State Machine Busy state, F-Vcc less than VLKO, alteration memory contents
occur.
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
ELECTRICAL CHARACTERISTICS ~85°C, F-Vcc 2.7V ~3.6V) Read-Only Mode
Limits
Symbol
Parameter
F-Vcc=2.7-3.6V 90ns
Unit
(AD) (CE) (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ
tAVAV tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ tPHEL
Read cycle time Address access time Chip enable access time Output enable access time Chip enable output low-Z Chip enable high output high Output enable output low-Z Output enable high output high F-RP# output high-Z Output hold from F-CE#, OE#, addresses F-RP# recovery F-CE#
Timing measurements made under waveforms read operations.
ELECTRICAL CHARACTERISTICS ~85°C, F-Vcc 2.7V ~3.6V) Write Mode (F-WE# control)
Limits F-Vcc=2.7-3.6V 90ns
Symbol
Parameter
Unit
tOEH tWPH tGHWL tBLS tBLH tDAP tDAE tWHRL
tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tELWL tWHEH tWLWH tWHWL tGHWL tPHHWH tQVPH tWHRH1 tWHRH2 tWHRL tPHWL
Write cycle time Address set-up time Address hold time Data set-up time Data hold time F-OE# hold from F-WE# high Latency between Read Write Chip enable set-up time Chip enable hold time Write pulse width Write pulse width high F-OE# hold F-WE# Block Lock set-up write enable high Block Lockhold from valid Duration auto-program operation Duration auto-block erase operation Write enable high F-RY/BY# F-RP# high recovery write enable
Read timing parameters during command write operations mode same during read-only operations mode. Typical values F-Vcc=3.3V, Ta=25°C
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) ELECTRICAL CHARACTERISTICS 85°C, F-Vcc 2.7V 3.6V) Write Mode (F-CE# control)
Limits F-Vcc=2.7-3.6V 90ns
Symbol
Parameter
Unit
tOEH tCEP tCEPH tGHEL tBLS tBLH tDAP tDAE tEHRL
tAVAV tAVWH tEHAX tDVWH tEHDX tEHGL tWLEL tEHWH tELEH tEHEL tGHEL tPHHEH tQVPH
Write cycle time Address set-up time Address hold time Data set-up time Data hold time F-OE# hold from F-CE# high Latency between Read Write Write enable set-up time Write enable hold time F-CE# pulse width F-CE# pulse width high F-OE# hold F-CE# Block Lock set-up write enable high Block Lockhold from valid Duration auto-program operation
tEHRH1 tEHRH2 Duration auto-block erase operation tEHRL F-CE# high F-RY/BY# tPHWL F-RP# high recovery write enable
Read timing parameters during command write operation mode same during read-only operation mode. Typical values F-Vcc=3.3V, Ta=25°C
Erase Program Performance
Parameter Block Erase Time Main Block Write Time (Page Mode) Page Write Time Unit
Program Suspend Latency Erase Suspend Time
Parameter Program Suspend Latency Erase Suspend Time
Please page
Unit
Power Down Timing
Symbol tVCS
Please page During power up/down, noise pulses control pins, device possibility accidental erasure programming. device must protected against initiation write cycle memory contents during power up/down. delay time min.2µsec always required before read operation write operation initiated from time F-Vcc reaches F-Vccmin during power up/down. holding F-RP# VIL, contents memory protected during F-Vcc power up/down. During power F-RP# must held min.2µs from time F-Vcc reaches F-Vccmin. During power down, F-RP# must held until reaches GND. F-RP# doesn't have latch mode ,therefore F-RP# must held during read operation erase/program operation.
Parameter F-RP# =VIH set-up time from Vccmin
Unit
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
POWER DOWN TIMING
Read /Write Inhibit Read /Write Inhibit Read /Write Inhibit
F-VCC
3.3V tVCS
F-RP#
F-CE#
F-WE#
WAVEFORMS READ OPERATION TEST CONDITIONS
ADDRESSES
ADDRESS VALID
TEST CONDITIONS CHARACTERISTICS Input voltage 3.0V Input rise fall times Reference voltage timing measurement 1.5V Output load 1TTL gate CL(30pF)
(AD) (CE) tDF(CE)
F-CE#
F-OE#
tOEH (OE) tOLZ HIGH-Z tCLZ tDF(OE) HIGH-Z
F-WE#
DATA
1.3V 1N914 3.3k =30pF
OUTPUT VALID
F-RP#
tPHZ
WAVEFORMS WRITE READ OPERATION
ADDRESSES
ADDRESS VALID
(AD) (CE) (OE)
F-CE#
tDF(CE)
F-OE#
tDF(OE)
HIGH-Z
F-WE#
tOLZ tCLZ
OUTPUT VALID
DATA
HIGH-Z
Valid
F-RP#
tPHZ
case F-CE# fixed, allowed define timming specification from rising edge F-WE# falling edge F-OE#, valid data read after spec tRE+ta(CE). (This only FFH,71H program read)
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) WAVEFORMS PAGE PROGRAM OPERATION (F-WE# control)
F-A19~F-A17, A16~A7 F-CE# F-OE# F-WE# DATA F-RY/BY# F-RP# F-WP# tBLS tBLH
VALID 01H~7EH other bank address
BANK ADDRESS VALID
PROGRAM
READ STATUS WRITE READ REGISTER ARRAY COMMAND
VALID
VALID
ADDRESS VALID
BANK ADDRESS VALID
tWPH
ta(CE)
ta(CE) ta(OE)
tOEH
tGHWL ta(OE)
tOEH tDAP
DOUT
tWHRL
WAVEFORMS PAGE PROGRAM OPERATION (F-CE# control)
F-A19~F-A17, A16~A7 F-CE# F-OE# F-WE# DATA F-RY/BY# F-RP# F-WP# tBLS tBLH
other bank address
BANK ADDRESS VALID
PROGRAM
READ STATUS WRITE READ REGISTER ARRAY COMMAND
VALID
VALID
ADDRESS VALID
BANK ADDRESS VALID
VALID
01H~7EH
tCEPH
ta(CE) ta(OE) tOEH tGHEL tOEH tDAP
ta(CE) ta(OE)
tCEP
DOUT
tEHRL
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
WAVEFORMS WORD PROGRAM OPERATION (F-WE# control) only BANK(I))
PROGRAM
BANK ADDRESS VALID
ADDR F-CE# F-OE# F-WE# DATA F-RY/BY# F-RP# F-WP#
READ STATUS REGISTER
WRITE READ ARRAY COMMAND
ADDRESS VALID
BANK(I) ADDRESS VALID
ta(CE) ta(OE) tOEH
tWPH
tWHRL tDAP
tBLS tBLH
WAVEFORMS WORD PROGRAM OPERATION (F-CE# control)
PROGRAM
BANK ADDRESS VALID
only BANK(I))
WRITE READ ARRAY COMMAND
ADDR F-CE# F-OE# F-WE# DATA F-RY/BY# F-RP#
READ STATUS REGISTER
ADDRESS VALID
BANK(I) ADDRESS VALID
ta(CE) ta(OE)
tCEP
tOEH
tEHRL tDAP
tBLS tBLH
F-WP#
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
WAVEFORMS ERASE OPERATIONS (F-WE# control)
ADDRESSES
ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
F-CE# F-OE# F-WE#
BANK ADDRESS VALID
ADDRESS VALID
BANK ADDRESS VALID
ta(CE)
tOEH tDAE
ta(OE)
tWPH
DATA
tBLS
tWHRL
F-RY/BY#
F-RP#
tBLH
F-WP#
WAVEFORMS ERASE OPERATIONS (F-CE# control)
ERASE
ADDRESSES
READ STATUS REGISTER
WRITE READ ARRAY COMMAND
F-CE#
BANK ADDRESS VALID
ADDRESS VALID
BANK ADDRESS VALID
ta(CE)
tCEP F-OE# F-WE# DATA
tCEPH tOEH
ta(OE)
tDAE
tEHRL
F-RY/BY#
F-RP#
tBLS tBLH
F-WP#
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) WAVEFORMS PAGE PROGRAM OPERATION WITH (F-WE# control)
Change Bank Address PROGRAM DATA BANK
F-A19~F-A17, A16~A7 F-CE# F-OE# F-WE# DATA F-RY/BY#
ARRAY READ FROM OTHER BANK WITH
BANK ADDRESS VALID
ADDRESS VALID
VALID
VALID
01H~7EH
VALID
VALID
tWPH
ta(CE) ta(OE) tOEH
DOUT
DOUT
tWHRL
WAVEFORMS PAGE PROGRAM OPERATION WITH (F-CE# control)
Change Bank Address PROGRAM DATA BANK
F-A19~F-A17, A16~A7
ARRAY READ FROM OTHER BANK WITH
BANK ADDRESS VALID
ADDRESS VALID
VALID
VALID
01H~7EH
VALID
VALID
tCEPH
ta(CE) ta(OE) tOEH
F-OE#
tCEP
DATA F-RY/BY#
F-WE#
F-CE#
DOUT
DOUT
tEHRL
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
WAVEFORMS WORD PROGRAM OPERATION WITH (F-WE# control)
Change Bank Address PROGRAM DATA BANK(I)
BANK ADDRESS VALID
F-A19~F-A17, A16~A7 F-CE# F-OE# F-WE# DATA F-RY/BY#
READ STATUS REGISTER
ARRAY READ FROM BANK(II) WITH
ADDRESS VALID
VALID
VALID
VALID
VALID
VALID
tWPH
ta(CE) ta(OE)
tOEH
DOUT DOUT
tWHRL
WAVEFORMS WORD PROGRAM OPERATION WITH (F-CE# control)
PROGRAM DATA BANK(I)
BANK ADDRESS VALID
F-A19~F-A17, A16~A7
READ STATUS REGISTER
Change Bank Address ARRAY READ FROM BANK(II) WITH
ADDRESS VALID
VALID
VALID
VALID
VALID
VALID
tCEPH
ta(CE) ta(OE) tOEH
F-CE#
F-OE#
tCEP
F-WE#
DOUT DOUT
DATA F-RY/BY#
tEHRL
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
WAVEFORMS BLOCK ERASE OPERATION WITH (F-WE# control)
Change Bank Address BLOCK ERASE BANK
BANK ADDRESS VALID
ADDRESSES F-CE# F-OE# F-WE# DATA F-RY/BY#
READ STATUS REGISTER
ARRAY READ FROM OTHER BANK WITH
ADDRESS VALID
VALID
VALID
tWPH tOEH
ta(CE) ta(OE)
DOUT DOUT
tWHRL
WAVEFORMS BLOCK ERASE OPERATION WITH (F-CE# control)
Change Bank Address BLOCK ERASE BANK
BANK ADDRESS VALID
ADDRESSES F-OE# F-WE# DATA F-RY/BY#
READ STATUS REGISTER
READ DATA FROM OTHER BANK WITH
ADDRESS VALID
VALID
VALID
F-CE#
tCEPH
ta(CE) ta(OE)
tCEP
tOEH
DOUT DOUT
tEHRL
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
WAVEFORMS SUSPEND OPERATION (F-WE# control)
ADDRESSES
READ STATUS REGISTER
F-CE#
BANK ADDRESS VALID
BANK ADDRESS VALID
ta(CE)
F-OE# F-WE# DATA
tOEH Program Suspend Latency
ta(OE)
S.R.6,7=1
VALID
tBLS tBLH
F-RY/BY#
F-RP#
F-WP#
WAVEFORMS SUSPEND OPERATION (F-CE# control)
ADDRESSES BANK ADDRESS VALID
READ STATUS REGISTER
F-CE# F-OE# F-WE# DATA
BANK ADDRESS VALID
tCEP
ta(CE)
ta(OE) tOEH Program Suspend Latency S.R.6,7=1
VALID
tBLS tBLH
F-RY/BY#
F-RP#
F-WP#
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) FULL STATUS CHECK PROCEDURE
STATUS REGISTER READ
LOCK PROGRAM FLOW CHART
START
SR.4 SR.5
WRITE COMMAND SEQUENCE ERROR WRITE BLOCK ADDRESS
SR.5
BLOCK ERASE ERROR SR.7
SR.4
PROGRAM ERROR (PAGE, LOCK BIT) SR.4
LOCK PROGRAM FAILED
SR.3 SUCCESSFUL (BLOCK ERASE, PROGRAM)
PROGRAM ERROR (BLOCK)
LOCK PROGRAM SUCCESSFUL
BYTE PROGRAM FLOW CHART
START
PAGE PROGRAM FLOW CHART
START
WRITE WRITE
WRITE ADDRESS DATA
STATUS REGISTER READ
WRITE ADDRESS DATA
SR.7
WRITE
STATUS REGISTER READ
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
SR.7 WRITE
PAGE PROGRAM COMPLETED
Word program admitted only BANK(I).
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
PAGE PROGRAM COMPLETED
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) CLEAR PAGE BUFFER
START
SUSPEND RESUME FLOW CHART
START
WRITE WRITE STATUS REGISTER READ WRITE SR.7 PAGE BUFFER CLEAR COMPLETED
SUSPEND
SR.6
SINGLE DATA LOAD PAGE BUFFER
START WRITE
PROGRAM ERASE COMPLETED
WRITE
READ ARRAY DATA
WRITE ADDRESS DATA
DONE READING
DONE LOADING?
WRITE
RESUME
SINGLE DATA LOAD PAGE BUFFER COMPLETED
OPERATION RESUMED
bank address required when writing this command. Also, there need suspend erase program operation when reading data from other bank. Please function.
PAGE BUFFER FLASH
START
BLOCK ERASE FLOW CHART
START
WRITE WRITE WRITE BLOCK ADDRESS WRITE PAGE ADDRESS STATUS REGISTER READ STATUS REGISTER READ
SR.7 WRITE SR.7
WRITE
FULL STATUS CHECK DESIRED
FULL STATUS CHECK DESIRED
SUSPEND LOOP WRITE
SUSPEND LOOP WRITE
PAGE BUFFER FLASH COMPLETED
BLOCK ERASE COMPLETED
Apr. 1999 Rev.1.7
OPERATION STATUS EFFECTIVE COMMAND
Clear Status Register
Read/Standby State Read Status Register
Read Device Identifier
Read Lock Status
Read Array
Setup State Clear Page Buffer Setup
Single Data Load Page Buffer Setup
Page Buffer Flash Setup
Page Program Setup
Byte Program Setup
Lock Program Setup
Block Erase Setup
Erase Unlocked Blocks Setup
OTHER
OTHER
Internal State
i=0-127
OTHER
OTHER
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
Program Verify
Ready
Erase Verify Read Status Register
Read Status Register
M6MGB/T166S4BWG
Suspend State
Change Bank Address
Read Status Register
Change Bank Address
Apr. 1999 Rev.1.7
Read State with Read Array
(From Other Bank)
Read Array
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
SRAM
SRAM M6MGB/T166S4BWG organized 262,144-word 16-bit. These devices operate single +2.7~3.6V powersupply, directly compatible both input output. fully static circuit needs clocks refresh, makes useful. operation mode determined combination device control inputs S-LB#,S-UB#,S-CE1#,S-CE2, S-WE# S-OE#. Each mode summarized function table. write operation executed whenever level S-WE# overlaps with level S-LB# and/or S-UB# level S-CE1#the high level S-CE2. address A0~A16,SA-17 must before write cycle must stable during entire cycle. read operation executed setting S-WE# high level S-OE# level while S-LB# and/or S-UB# S-CE1# S-CE2 active state(S-CE1#=L,S-CE2=H). When setting S-LB# high level other pins active stage, upper-byte selectable mode which both reading writing enabled, lower-byte non-selectable mode. when setting S-UB# high level other pins active stage, lower-byte selectable mode upper-byte non-selectable mode. When setting S-LB# S-UB# high level S-CE1# high level S-CE2 level, chips nonselectable mode which both reading writing disabled. this mode, output stage highimpedance state, allowing OR-tie with other chips memory expansion S-LB#,S-UB# S-CE1#,S-CE2. power supply current reduced 0.3µA(25°C,typical), memory data held powersupply, enabling battery back-up operation during power failure power-down operation non-selected mode.
FUNCTION TABLE
S-CE1# S-CE2 S-LB# S-UB# S-WE# S-OE# Write Read Mode
selection selection selection selection
DQ0~7
DQ8~15
Standby Standby Standby Standby Active Active Active Active Active Active Active Active Active
High-Z High-Z High-Z High-Z Dout High-Z High-Z High-Z High-Z Dout High-Z
High-Z High-Z High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z
Write Read Write Read
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
ABSOLUTE MAXIMUM RATINGS
Symbol
S-Vcc Tstg
Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature
Conditions With respect With respect With respect Ta=25°C W-version
Ratings
Units
-0.5* +4.6 -0.5* S-Vcc S-Vcc +85°C +150°C
-3.0V case (Pulse width= 30ns)
ELECTRICAL CHARACTERISTICS
Symbol Parameter High-level input voltage Low-level input voltage High-level output voltage IOH= -0.5mA High-level output voltage IOH= -0.05mA Low-level output voltage Input leakage current Output leakage current Conditions
S-Vcc=2.7 3.6V, unless otherwise noted) Limits
S-Vcc+0.3V
Units
VOH1 VOH2
-0.3
S-Vcc-0.5V
IOL=2mA S-Vcc
S-LB# S-UB#=VIH S-CE1#=VIH S-CE2=VIH S-OE#=VIH, VI/O=0 S-Vcc
S-LB# S-UB# 0.2V,S-CE1# 0.2V, S-CE2 S-Vcc-0.2V other inputs 0.2V S-Vcc-0.2V Output-open(duty 100%) S-LB# S-UB#=VIL,S-CE1#=VIL, S-CE2=VIH other inputs=VIH Output-open(duty 100%)
Icc1 Active supply current
AC,MOS level
10MHz 1MHz 10MHz 1MHz
Icc2
Active supply current AC,TTL level
Icc3
Stand supply current AC,MOS level
S-CE2 0.2V Other inputs=0~S-Vcc
Icc4 Stand supply current
AC,TTL level
S-LB# S-UB#=VIH S-CE1#=VIH S-CE2=VIL Other inputs= S-Vcc
Note Direction current flowing into indicated positive mark) Note Typical value S-Vcc=3.0V Ta=25°C
-3.0V case (Pulse width< 30ns)
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
(S-Vcc=2.7 3.6V, unless otherwise noted) Limits Units
Note: value common pins SRAM Flash Memory SRAM.
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
ELECTRICAL CHARACTERISTICS TEST CONDITIONS
Supply voltage Input pulse Input rise time fall time Reference level
(S-Vcc=2.7 3.6V, unless otherwise noted)
2.7V~3.6V VIH=2.4V, VIL=0.4V VOH=VOL=1.5V
Transition measured 500mV from steady state voltage.(for ten,tdis)
1TTL
Including scope capacitance
Output loads
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Fig.1 Output load
READ CYCLE
Limits Symbol ta(A) ta(CE1) ta(CE2) ta(LB) ta(UB) ta(OE) tdis(CE1) tdis(CE2) tdis(LB) tdis(UB) tdis(OE) ten(CE1) ten(CE2) tdis(LB) tdis(UB) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select access time Chip select access time Lower Byte control access time Upper Byte control access time Output enable access time Output disable time after S-CE1# high Output disable time after S-CE2 Output disable time after S-LB# high Output disable time after S-UB# high Output disable time after S-OE high Output enable time after S-CE1# Output enable time after S-CE2 high Output enable time after S-LB# Output enable time after S-UB# Output enable time after S-OE Data valid time after address
SRAM
Units
WRITE CYCLE
Limits Symbol Parameter Write cycle time Write pulse width Address setup time Address setup time with respect S-WE# Lower Byte control setup time Upper Byte control setup time Chip select setup time Chip select setup time Data setup time Data hold time Write recovery time Output disable time from S-WE# Output disable time from S-OE# high Output enable time from S-WE# high Output enable time from S-OE#
SRAM
Units
tw(W) tsu(A) tsu(A-WH) tsu(LB) tsu(UB) tsu(CE1) tsu(CE2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE)
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
(4)TIMING DIAGRAMS Read cycle
A0~16, S-A17 ta(A) ta(LB) S-LB#, S-UB#
(Note3)
ta(UB)
tdis (LB) tdis (UB) ta(CE1)
(Note3)
S-CE1#
(Note3)
tdis (CE1) ta(CE2)
(Note3)
S-CE2
(Note3)
tdis (CE2) (OE)
(Note3)
S-OE#
(Note3) S-WE# level
(OE) (LB) (UB) (CE1) (CE2)
tdis (OE)
(Note3)
DQ0~15
VALID DATA
Write cycle (S-WE# control mode)
A0~16, S-A17
(LB) tsu(UB) S-LB#, S-UB#
(Note3) (Note3)
S-CE1#
(Note3)
(CE1)
(Note3)
S-CE2
(Note3)
(CE2)
(Note3)
S-OE# S-WE# tdis(OE) DQ0~15
(A-WH) tdis
trec ten(OE)
DATA STABLE
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
Write cycle (S-LB#,S-UB# control mode)
A0~16, S-A17 S-LB#, S-UB# S-CE1#
(Note3) (Note3)
(LB) tsu(UB)
trec
S-CE2
(Note3) (Note5) (Note4) (Note3) (Note3)
S-WE#
DATA STABLE
(Note3)
DQ0~15
Note Hatching indicates state "don't care". Note Write occurs during S-CE1# low, S-CE2 high overlaps S-LB# and/or S-UB# low. Note When falling edge S-WE# simultaneously prior falling edge S-LB# and/or S-UB# falling edge S-CE1# rising edge S-CE2, outputs maintained high impedance state. Note Don't apply inverted phase signal externally when output mode.
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
Write cycle (S-CE1# control mode)
A0~16, S-A17 S-LB#, S-UB#
(Note3)
(CE1)
trec
(Note3)
S-CE1#
S-CE2
(Note3) (Note5) (Note3)
S-WE#
(Note3)
(Note4)
DATA STABLE
(Note3)
DQ0~15
Write cycle (S-CE2 control mode)
A0~16, S-A17 S-LB#, S-UB#
(Note3)
(CE2)
trec
(Note3)
S-CE1#
S-CE2
(Note3) (Note5) (Note3)
S-WE#
(Note3)
(Note4)
DATA STABLE
(Note3)
DQ0~15
Apr. 1999 Rev.1.7
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD 16-BIT CMOS 3.3V-ONLY FLASH MEMORY 4,194,304-BIT (262,144-WORD 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package)
POWER DOWN CHARACTERISTICS ELECTRICAL CHARACTERISTICS
Symbol Parameter Test conditions Limits Units
S-Vcc (PD) Power down supply voltage
(S-BC)
Byte control input S-LB#,S-UB#
(S-CE1#) Chip select input S-CE1# (S-CE2) Chip select input S-CE2 (PD) Power down supply current
S-Vcc=3.0V S-CE2 0.2V other inputs=0~3V
Typical value Ta=25°C
TIMING REQUIREMINTS
Symbol Limits Parameter Power down time Power down recovery time Test conditions Units
(PD) trec (PD)
TIMING DIAGRAM
S-LB#,S-UB# control mode S-Vcc (PD) S-LB#, S-UB# 2.2V S-LB#,S-UB# (S-Vcc) 0.2V 2.7V 2.7V trec (PD) 2.2V
S-CE1# control mode S-Vcc (PD) S-CE1# 2.2V S-CE1# (S-Vcc) 0.2V 2.7V 2.7V trec (PD) 2.2V
S-CE2 control mode S-Vcc 2.7V 2.7V
S-CE2
0.2V (PD) S-CE2 0.2V trec (PD)
0.2V
Apr. 1999 Rev.1.7
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