PM73123 AAL1GATOR-8 PM4354 COMET-QUAD AAL1GATOR-8 REFERENCE DESIG

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PM73123 AAL1GATOR-8 PM4354 COMET-QUAD AAL1GATOR-8 REFERENCE DESIG

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PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
PM73123
AAL1GATOR-8
REFERENCE DESIGN
PRELIMINARY ISSUE JUNE 2001
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PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
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PUBIC REVISION HISTORY Issue Issue Date Details Change December 1999 June 2001 Document created. Updated COMET-QUAD decoupling (C4, C14, C21, C42, C49, C56, C65) schematics corrected power sequencing description. Updated power calculations.
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CONTENTS INTRODUCTION. PURPOSE. SCOPE. APPLICATIONS
GENERAL DESCRIPTION. AAL1GATOR-8 ARCHITECTURE
FEATURES HIGH LEVEL DESIGN BLOCK DESCRIPTION 5.10 5.11 5.12 5.13 AAL1GATOR-8. COMET COMET-QUAD MICROPROCESSOR INTERFACE BLOCK AAL1GATOR-8 COMET/COMET-QUADS INTERCONNECTIONS FPGA BLOCK AAL1GATOR-8'S SRAM REGULATORS BLOCK. BLOCKS. RESET BLOCK JTAG PORT TIMING BLOCK. UTOPIA INTERFACE
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DESIGN ISSUES AAL1GATOR-8 DESIGN CONSIDERATIONS 6.1.1 POWER SUPPLY 6.1.2 DECOUPLING 6.1.3 LINE MODE SELECTION. LINE TERMINATION COMET DESIGN CONSIDERATIONS. 6.3.1 POWER SUPPLY 6.3.2 DECOUPLING 6.3.3 VOLTAGE REFERENCES. COMET-QUAD DESIGN CONSIDERATIONS 6.4.1 POWER SUPPLY SEQUENCING 6.4.2 DECOUPLING 6.4.3 VOLTAGE REFERENCES. MICROPROCESSOR INTERFACE POWER REQUIREMENTS.
IMPLEMENTATION DESCRIPTION AAL1GATOR-8 WITH COMET SCHEMATICS AAL1GATOR-8 WITH COMET-QUAD SCHEMATICS
GLOSSARY DEFINITIONS REFERENCES. DISCLAIMER APPENDIX BILL MATERIALS (COMET VERSION)
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APPENDIX BILL MATERIALS (COMET-QUAD VERSION). APPENDIX AAL1GATOR-8 W/COMETS SCHEMATICS APPENDIX AAL1GATOR-8 W/COMET-QUADS SCHEMATICS.
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LIST FIGURES FIGURE AAL1GATOR-8 CONFIGURATIONS FIGURE AAL1GATOR-8 COMETS FIGURE AAL1GATOR-8 COMET-QUADS. FIGURE AAL1GATOR-8 DESIGN BLOCK DIAGRAM WITH COMETS FIGURE AAL1GATOR-8 DESIGN DIAGRAM WITH COMET-QUADS FIGURE GLUELESS AAL1GATOR-8 COMETS CONNECTION.11 FIGURE GLUELESS AAL1GATOR-8 COMET-QUADS CONNECTION
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LIST TABLES TABLE TABLE TABLE TABLE TABLE TABLE TABLE AAL1GATOR-8 COMET/COMET-QUAD CONNECTIONS OSCILLATORS AAL1GATOR-8'S UTOPIA OPERATING MODES INTERFACE PINOUT AAL1GATOR-8 W/COMETS. INTERFACE PINOUT AAL1GATOR-8 W/COMET-QUADS. ADDRESS SPACE AAL1GATOR-8 W/COMETS ADDRESS SPACE AAL1GATOR-8 W/COMET-QUADS
TABLE POWER CONSUMPTION AAL1GATOR-8 W/COMETS TABLE POWER AAL1GATOR-8 W/COMET-QUADS TABLE MAJOR COMPONENTS LIST TABLE MAJOR COMPONENTS LIST
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INTRODUCTION AAL1gator-8 Reference Design assists customers designing Circuit Emulation Service (CES) and/or Dynamic Bandwidth Circuit Emulation Service (DBCES) card. CES/DBCES card used emulate circuit oriented transmission characteristics support Constant Rate (CBR) traffic.
PURPOSE This reference design will assist engineers designing their products using PMC-Sierra's AAL1gator-8, COMET COMET-QUAD devices thereby bringing customers' designs market earlier.
SCOPE This document paper reference design describes scope deliverables required AAL1gator-8 Reference Design. Note that design actually built tested, only been designed paper. This reference design modularized card with design options: AAL1gator-8, COMET-QUADs, microprocessor interface, line interfaces. AAL1gator-8, eight COMETs, microprocessor interface, line interfaces. block diagram shown designs. Descriptions provided each functional blocks detailed implementation descriptions then follow.
APPLICATIONS Emulating existing circuits essential function Aswitches. Currently circuits provide most voice data services therefore seamless interaction between Ahas become system requirement. AForum standardized internetworking function that satisfies this requirement called Circuit Emulation Services (CES) Specification. following some application examples AAL1gator-8 Reference Design: 8-Link T1/E1 Cards
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AAccess Service Concentrator Part AMultiservice ASwitch
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GENERAL DESCRIPTION AAL1gator-8 Architecture purpose AAL1gator-8 provide high density T1/E1, DS3/E3/J2 line interfaces access AAL1 Anetwork. AAL1gator-8 support T1/E1 lines, DS3/E3/STS-1 link 8Mbps H-MVIP links. AAL1gator-8 capable supporting VCs. system side, AAL1gator-8 supports standard UTOPIA Level interface that optionally supports parity runs MHz. optional 8/16-bit Any-PHY slave interface UTOPIA Level master/slave interface also supported system side. Figure indicates ways which AAL1gator-8 used connect T1/E1 DS3/E3 line interfaces. Figure AAL1gator-8 Configurations
Any-PHY UTOPIA
AAL1gator-8
Structured unstructured T1/E1 with support MVIP Switch Unstructured DS3/E3
T1/E1 Framer (TQUAD/EQUAD) T1/E1 Framer+LIU (COMET) (COMET-Q)
DS3/E3 Framer (S/UNI-QJET)
T1/E1 (QDSX)
(D3MX)
DS3/E3
Figures show system context which AAL1gator-8 devices reside within reference designs. these designs each AAL1gator-8 interface with eight COMETs COMET-QUADs support structured/unstructured E1s.
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PM4351 COMET single channel combined E1/T1 transceiver framer, PM4354 COMET-QUAD four channel combined E1/T1 transceiver framer both devices capable long short haul systems with minimum external circuitry. When used with COMETs COMET-QUADs, AAL1gator-8 part multiservice switch application which provide circuit emulation services pipes. Figure AAL1gator-8 COMETs
Data Clock Lines
Line Interface
PM4351 COMET
Line Interface
PM4351 COMET PM4351 COMET PM73123 AAL1gator-8
UTOPIA AnyPHY
Line Interface
Line Interface
PM4351 COMET PM4351 COMET
Line Interface
Line Interface
PM4351 COMET PM4351 COMET
Line Interface
Line Interface
PM4351 COMET
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Figure
AAL1gator-8 COMET-QUADs
Data Clock Lines
PM4354 COMET-QUAD
PM73123 AAL1gator-8
UTOPIA AnyPHY
PM4354 COMET-QUAD
COMETs COMET-QUADs receive data through T1/E1 line interfaces. formatted data then passed through T1/E1 framers AAL1gator-8 servicing. cells then routed through UTOPIA connector routing, switching, traffic policing shaping. transmit path, AAL1gator-8 receives Acells from UTOPIA bus. AAL1gator-8 retrieves data signaling information, places data transmitted over lines COMETs COMETQUADs appropriate port time slot.
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FEATURES Implementation strategy AAL1gator-8 Multi Service Access Concentrator environment using PM4351 COMET PM4354 COMETQUAD. Supports T1/E1 rates channelized mode. Supports CES. Supports independently clocked links. microprocessor interface configuration monitoring.
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HIGH LEVEL DESIGN block diagrams AAL1gator-8 reference design shown Figure Figure Figure illustrates high level design reference design with COMET devices while Figure shows high level design with COMET-QUAD devices.
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Figure
AAL1gator-8 Design Block Diagram with COMETs
Microprocessor Interface Address Control
Reset Switch
Data
Regulators
Memory system (Buffers/XCVRs, Decode Logic) Power LEDs
Address, Data Control Oscillators
RXRING1 RXTIP1 TXRING1 &TXTIP1
PM4351 COMET
FPGA
RXRING2 RXTIP2 TXRING2 &TXTIP2
PM4351 COMET
128Kx16 PM4351 COMET
RXRING3 RXTIP3 TXRING3 &TXTIP3
Data clock Lines
RXRING4 RXTIP4 TXRING4 &TXTIP4
PM4351 COMET
PM73123 AAL1gator-8
UTOPIA
UTIOPA Connect
Line Interface
RXRING5 RXTIP5 TXRING5 &TXTIP5
PM4351 COMET
RXRING6 RXTIP6 TXRING6 &TXTIP6
PM4351 COMET
RXRING7 RXTIP7 TXRING7 &TXTIP7
PM4351 COMET
AAL1gator-8 ALARM LEDs
RXRING8 RXTIP8 TXRING8 &TXTIP8
PM4351 COMET
COMET ALARMS LEDs
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Figure
AAL1gator-8 Design Diagram with COMET-QUADs
Microprocessor Interface Address Control Reset Switch
Data
Regulators
Memory system (Buffers/XCVRs, Decode Logic) Power LEDs
Address, Data Control Oscillators
RXRING[4:1] RXTIP[4:1] TXTIP[4:1] TXRING[4:1] PM4354 COMET-QUAD FPGA 128Kx16
Line Interface
Data clock Lines
PM73123 AAL1gator-8
UTOPIA
UTIOPA Connect
TXRING[8:5] TXTIP[8:5] RXTIP[8:5] RXRING[8:5] PM4354 COMET-QUAD
COMET-QUAD ALARMS LEDs
AAL1gator-8 ALARM LEDs
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illustrated, designs contain following functional blocks: PM73123 AAL1gator-8 PM4351 COMET/PM4354 COMET-QUAD Microprocessor Memory System Interface Field Programmable Gate Array (FPGA) Line Interface UTOPIA Interface Power Clock Sources hardware allows full access AAL1gator-8 COMET/COMET-QUAD devices microprocessor interface. Each COMET device acts single line interface unit with integrated long haul LIU, T1/E1 framer/deframer while each COMET-QUAD device acts four line interface units with integrated long haul LIUs, T1/E1 framers/de-framers. receive path (from line), COMET COMET-QUAD converts incoming line data form channels) serial stream. AAL1gator-8 then receives this data clocking information builds AAL1 cells sent UTOPIA bus. transmit path line), AAL1gator-8 receives Acells from UTOPIA bus. AAL1gator-8 retrieves data signaling information, places data transmitted over lines COMETs/COMET-QUADs appropriate port time slot. illustrated both Figure Figure connections from FPGA PMC's devices dotted lines. This because possible connect AAL1gator-8 COMETs COMET-QUADs directly (i.e. without using FPGA). Figure shows direct connection between AAL1gator-8 COMETs while Figure illustrates this glueless interconnection between AAL1gator-8 COMET-QUADs.
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Figure
Glueless AAL1gator-8 COMETs Connection
Optional External Clock Source
BTCLK[7.0] BTSIG[7.0]
TL_CLK[7.0] TL_SIG[7.0]
COMET Blocks
BTFP[7.0]
PM73123 AAL1gator-8
TL_SYNC[7.0]
Figure
Glueless AAL1gator-8 COMET-QUADs Connection
Optional External Clock Source
BTCLK[4.1] BTSIG[4.1]
PM4354 COMET-QUAD
TL_CLK[7.0] TL_SIG[7.0]
BTFP[4.1]
PM73123 AAL1gator-8
BTFP[4.1] TL_SYNC[7.0]
PM4354 COMET-QUAD
BTSIG[4.1] BTCLK[4.1]
AAL1gator-8 also supports 8Mbit/s H-MVIP line interface, COMET-QUAD also supports 8Mbit/s H-MVIP system interface.
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Therefore, H-MVIP interface optionally provided AAL1gator-8 with COMET-QUAD Reference design. main purpose FPGA provide maximum clock distribution flexibility allowing independently clocked links. AAL1gator-8 capable implementing SRTS Adaptive Clock Recovery algorithm own; however, using FPGA possible implement external Adaptive Clock Recovery scheme SRTS clock scheme. FPGA also used generation TL_CLK (AAL1gator-8) BTCLK (COMET COMET-QUAD). addition, FPGA generates appropriate signal AAL1gator-8 network clock pin, N_CLK, 2.43 MHz), also distributes XCLK signals COMET COMET-QUAD devices from only clock oscillators: 1.544 2.048 MHz. H-MVIP mode, FPGA used distribute 16.384 clock AAL1gator-8's C16B COMET-QUADs' CMV8MCLK input pins. FPGA also used distribute 4.096 Frame Pulse Clock AAL1gator-8's COMET-QUADs' CMVPFC inputs, generate Common H-MVIP Frame Pulse from Frame Pulse Clock. addition, both Figures TL_SYNC pins AAL1gator-8 connected COMET BTFP COMET-QUAD BTFP pins (configured outputs). Depending value MF_SYNC_MODE LI_CFG_REG register AAL1gator-8 line, this allows alignment signaling bits multiframe boundaries frame boundary. Power requirements boards +5.0V, +3.3V +2.5V. AAL1gator8 COMET-QUADs require +3.3V +2.5V while COMETs require only +3.3V. +5.0V used input COMETs' BIAS pins generate +3.3V +2.5V using voltage regulators. this reference design, AAL1gator-8, COMET COMET-QUAD devices configured with de-multiplexed microprocessor address data bus. microprocessor interface been provided through 96-pin connector. This interface provides configuration monitoring PMC-Sierra's devices. memory sub-unit AAL1gator-8's block contains 128k SRAM module connected AAL1gator-8 device's interface. 80-pin female UTOPIA connectors carry receive transmit UTOPIA signals between AAL1gator-8 external board Parallel Cell Traffic Generator Analyzer. designs also include several circuits device alarms power indications.
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BLOCK DESCRIPTION AAL1gator-8 AAL1 Segmentation Reassembly (SAR) Processor (AAL1gator-8) monolithic single chip device that provides DS1, line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external (128K 16/18 bits) 10ns SRAM storage configuration, user data, statistics. Some device's important functionality follows: Compliant with AForum's Circuit Emulation Services (CES) specification (AF-VTOA-0078), ITU-T I.363.1 Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with AForum's DBCES specification (AF-VTOA-0085). Supports idle channel detection processor intervention, signaling, data pattern detection. Provides idle channel indication channel basis. Provides AAL1 segmentation reassembly individual lines, H-MVIP lines 8Mbit/s, line. Provides standard 16/8 bits UTOPIA level Interface which optionally supports parity runs MHz. following modes supported: 16-bit Level Multi-Phy Mode (MPHY) 8-bit Level MPHY 8-bit Level SPHY 8-bit Level AMaster
Supports Virtual Channels (VC).
AAL1gator-8 configured, controlled monitored generic 8-bit microprocessor through which internal registers accessed. sources interrupts masked acknowledged through microprocessor interface.
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this reference design, AAL1gator-8 configured with direct mode line interface connect COMETs COMET-QUADs. line mode operation needs setup from hardware reset cannot changed once chip powered line mode controlled AAL1gator-8's LINE_MODE pin. When LINE_MODE using provided jumpers AAL1gator-8 will support speed lines, high speed line, interface with COMET COMET-QUAD devices. When LINE_MODE high, AAL1gator-8 will H-MVIP mode when interfacing COMET-QUADs. This mode provided extra optional interface ignored. UTOPIA interface AAL1gator-8 will power with outputs tri-stated will remain tri-stated until UI_EN UI_COMN_CFG register set. Also, during hardware configuration AAL1gator-8, TL_CLK_OE signal tied high clock provided RL_CLK TL_CLK will drive this clock externally. When chip taken hardware reset, internal SYSCLK, which used maintain skew interface, will into hunt mode will adjust internal SYSCLK until aligns with external SYSCLK. microprocessor should poll DLL_STAT_REG register until this set. this point, entire chip with exception microprocessor interface reset. Before configuration done, including accessing RAM, chip must taken software reset clearing SW_RESET DEV_ID_REG register. Then, should cleared zeros. this point, A1SP block still reset because SW_RESET CMD_REG register still set. line interface configured direct speed mode indicated LINE_MODE pins internal registers reset state. line interface reset this point will only driving data lines and/or queues disabled. UTOPIA interface, mentioned above, disabled UTOPIA outputs tri-stated. software configuration AAL1gator-8 done three steps: Line Configuration: while A1SP reset, memory mapped registers which contain line configuration (the LIN_STR_MODE HS_LIN_REG registers) initialized. Then, CMD_ATTN CMD_REG register that A1SP read configuration. SW_RESET CMD_REG register should remain set. Queue Configuration: SW_RESET CMD_REG register cleared which takes A1SP reset. R_CHAN_2_QUE_TBL will then
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begin SYSCLK cycle initialization, which reset each timeslot playing conditioned data. this point, queues initialized needed. Adding Queues: setting corresponding bits ADDQ_FIFO register, queues added. more detailed description AAL1gator-8, please refer [1]. COMET PM4351 Combined E1/T1 Transceiver (COMET) feature-rich monolithic integrated circuit suitable long haul short haul systems with minimum external circuitry. COMET software configurable, allowing feature selection without changes external wiring. Analog circuitry provided allow direct reception long haul compatible signals with cable loss 1.024MHz mode) cable loss mode) using minimum external components. Typically, only line protection, transformer line termination resistor required. Digital line inputs provided applications requiring physical interface. COMET recovers clock data from line frames incoming data. mode, frame several DS-1 signal formats: ESF, T1DM (DDS) SLC®96. mode, COMET frames basic G.704 signals CRC-4 multiframe alignment signals, automatically performs G.706 interworking procedure. AMI, HDB3 B8ZS line codes supported. mode, COMET generates framing T1DM (DDS) formats. mode, COMET generates framing basic G.704 signal. signaling multiframe alignment structure multiframe structure optionally inserted. Framing optionally disabled. Internal analog circuitry allows direct transmission long haul short haul compatible signals using minimum external components. Typically, only line protection, transformer line termination resistor required. Digitally programmable pulse shaping allows transmission DSX-1 compatible signals feet from cross-connect, short haul pulses into twisted pair coaxial cable, long haul pulses into twisted pair well long haul DS-1 pulses into twisted pair with integrated support filtering required rules. addition, programmable pulse shape extending over 5-bit periods allows customization short haul long haul line interface circuits application requirements. Digital line inputs outputs provided applications requiring physical interface.
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COMET provides both parallel microprocessor interface controlling operation device serial interfaces that allow backplane rates from 1.544 Mbit/s 8.192 Mbit/s directly supported. this reference design, each COMET interfaces with AAL1gator-8 configured independently mode. After power hardware/software reset, following steps performed configure COMET: Initialize XLPG (Transmit Pulse Template) registers clear pulse template. Setup XLPG program pulse template generate short-haul long-haul pulses specified [2]. Also, amplitude pulse template enable XLPG. Program COMET mode writing E1/T1B Global Configuration register. Configure Clock Synthesis Unit (CSU) selecting 1.544MHz 2.048MHz line rate (XCLK TCLKO). Configure Clock Data Recovery Unit (CDRC) receive appropriate line decoding (AMI B8ZS mode, HDB3 mode). Configure Receive Transmit Elastic Stores units (RX-ELST TXELST). framing format line encoding transmitter (XBAS mode, E1-TRAN mode). Program framing format receiver. Configure framing format data rate facility data link. Configure Signaling Extraction Block register (SIGX). Configure Receive Line Interface (RLPS). Configure Transmit/Receive Jitter Attenuator Receive Option registers disable enable jitter attenuation transmit receive line side. Configure Backplane Receive System Interface (BRIF) block (registers 0x30 0x31):
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Full Frame mode BRCLK output BRPCM, BRSIG, BRFP updated rising edge BRCLK BRCLK backplane rate (1.544MHz 2.048MHz) BRFP (Backplane Frame Pulse) output
Configure Backplane Transmit System Interface (BTIF) block (registers 0x40 0x41): Full Frame mode BRCLK input BTPCM, BTSIG, BTFP updated rising edge BTCLK BTCLK backplane rate (1.544MHz 2.048MHz) BRFP (Backplane Frame Pulse) output
Program Receive Line Equalization table stated [2]. more information about COMET please refer [2]. COMET-QUAD PM4354 Four Channel Combined E1/T1/J1 Transceiver Framer (COMET-QUAD) feature-rich monolithic integrated circuit suitable long haul short haul systems with minimum external circuitry. COMET-QUAD software configurable, allowing feature selection without changes external wiring. Analog circuitry provided allow direct reception long haul T1/J1 compatible signals typically with cable loss 1024 (E1) cable loss (T1/J1) using minimum external components. Typically, only line protection, transformer line termination resistor required. COMET-QUAD recovers clock data from line frames incoming data. mode, frame signal formats.
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mode, COMET-QUAD frames basic G.704 signals CRC-4 multiframe alignment signals, automatically performs G.706 interworking procedure. AMI, HDB3 B8ZS line codes supported. mode, COMET-QUAD generates framing formats. mode, COMET-QUAD generates framing basic G.704 signal. signaling multiframe alignment structure multiframe structure optionally inserted. Framing optionally disabled. Internal analog circuitry allows direct transmission long haul short haul compatible signals using minimum external components. Typically, only line protection, transformer line termination resistor required. Digitally programmable pulse shaping allows transmission DSX-1 compatible signals feet from cross-connect, short haul pulses into twisted pair coaxial cable, long haul pulses into twisted pair well long haul DS-1 pulses into twisted pair with integrated support filtering required rules. addition, programmable pulse shape extending over 5-bit periods allows customization short haul long haul line interface circuits application requirements. Serial interfaces each framer allow 1.544 Mbit/s backplane receive/backplane transmit system interfaces directly supported. Tolerance gapped clocks allows other backplane rates supported with minimum external logic. synchronous backplane systems 8Mbit/s H-MVIP interfaces provided access channel associated signaling (CAS) common channel signaling (CCS) each data channel H-MVIP H-MVIP access multiplexed with serial interface pins. signaling HMVIP interface independent channel H-MVIP access. H-MVIP interfaces requires that common clocks frame pulse used along with T1/E1 slip buffers. COMET-QUAD configured, controlled monitored generic 8-bit microprocessor through which internal registers accessed. sources interrupts masked acknowledged through microprocessor interface. Please refer more information about COMET-QUAD. Microprocessor Interface Block microprocessor interface contains de-multiplexed address data buses control perform following functions AAL1gator-8 Reference Design:
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Configuration AAL1gator-8 COMET COMET-QUAD devices Monitoring alarms interrupts AAL1gator-8 COMET COMET-QUAD devices
order provide maximum system implementation flexibility, particular microprocessor been specified. However, system microprocessor must have following minimum capabilities: address data programmable chip selects independent interrupt request lines
example microprocessor that meets these minimum requirements Motorola MC68340. Another option would implement design compact system. AAL1gator-8 COMET/COMET-QUADs Interconnections AAL1gator-8 communicates with COMET/COMET-QUAD devices framer signals listed Table Four bits each signal group connects COMET-QUAD device. instance, TL_SYNC[3.0] connected COMET-QUAD while TL_SYNC[7.4] connected COMET-QUAD Table SIGNAL TL_SYNC[7.0] TL_CLK[7.0] RL_CLK[7.0] RL_SYNC[7.0] RL_SIG[7.0] RL_DATA[7.0] TL_SIG[7.0] TL_DATA[7.0] AAL1gator-8 COMET/COMET-QUAD Connections DESCRIPTION FPGA generates this signal both AAL1gator-8 COMET/COMET-QUADs. mode, this signal consists pulse once every periods. This clock signal transmit line rate. source determined configuration FPGA. Receive line clock either 1.544 2.048 MHz, derived from recovered line rate timing. Carries receive frame synchronization from COMET/COMETQUAD devices. Carries signaling information from COMET/COMETQUAD devices. Carries receive data from COMET/COMET-QUAD devices. Carries signaling outputs COMET/COMET-QUAD devices. Carries serial data COMET/COMET-QUAD devices.
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FPGA Block direct connections between AAL1gator-8 COMETs COMET-QUADs used, depending upon configuration, Field Programmable Gate Array (FPGA) performs following optional functions: Implements external Adaptive Clock Recovery scheme designer would like perform external algorithm instead AAL1gator-8's internal algorithm. Distributes XCLK source among COMET COMET-QUAD devices. Generates framing pulses. Generates software selected N_CLK signal (2.43 MHz) from Network clock. Note that AAL1gator-8 capable implementing SRTS Adaptive Clock Recovery scheme own; therefore, FPGA required perform these methods, required perform other functions mentioned items above. adaptive Clock recovery mode, AAL1gator-8 provides queue depth difference controlling external clock. FPGA latches channel status frame difference uses them adjust synthesized clock frequency. queue depth low, clock frequency reduced; however, queue depth high, clock frequency increased. FPGA also distributes XCLK signals COMET COMET-QUAD devices from only clock oscillators: 1.544 2.048 MHz. Another function FPGA generate framing pulse from transmit line clock (BTCLK COMET COMET-QUAD) framers. This signal connects AAL1gator-8 TL_SYNC input COMET's COMET-QUAD's BTFP input. mode, frame pulse (BTFP) clock (BTCLK) period wide, generated every bits. But, mode, frame pulse generated every bits. implementation synchronous residual time stamp (SRTS), AAL1gator-8's network clock (N_CLK) must 2.43 signal. This signal generated dividing 155.52 Anetwork clock FPGA. AAL1gator-8 with COMET-QUADs Reference Design, H-MVIP mode used, FPGA used distribute 16.384 clock AAL1gator8's C16B COMET-QUADs' CMV8MCLK input pins. FPGA also used distribute 4.096 Frame Pulse Clock AAL1gator-8's
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COMET-QUADs' CMVPFC inputs, generate Common H-MVIP Frame Pulse from Frame Pulse Clock. H-MVIP common frame pulse sampled falling edge 4.096 clock occurs every 125us (i.e. occurs every pulse). AAL1gator-8's SRAM 128k pipelined SRAM used interface with AAL1gator-8. this reference design, pipelined Synchronous Turn Around) SRAM, GS841Z18, from Technology used power consumption approximately 3.3V less than other vendors). GS841Z18 SRAM (256k bi-directional data pins which indicate parity lower upper bytes data. Note that since there 128k 16-bit SRAMs market, 256k 16-bit SRAM used this reference design. Other manufacturers such Cypress Semiconductor's NoBL, Samsung Electronics' NtRAM, Integrated Device Technology's RAMS also used instead GS841Z8 SRAM compatibility. Regulators Block generate +3.3V +2.5V voltages from (Vcc), drop voltage regulators: LT1528 LT1118CST used AAL1gator-8 Reference Design. LT1528 voltage regulator provides 3.3V board. LT1118CST voltage regulator provides 0.500A 2.5V AAL1gator-8 with COMETs reference design 0.750A AAL1gator-8 with COMET-QUADs reference design. Both regulators should package, that additional heat sink required. dissipated heat each regulator 3.3) LT1528 2.5) 1.25 LT1118CST AAL1gator-8 w/COMETs 2.5) 0.75 1.875 LT1118CST AAL1gator-8 w/COMET-Q Blocks blocks contain super green yellow LEDs. super green LEDs used show power status +5V, +3.3V +2.5V power sources.
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yellow LEDs used interrupt alarm monitoring AAL1gator-8, COMET COMET-QUAD devices. 5.10 RESET Block hardware reset circuitry constructed with pushbutton switch MAX700 Power-Supply Monitor with Reset device circuitry. 5.11 JTAG Port JTAG port connected among devices allow boundary scan testing. signals connected following way: Test Mode Select signal connected parallel among COMET/COMET-QUAD devices, SRAM AAL1gator-8. Test Clock signal connected parallel among COMET/COMET-QUAD devices, SRAM AAL1gator-8. TRSTB Test Reset Select signal connected parallel among COMET/COMET-QUAD devices AAL1gator-8. source this signal either JTAG controller, from pushbutton activation TDI/TDO Test Data Input/Test Data Output signal connected serially among COMET/COMET-QUAD devices, SRAM AAL1gator-8, beginning with AAL1gator-8, ending with last COMET/COMETQUAD device.
JTAG port signals connect externally accessible header. 5.12 Timing Block timing block consists oscillators part FPGA. 50ppm HCMOS oscillators chosen packaged half-sized metal DIP. Table shows type functionality oscillators used reference design. Table Frequency (MHz) 1.544 2.048 Oscillators Usage Provides XCLK signals COMETs COMETQUADs mode. Provides XCLK signals COMETs COMET-
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QUADs mode. 38.88 Provides AAL1gator-8's system clock (AAL1_SYSCLK) AAL1gator-8's SRAM clock (RAM_CLK) Used H-MVIP mode generate sample HMVIP frame pulse signal. Used H-MVIP mode provide common clock used transfer data across H-MVIP bus.
4.096 16.384 5.13
UTOPIA Interface AAL1gator-8 communicate with Alayer devices (such S/UNI-ATLAS) UTOPIA interface. Please refer UTOPIA Interface signals AAL1gator-8 data sheet description individual signals. There possible modes operation AAL1gator-8: UTOPIA mode Any-PHY mode. These configurations possible through AAL1gator-8's UI_Source_Config Register (UI_SRC_CFG). When ANY_PHY_EN this register cleared (ANY_PHY_EN `0'), AAL1gator8 configured with UTOPIA interface. When ANY_PHY_EN (ANY_PHY_EN `1'), device Any-PHY mode. Also, UTOP_MODE [1:0] bits this register selects UTOPIA operating mode source side interface illustrated Table Table AAL1gator-8's UTOPIA Operating Modes Operating Mode UTOPIA-Level Master UTOPIA-Level Slave UTOPIA-Level Single Address Slave Reserved
UTOP_MODE[1:0] `00' `01' `10' `11'
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DESIGN ISSUES AAL1gator-8 Design Considerations
6.1.1 Power Supply power +3.3V pins should applied before power +2.5V pins applied. ground pins (PPL, PQL, PCL) should connected together. 6.1.2 Decoupling 0.01µF capacitor placed between power ground +2.5V +3.3Vpins. capacitors should placed close actual possible. 6.1.3 Line Mode Selection AAL1gator-8 configured operate direct mode setting Line_Mode high H-MVIP mode. this purpose jumpers provided select ground (low) +3.3V. (high). This hardware configuration must done prior power Line Termination each line terminations COMET COMET-QUAD devices, this reference design uses termination that compromises between termination been used. COMET Design Considerations
6.3.1 Power Supply During power-up, BIAS must equal greater than voltage pins. This accomplished with voltage regulator. voltage BIAS also same used regulate voltage. Therefore, worst case that regulator malfunctions shorts, which still leaves BIAS equal VDD. Also, extra protection diode used limit maximum 0.5V above BIAS voltage. Analog power pins must applied after they must current limited maximum latch-up current 100mA. simple solution small filtering network between pins delay power.
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differential voltage measured between supplies must less than 0.5V. 6.3.2 Decoupling 0.01µF capacitor placed between power ground VDDO pins. 0.1µF capacitor placed between power ground VDDI pins. capacitors should placed close actual possible. pins require filtering network between plane each pin. network single network with resistor between plane capacitor from plane. Please refer schematics Appendix component values. 6.3.3 Voltage References Transmit Voltage Reference (TVREF) requires 4.7uF capacitor analog ground 12.7Ohm resistors corresponding TxRING TxTIP pins. Reference Voltage Reference (RVREF), which reserved precision analog voltage current reference, must connected circuit consisting kohm resistor connected parallel with 10nF capacitor analog ground. COMET-QUAD Design Considerations
6.4.1 Power Supply Sequencing following power sequence COMET-QUAD must followed: +3.3V digital pins +3.3V analog pins (TAVDx, CAVD, RAVDx, QAVD) +2.5V digital pins
Power +3.3V pins, both analog digital, must applied before +2.5V. Power +3.3V digital pins must applied before power +3.3V analog. simple solution latter statement small filtering network between +3.3V digital +3.3V analog pins delay power.
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6.4.2 Decoupling 0.01µF 0.1µF capacitors placed between power ground (+2.5 +3.3V) pins. capacitors should placed close actual pins possible. pins require filtering network between plane each pin. network single network with resistor between plane capacitor from plane. Please refer schematics Appendix component values. 6.4.3 Voltage References Each Transmit Common Mode (TxCM[1:4]) requires 4.7uF capacitors analog ground 12.7Ohm resistors corresponding TxRING TxTIP pins. Reference Voltage Reference (RVREF), which reserved precision analog voltage current reference, must connected circuit consisting kohm resistor connected parallel with 10nF capacitor analog ground. Microprocessor Interface Table Table list assignment potential microprocessor interfaces DIN) AAL1gator-8 reference design with COMETs COMETQUADs, respectively. Note that these interfaces include connections from microprocessor AAL1gator-8, COMET COMET-QUAD devices, FPGA. Table NAME UP_D(15) UP_D(14) UP_D(13) UP_D(12) UP_D(11) UP_D(10) UP_D(9) UP_D(8) UP_D(7) UP_D(6) Interface Pinout AAL1gator-8 w/COMETs TYPE NUMBER FUNCTION data
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NAME UP_D(5) UP_D(4) UP_D(3) UP_D(2) UP_D(1) UP_D(0) UP_A(23) UP_A(22) UP_A(21) UP_A(20) UP_A(19) UP_A(18) UP_A(17) UP_A(16) UP_A(15) UP_A(14) UP_A(13) UP_A(12) UP_A(11) UP_A(10) UP_A(9) UP_A(8) UP_A(7) UP_A(6) UP_A(5) UP_A(4) UP_A(3) UP_A(2) UP_A(1) UP_A(0) RDB_IN WRB_IN AAL1_ACKB AAL1_INTB IRQ2B RSTB AAL1_CSB
TYPE
Input (from
Input Input Input Output Output Input Input
NUMBER
FUNCTION
address
Active read signal Active write signal. Active acknowledge signal Active interrupt request from AAL1gator-8 Active interrupt request from Framer Active global reset. Active chip select. When asserted, AAL1gator-8 selected.
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NAME CS2B CS3B Table NAME UP_D(15) UP_D(14) UP_D(13) UP_D(12) UP_D(11) UP_D(10) UP_D(9) UP_D(8) UP_D(7) UP_D(6) UP_D(5) UP_D(4) UP_D(3) UP_D(2) UP_D(1) UP_D(0) UP_A(21) UP_A(20) UP_A(19) UP_A(18) UP_A(17) UP_A(16) UP_A(15) UP_A(14) UP_A(13) UP_A(12) UP_A(11) UP_A(10) UP_A(9) UP_A(8) UP_A(7) UP_A(6) UP_A(5)
TYPE Input Input
NUMBER
FUNCTION Active chip select. When asserted COMET selected. Active chip select. When asserted, FPGA selected. GND. Ground Reference
Interface Pinout AAL1gator-8 w/COMET-QUADs TYPE NUMBER FUNCTION data
Input (from
22bit address
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NAME UP_A(4) UP_A(3) UP_A(2) UP_A(1) UP_A(0) RDB_IN WRB_IN AAL1_ACKB AAL1_INTB IRQ2B RSTB AAL1_CSB CS2B CS3B
TYPE
Input Input Input Output Output Input Input Input Input
NUMBER
FUNCTION
Active read signal Active write signal. Active acknowledge signal Active interrupt request from AAL1gator-8 Active interrupt request from Framer Active global reset. Active chip select. When asserted, AAL1gator-8 selected. Active chip select. When asserted, COMET-QUAD selected. Active chip select. When asserted, FPGA selected. GND. Ground Reference
Figures indicate usage external address buffers data transceivers. order system operate maximum frequency 40.00 MHz, address buffers must have worst case propagation delay 8ns, while data transceivers must have worst case delay 10ns. these reasons IDT74FCT163827CT chosen address buffer. This device maximum propagation delay 4.4ns (50pF, load). IDT74FCT163646 chosen data transceiver. This 16-bit device worst case propagation delay 5.4ns under same loading conditions. When microprocessor wishes communicate with COMET device, asserts address listed Table When appropriate address driven onto bus, microprocessor simultaneously asserts CS2B. Since high, decoder then active. Address bits A[22.20] determine which output decoder driven low. decoder output connects input each COMET device. example, A[22.20] 000, then decoder output driven low, which also asserts COMET0. other COMET
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device selected this time. Address bits A[8.0] determine which register COMET microprocessor communicating with. order meet timing requirements COMET devices (refer [2]), decoder (74HCT138) must have maximum propagation delay 10ns. With 15pF load, device typical delay 13ns. 50pf (VCC 4.5), delay increases 38ns, therefore will meet specifications. Table Address Space AAL1gator-8 w/COMETs BASE ADDRESS 000000h 800000h 900000h A00000h B00000h C00000h D00000h E00000h F00000h ADDRESS RANGE 000000 0FFFFFh 800000 8001FFh 900000 9001FFh A00000 A001FFh B00000 B001FFh C00000 C001FFh D00000 D001FFh E00000 E001FFh F00000 F001FFh
DEVICE AAL1gator-8 COMET0 COMET1 COMET2 COMET3 COMET4 COMET5 COMET6 COMET7
Table shows Address ranges devices used AAL1gator-8 with COMET-QUADs reference design. Table Address Space AAL1gator-8 w/COMET-QUADs BASE ADDRESS 000000h 200000h 300000h ADDRESS RANGE 000000 0FFFFFh 200000 2007FFh 300000 3007FFh
DEVICE AAL1gator-8 COMET-QUAD0 COMET-QUAD1
Since address data buses shared among many devices, buffer transceiver used. This insures that clean signals present inputs devices, that data collisions occur. buffer (FCT163827) only placed address lines, various control signals such well. 16-bit transceiver (FCT163646) used flow through mode control data access. transceivers output enable controlled result logical CS2B CS3B. this way, whenever microprocessor needs communicate with either COMET/COMET-QUAD FPGA, either CS2B, CS3B signal must driven low, which drives active output enable signal transceiver low. transceivers' direction controlled signal.
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Power Requirements Table provides estimated power requirements AAL1gator-8 Reference Design with COMETs. Table AAL1gator-8 w/COMET-QUADs provides maximum power requirements AAL1gator-8 Reference Design with COMET-QUADs. Table Power Consumption AAL1gator-8 w/COMETs
Components 74HCT138A (SOIC) LEDs 74HCT08 Misc, pullups/downs Total Power 3.3V Components COMET AAL1gator-8 FPGA SRAM Oscillators LEDs Buffers/Transceivers Misc. Total 3.3V Power 2.5V Components AAL1gator-8 Total 2.5V Power
Quantity Current (mA) Power (mW)
1240 (mW)
Power (mW)
Quantity
Current (mA)
6600 402.6 1188 72.6 10804.(mW)
Power (mW)
Quantity
Current (mA)
(mW)
Total Power
12644 (mW)
Table Power AAL1gator-8 w/COMET-QUADs
Components 74HCT138A (SOIC) LEDs 74HCT08 Misc, pullups/downs Total Power
Quantity Current (mA) Power (mW)
1240 (mW)
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3.3V Components COMET-QUAD AAL1gator-8 FPGA SRAM Oscillators LEDs Buffers/Transceivers Misc. Total 3.3V Power 2.5V Components COMET-QUAD AAL1gator-8 Total 2.5V Power
Quantity
Current (mA)
Power (mW)
2910.6 402.6 1188 72.6 7181 (mW)
Power (mW)
Quantity
Current (mA)
(mW)
Total Power
9211 (mW)
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IMPLEMENTATION DESCRIPTION AAL1gator-8 with COMETs AAL1gator-8 with COMET-QUADs reference design schematics were captured using Cadence software Concept Schematics Capture tool.
AAL1GATOR-8 with COMET Schematics Sheet ROOT DRAWING This sheet provides overview major functional blocks AAL1gator8 plus COMET reference design. Also, illustrates interconnections among various blocks design. Groups signals have been combined into type name format even though these signals typically made into buses. This done make schematic less cluttered more readable utilize capabilities schematic capture tool. Some examples such signals TXTIP<7.0>, TL_DATA<7.0>, TL_CLK<7.0>. Sheets 2-9: COMET BLOCK These sheets show COMET devices their power circuitry. power circuitry includes schottky diode protection while powering COMET device separate filtering circuitry analog digital power pins. addition, JTAG port connected among COMET devices, AAL1gator-8. Sheets 10-13: LINE INTERFACE These schematics show termination, magnetic protection circuitry line interface. Pulse T9021, quad 1:2.42 transformer included with Surge Protector Diode Array, used couple four COMETs' transmit receive lines connectors. LC01-6 transient voltage suppressor (TVS) Raychem provide over voltage protection. single footprint provided both bantam RJ48C connectors. Sheet FPGA BLOCK This sheet shows interconnection Actel 42MX36 FPGA between AAL1gator-8 COMET devices. 1.544 2.048 oscillators present supply XCLK signal COMET devices. 38.88 oscillator present supply AAL1gator-8 system clock (SYSCLK) AAL1gator-8's clock (RAM_CLK). A
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Network clock used FPGA generate 2.43 NCLK. 0.1uF bulk capacitors specified, should placed corners FPGA. AAL1gator-8's clock synthesizer's interfaces optionally provided FPGA order provide customization SRTS adaptive recovery algorithms. Note that FPGA Mode except during device programming debugging. Note that actual design FPGA been performed this paper reference design. FPGA design implemented with schematics hardware definition language. Sheet MEMORY SYSTEM BLOCK This sheet indicates connections between system microprocessor, AAL1gator-8, COMET devices, FPGA. buffers data transceivers present. Sheets 16-18: AAL1GATOR-8 BLOCK These sheets show AAL1gator-8 connected into system. Page illustrates AAL1gator-8's line interface, microprocessor interface, JTAG connections, power supply signal connections, decoupling capacitors. Note that TLCLK_OE input high make TL_CLK pins outputs between time hardware reset when CLK_SOURCE_TX bits read. Direct mode, Line_Mode pins grounded. Page shows AAL1gator-8's interface with 256k 18-bit pipelined GS841Z18 SRAM. Since interface AAL1gator-8 limited 128k, most significant SRAM grounded. Bits indicate parity lower upper bytes, respectively. Page shows AAL1gator-8's UTOPIA connection UTOPIA connector provide access UTOPIA externally. Sheet MICRO INTERFACE POWER This page shows connections between system microprocessor reference design board. LT1528 drop voltage regulator provides 3.3V board. LT1118CST voltage regulator provides 0.500A 2.5V AAL1gator-8 reference design. Both regulators should package, that additional heat sink required. Also, pushbutton
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switch included Reset circuitry provide hardware reset. This page also included JTAG port, power interrupt status circuitry. AAL1GATOR-8 with COMET-QUAD Schematics Sheet ROOT DRAWING This sheet provides overview major functional blocks AAL1gator8 plus COMET-QUAD reference design. Also, illustrates interconnections among various blocks design. Sheets 2-3: COMET-QUAD BLOCK These pages show COMET-QUAD devices their power circuitry. Separate filtering circuitry analog digital power pins included. addition, JTAG port connected among COMET-QUAD devices, AAL1gator-8. H-MVIP signal interface also provided optional use. Sheets 4-7:LINE INTERFACE These schematic diagrams same those COMET version. Sheet FPGA BLOCK This sheet shows interconnection FPGA between AAL1gator-8 COMET-QUAD devices. 1.544 2.048 oscillators present supply XCLK signal COMET-QUAD devices. The38.88 oscillator present supply AAL1gator-8 system clock (SYSCLK) AAL1gator-8's clock (RAM_CLK). Anetwork clock used FPGA generate 2.43 NCLK. 4.096 16.384 oscillators provided H-MVIP mode's common clock frame pulses. 0.1uF bulk capacitors specified, should placed corners FPGA. Sheet MEMORY SYSTEM BLOCK This sheet indicates connections between system microprocessor, AAL1gator-8, COMET-QUAD devices, FPGA. buffers data transceivers present.
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Sheets 10-12: AAL1GATOR-8 BLOCK These schematic diagrams same those COMET version, except Line_Mode0 Direct mode high H-MVIP mode. Sheet MICRO INTERFACE POWER This page shows connections between system microprocessor reference design board. LT1528 drop voltage regulator provides 3.3V board. LT1118CST voltage regulator provides 0.750A 2.5V AAL1gator-8 COMET-QUAD devices. Both regulators should package, that additional heat sink required. Also, pushbutton switch included Reset circuitry provide hardware reset. This sheet also included JTAG port, power interrupt status circuitry.
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GLOSSARY AAL1 Any-PHY ACBR SCI-PHY SRTS UTOPIA AAdaptation Layer Interoperable version UTOPIA SCI-PHY Asynchronous Transfer Mode Constant Rate Circuit Emulation Services Class Service Physical Layer Segmentation Re-assembly PMC-Sierra enhanced UTOPIA Synchronous Residual Time Stamp Universal Test Operations Interface AVariable Rate Virtual Circuit Virtual Channel Connection Virtual Circuit Identifier Virtual Path Virtual Path Connection Virtual Path Identifier Wide Area Network Zero Turnaround
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DEFINITIONS (AAdaptation Layer) layer above Alayer that allows users send packets larger than cell. Ainterface segments these packets, transmits cells individually, reassembles them other end. consists sub-layers: Convergence Sub-layer (CS) Segmentation Reassmbly (SAR). supports many kinds services with different traffic characteristics system requirements. AAL1 (AAdaptation Layer layer above ALayer AProtocol Model that handles adapting traffic Anetwork. Supports connection-oriented services that require constant rates have specific timing delay requirements. Examples constant rate services like transport. (Constant Rate) Constant Rate (CBR) five service categories ALayer. This service type allows user define specific cell delay, cell delay variation (CDV), reserves specific fixed bandwidth network. traffic includes voice, video, circuit emulation (e.g., Circuit emulation). Voice video that been compressed have variable transmission rate therefore would into this service class. (Circuit Emulation Service) service provided emulate circuits only passing bits through Anetwork maintaining synchronization providing timing. (Segmentation Reassembly) Segmentation Reassembly Layer lower sublayers (Convergence Sublayer (CS) SAR) that make AAdaptation Layer (AAL) shown diagram below. responsible mapping data from Convergence Sublayer into cell payloads Acell stream. (Time Division Multiplexing) method multiplexing which transmission channel divided into discrete time intervals
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REFERENCES PMC-Sierra Inc., PMC-1970624, "Combined E1/T1 Transceiver Standard Product Data Sheet", November 2000, Issue PMC-Sierra Inc., PMC-1990315, "COMET-QUAD Data Sheet", 2001, Issue PMC-Sierra Inc., PMC-2000097, "AAL1gator-8 Data Sheet", January 2000, Issue
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DISCLAIMER This document paper reference design, such, been built tested this date.
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PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
APPENDIX BILL MATERIALS (COMET VERSION) Table Ref. U2-9 U28-47 U15-16 U51, U52, Major Components List Component PM73123 AAL1gator-8 PM4351 COMET LC01-6 T9021 1:2.42 Transformer A42MX36 PQ208 FPGA GS841Z18 SRAM MAX700 Power Supply Monitor 74FCT163827 FAST Buffer 74FCT163646 FAST Transceiver MC74HCT138AD 3-to-8 Decoder MCHCT541 Buffer LT1528 Voltage Regulator LT1118CST Voltage Regulator HCMOS 38.880MHz, 50ppm Oscillator Manufacture PMC-Sierra Inc. PMC-Sierra Inc. SEMTECH Pulse Inc. ACTEL Technology MAXIM Motorola Motorola Linear Technology Linear Technology Components Package Type PBGA CABGA PQFP TQFP SOIC SOIC SOIC Half-size Quantity
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
TR1-32
HCMOS 1.544MHz, 50ppm Oscillator HCMOS 2.048MHz, 50ppm Oscillator 3.000A NANO 0.500A NANO Pushbutton switch TR250-180U Thermistor
Components Components Littlefuse Littlefuse
Half-size Half-size Socket Socket
Raychem Telecomm.
PC-834-C-Black Bantam Covers J10, J12, J13, J15, J16, J18, J19, J21, J22,
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
APPENDIX BILL MATERIALS (COMET-QUAD VERSION) Table Ref. U2-3 U20-23, U26-29, U32-35, U38-41 U5-6 Major Components List Component PM73123 AAL1gator-8 PM4354 COMET-QUAD LC01-6 Manufacture PMC-Sierra Inc. PMC-Sierra Inc. SEMTECH Package Type PBGA PBGA Quantity
T9021 1:2.42 Transformer A42MX36 PQ208 FPGA GS841Z18 SRAM MAX700 Power Supply Monitor
Pulse Inc. ACTEL Technology MAXIM Motorola Motorola Linear Technology Linear Technology
PQFP TQFP SOIC SOIC SOIC Half-size
U44, 74FCT163827 FAST Buffer U45, 74FCT163646 FAST Transceiver MCHCT541 Buffer MC74HCT138AD 3-to-8 Decoder LT1528 Voltage Regulator LT1118CST Voltage Regulator HCMOS 38.880MHz, 50ppm
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
Oscillator TR1-32 J10, J12, J13, J15, J16, J18, J19, J21, J22, HCMOS 1.544MHz, 50ppm Oscillator HCMOS 2.048MHz, 50ppm Oscillator HCMOS 16.384MHz, 50ppm Oscillator HCMOS 4.096MHz, 50ppm Oscillator Littlefuse, 3.000A NANO Littlefuse, 0.750A NANO Pushbutton switch Raychem, TR250-180U Thermistor PC-834-C-Black Bantam Covers
Components Components Components Components Components Littlefuse Littlefuse Raychem Telecomm
Half-size Half-size Half-size Half-size Socket Socket
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
APPENDIX AAL1GATOR-8 W/COMETS SCHEMATICS
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
APPENDIX AAL1GATOR-8 W/COMET-QUADS SCHEMATICS
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
REVISIONS
ZONE DESCRIPTION DATE APPR
PAGES 10-12 AAL1GATOR_8_BLOCK TL_DATA<7.0> TL_SIG<7.0> RL_DATA<7.0> RL_SIG<7.0> RL_SYNC<7.0> RL_CLK<7.0> AAL1_TDO PAGES COMET_QUAD_BLOCK TXTIP<7.0> TXRING<7.0> TXCM<7.0> RXTIP<7.0> RXRING<7.0> PAGES LINE_INTERFACE
TL_DATA<7.0> TL_SIG<7.0> RL_DATA<7.0> RL_SIG<7.0> RL_SYNC<7.0> RL_CLK<7.0> AAL1_TDO
TL_DATA<7.0> TL_SIG<7.0> RL_DATA<7.0> RL_SIG<7.0> RL_SYNC<7.0> RL_CLK<7.0>
TXTIP<7.0> TXRING<7.0> TXCM<7.0> RXTIP<7.0> RXRING<7.0> TRSTB
TXTIP<7.0> TXRING<7.0> TXCM<7.0> RXTIP<7.0> RXRING<7.0>
AAL1_TDO
TDO1 IRQ2_BUS<1.0>
PAGE FPGA_BLOCK TL_CLK<7.0> TL_SYNC<7.0> CGC_SER_D CGC_VALID CGC_DOUT<3.0> CGC_LINE<3.0> ADAP_STRB SRTS_STRB AAL1_SYSCLK NCLK RAM_CLK TL_CLK<7.0> TL_SYNC<7.0> CGC_SER_D CGC_VALID CGC_DOUT<3.0> CGC_LINE<3.0> ADAP_STRB SRTS_STRB AAL1_SYSCLK NCLK RAM_CLK TL_CLK<7.0> TL_SYNC<7.0> CGC_SER_D CGC_VALID CGC_DOUT<3.0> CGC_LINE<3.0> ADAP_STRB SRTS_STRB AAL1_SYSCLK NCLK RAM_CLK CS3B PAGE MICRO INTERFACE AAL1_CSB AAL1_ACKB AAL1_INTB AAL1_CSB AAL1_ACKB AAL1_INTB AAL1_CSB PAGE AAL1_ACKB AAL1_INTB RDB_IN WRB_IN RSTB RSTB COMETQ_CSB<1.0> MEMORY_SYSTEM_BLOCK USED H-MVIP MODE C16B C16B C16B RSTB COMETQ_FPGA_A<2.0> COMETQ_FPGA_D<7.0> COMETQ_FPGA_A<2.0> CMV8MCLK CMVFPC CMVFPB USED H-MVIP MODE CMV8MCLK CMVFPC CMVFPB BTCLK<7.0> BTFP<7.0> XCLK<1.0> BTCLK<7.0> BTFP<7.0> XCLK<1.0> BTCLK<7.0> BTFP<7.0> XCLK<1.0>
RSTB COMETQ_FPGA_D<7.0> COMETQ_FPGA_A<10.0> COMETQ_CSB<1.0>
CMV8MCLK CMVFPC CMVFPB
<2.0>
COMETQ_CSB<1.0>
COMETQ_FPGA_A<10.0> TRSTB UP_A<21.0> UP_D<15.0> CS2B RDB_IN WRB_IN CS3B RSTB IRQ2_BUS<1.0> COMETQ_FPGA_D<7.0> TRSTB AAL1_A<19.0> AAL1_D<15.0> AAL1_A<19.0> AAL1_D<15.0> AAL1_A<19.0> AAL1_D<15.0>
COMETQ_FPGA_A<10.0> COMETQ_FPGA_D<7.0>
UP_A<21.0> UP_D<15.0> CS2B RDB_IN WRB_IN CS3B RSTB IRQ2_BUS<1.0> DEV_SELB TDO1 TRSTB
UP_A<21.0> RDB_IN UP_D<15.0> CS2B WRB_IN
DEV_SELB
PMC-Sierra, Inc.
DRAWING TITLE=AAL_ROOT ABBREV=AAL_ROOT LAST_MODIFIED=Fri 10:30:26 2000 DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN ROOT DRAWING ENGINEER: ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:1 TRUE
REVISIONS
ZONE DESCRIPTION DATE APPR
PBGA PBGA
5D10< 5G10< 4D10< 4G10<
8F2>
BTCLK<7.0>\I
COMET-QUAD PM4354
TXTIP<3>\I TXTIP<2>\I TXTIP<1>\I TXTIP<0>\I
COMET-QUAD PM4354 TXTIP1<4> TXTIP1<3> TXTIP1<2> TXTIP1<1> TXTIP2<4> TXTIP2<3> TXTIP2<2> TXTIP2<1> TXRING1<4> TXRING1<3> TXRING1<2> TXRING1<1> TXRING2<4> TXRING2<3> TXRING2<2> TXRING2<1> TXCM<4> TXCM<3> TXCM<2> TXCM<1>
RXTIP<4> RXTIP<3> RXTIP<2> RXTIP<1>
RXTIP<3>\I RXTIP<2>\I RXTIP<1>\I RXTIP<0>\I RXRING<3>\I RXRING<2>\I RXRING<1>\I RXRING<0>\I
5B10> 5F10> 4B10> 4F10> 5B10> 5E10> 4B10> 4E10>
BTCLK<4> BTCLK<3> BTCLK<2> BTCLK<1> BTSIG<4> BTSIG<3> BTSIG<2> BTSIG<1> BTFP<4> BTFP<3> BTFP<2> BTFP<1> BTPCM<4> BTPCM<3> BTPCM<2> CASBTD_BTPCM<1>
BRCLK<4> BRCLK<3> BRCLK<2> BRCLK<1> BRSIG<4> BRSIG<3> BRSIG<2> BRSIG<1> BRFP<4> BRFP<3> BRFP<2> BRFP<1> BRPCM<4> BRPCM<3> BRPCM<2> CASBRD_BRPCM<1>
RL_CLK<7.0>\I
3G2> 10C10<
RL_SIG<7.0>\I
3G2> 10C10<
10C5>
TL_SIG<7.0>\I
RXRING<4> RXRING<3> RXRING<2> RXRING<1> RVREF<4> RVREF<3> RVREF<2> RVREF<1> RES<8> XCLK CTCLK RSYNC RES<7> RES<6> RES<5> RES<4> RES<3> RES<2> RES<1>
8E2>
BTFP<7.0>\I
5C10< 5G10< 4C10< 4G10<
TXRING<3>\I TXRING<2>\I TXRING<1>\I TXRING<0>\I
RL_SYNC<7.0>\I
3G2> 10D10<
10D5>
TL_DATA<7.0>\I
RL_DATA<7.0>\I
3F2> 10D10<
XCLK<0>\I
8C2>
5D10> 5G10> 4D10> 4G10>
TXCM<3>\I TXCM<2>\I TXCM<1>\I TXCM<0>\I
8E2> 8D2> 8D2>
CMV8MCLK\I CMVFPC\I CMVFPB\I
CCSBTD MVBTD MVBRD_CCSBRD CMV8MCLK CMVFPC CMVFPB SYSTEM
0.01UF
0.01UF
0.01UF
100K
100K
100K
100K
LINE
0.01UF
22UF 0.01UF 22UF R102 0.01UF
PBGA
0.47UF
0.47UF 0.01UF
0.47UF 0.01UF
0.47UF 0.01UF
QAVD<2> QAVD<1> RAVD1<4> RAVD1<3> RAVD1<2> RAVD1<1> RAVD2<4> RAVD2<3> RAVD2<2> RAVD2<1> TAVD1<4> TAVD1<3> TAVD1<2> TAVD1<1> TAVD2<4> TAVD2<3> TAVD2<2> TAVD2<1> TAVD3<4> TAVD3<3> TAVD3<2> TAVD3<1>
COMET-QUAD PM4354 QAVS<2> QAVS<1> RAVS1<4> RAVS1<3> RAVS1<2> RAVS1<1> RAVS2<4> RAVS2<3> RAVS2<2> RAVS2<1> TAVS1<4> TAVS1<3> TAVS1<2> TAVS1<1> TAVS2<4> TAVS2<3> TAVS2<2> TAVS2<1> TAVS3<4> TAVS3<3> TAVS3<2> TAVS3<1> VSSC2_5<7> VSSC2_5<6> VSSC2_5<5> VSSC2_5<4> VSSC2_5<3> VSSC2_5<2> VSSC2_5<1> VSS3_3<9> VSS3_3<8> VSS3_3<7> VSS3_3<6> VSS3_3<5> VSS3_3<4> VSS3_3<3> VSS3_3<2> VSS3_3<1> VSSQ3_3<2> VSSQ3_3<1> GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 POWER
0.01UF
0.1UF 0.01UF
0.1UF 0.01UF
0.1UF 0.01UF
0.1UF R100 0.01UF
47UF 0.01UF
47UF 0.01UF
47UF 0.01UF
47UF 0.01UF
VDDC2_5<8> VDDC2_5<7> VDDC2_5<6> VDDC2_5<5> VDDC2_5<4> VDDC2_5<3> VDDC2_5<2> VDDC2_5<1> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDDQ3_3<2> VDDQ3_3<1> CAVS CAVD GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
9D1>
COMETQ_FPGA_A<10.0>\I
0.01UF
3A10< 11E2> 13G5> 13H5> 13G5>
TDO0 AAL1_TDO\I TCK\I TMS\I TRSTB\I
RDB\I WRB\I COMETQ_CSB<0>\I IRQ2_BUS<0>\I RSTB\I
9C1> 9C1> 9B1> 13E2< 13F5>
22UF
PBGA COMET-QUAD PM4354 D<7> A<10> A<9> D<6> A<8> D<5> A<7> D<4> A<6> D<3> A<5> D<2> A<4> D<1> A<3> D<0> A<2> A<1> A<0> INTB RSTB TRSTB MICRO_JTAG
COMETQ_FPGA_D<7.0>\I
4.7K
3B7<> 9E1<> 8C9<
R101
DRAWING: COMET_Q_1 COMETQ 11:12:19 2001
PMC-Sierra, Inc.
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF C146 C147
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN COMET_QUAD_1 ENGINEER:
ISSUE DATE: 01/05/16 REVISION NUMBER: PAGE:2
DECOUPLING CAPS: POWER PINS
REVISIONS
ZONE DESCRIPTION DATE APPR
COMET-QUAD PM4354
7D10< 7G10< 6D10< 6G10<
8F2>
BTCLK<7.0>\I
TXTIP<7>\I TXTIP<6>\I TXTIP<5>\I TXTIP<4>\I
COMET-QUAD PM4354 TXTIP1<4> TXTIP1<3> TXTIP1<2> TXTIP1<1> TXTIP2<4> TXTIP2<3> TXTIP2<2> TXTIP2<1> TXRING1<4> TXRING1<3> TXRING1<2> TXRING1<1> TXRING2<4> TXRING2<3> TXRING2<2> TXRING2<1> TXCM<4> TXCM<3> TXCM<2> TXCM<1>
RXTIP<4> RXTIP<3> RXTIP<2> RXTIP<1>
TP10 TP11
RXTIP<7>\I RXTIP<6>\I RXTIP<5>\I RXTIP<4>\I RXRING<7>\I RXRING<6>\I RXRING<5>\I RXRING<4>\I
7B10> 7F10> 6B10> 6F10> 7B10> 7E10> 6B10> 6E10>
BTCLK<4> BTCLK<3> BTCLK<2> BTCLK<1> BTSIG<4> BTSIG<3> BTSIG<2> BTSIG<1> BTFP<4> BTFP<3> BTFP<2> BTFP<1> BTPCM<4> BTPCM<3> BTPCM<2> CASBTD_BTPCM<1>
BRCLK<4> BRCLK<3> BRCLK<2> BRCLK<1> BRSIG<4> BRSIG<3> BRSIG<2> BRSIG<1> BRFP<4> BRFP<3> BRFP<2> BRFP<1> BRPCM<4> BRPCM<3> BRPCM<2> CASBRD_BRPCM<1>
RL_CLK<7.0>\I
2G2>10C10<
RL_SIG<7.0>\I
2G2>10C10<
10C5>
TL_SIG<7.0>\I
RXRING<4> RXRING<3> RXRING<2> RXRING<1> RVREF<4> RVREF<3> RVREF<2> RVREF<1> RES<8> XCLK CTCLK RSYNC RES<7> RES<6> RES<5> RES<4> RES<3> RES<2> RES<1>
8E2>
BTFP<7.0>\I
RL_SYNC<7.0>\I
2G2>10D10<
7C10< 7G10< 6C10< 6G10<
TXRING<7>\I TXRING<6>\I TXRING<5>\I TXRING<4>\I
10D5>
TL_DATA<7.0>\I
RL_DATA<7.0>\I
2F2>10D10<
XCLK<1>\I
8C2>
R106
7D10> 7G10> 6D10> 6G10>
TXCM<7>\I TXCM<6>\I TXCM<5>\I TXCM<4>\I
8E2> 8D2> 8D2>
CMV8MCLK\I CMVFPC\I CMVFPB\I
CCSBTD MVBTD MVBRD_CCSBRD CMV8MCLK CMVFPC CMVFPB SYSTEM
0.01UF
0.01UF
0.01UF
R107
R111
R115
100K
100K
100K
100K
R116
LINE
0.01UF
22UF R117 0.01UF 22UF R122 0.01UF
0.47UF
0.47UF R104 0.01UF
0.47UF R109 0.01UF
0.47UF R113 0.01UF
QAVD<2> QAVD<1> RAVD1<4> RAVD1<3> RAVD1<2> RAVD1<1> RAVD2<4> RAVD2<3> RAVD2<2> RAVD2<1> TAVD1<4> TAVD1<3> TAVD1<2> TAVD1<1> TAVD2<4> TAVD2<3> TAVD2<2> TAVD2<1> TAVD3<4> TAVD3<3> TAVD3<2> TAVD3<1>
COMET-QUAD PM4354 QAVS<2> QAVS<1> RAVS1<4> RAVS1<3> RAVS1<2> RAVS1<1> RAVS2<4> RAVS2<3> RAVS2<2> RAVS2<1> TAVS1<4> TAVS1<3> TAVS1<2> TAVS1<1> TAVS2<4> TAVS2<3> TAVS2<2> TAVS2<1> TAVS3<4> TAVS3<3> TAVS3<2> TAVS3<1> VSSC2_5<7> VSSC2_5<6> VSSC2_5<5> VSSC2_5<4> VSSC2_5<3> VSSC2_5<2> VSSC2_5<1> VSS3_3<9> VSS3_3<8> VSS3_3<7> VSS3_3<6> VSS3_3<5> VSS3_3<4> VSS3_3<3> VSS3_3<2> VSS3_3<1> VSSQ3_3<2> VSSQ3_3<1> GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 POWER
R119 0.01UF
0.1UF R105 0.01UF
0.1UF R110 0.01UF
0.1UF R114 0.01UF
0.1UF R120 0.01UF
R103 47UF 0.01UF
R108 47UF 0.01UF
R112 47UF 0.01UF
R118 47UF 0.01UF
VDDC2_5<8> VDDC2_5<7> VDDC2_5<6> VDDC2_5<5> VDDC2_5<4> VDDC2_5<3> VDDC2_5<2> VDDC2_5<1> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDDQ3_3<2> VDDQ3_3<1> CAVS CAVD GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
COMETQ_FPGA_A<10.0>\I COMET-QUAD PM4354 D<7> A<10> A<9> D<6> A<8> D<5> A<7> D<4> A<6> D<3> A<5> D<2> A<4> D<1> A<3> D<0> A<2> A<1> A<0> INTB RSTB TRSTB MICRO_JTAG
22UF
9D1>
COMETQ_FPGA_D<7.0>\I
4.7K
0.01UF
R121
2C7<> 9E1<> 8C9<
DRAWING: COMET_Q_2 COMETQ 11:12:24 2001
13G5< 2B10> 13G5> 13H5> 13G5>
TDO1\I TDO0 TCK\I TMS\I TRSTB\I
RDB\I 9C1> WRB\I 9C1> COMETQ_CSB<1>\I 9B1> IRQ2_BUS<1>\I RSTB\I
13E2< 13F5>
PMC-Sierra, Inc.
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN COMET_QUAD_2 ENGINEER:
ISSUE DATE: 01/05/16 REVISION NUMBER: PAGE:3
DECOUPLING CAPS: POWER PINS
REVISIONS
ZONE DESCRIPTION DATE APPR
TR250-180
RING OPTIONAL CHOKE PLACEMENT
2G10>
TXTIP<0>\I
12.7
2F10<
TXCM<0>\I
12.7
4.7UF
T9021
1:2.42
LC01-6
BANTAM
TR250-180
2F10>
TXRING<0>\I
TR250-180
BANTAM
2G6<
RXTIP<0>\I
1:2.42
18.2
LC01-6
TR250-180
2G6<
RXRING<0>\I
TR250-180
RING OPTIONAL CHOKE PLACEMENT
2G10>
TXTIP<1>\I
12.7
1:2.42
BANTAM
4.7UF
2F10<
TXCM<1>\I
12.7
LC01-6
TR250-180
2F10>
TXRING<1>\I
1:2.42
TR250-180
BANTAM LC01-6
2G6<
18.2
RXTIP<1>\I
RXRING<1>\I
TR250-180
2G6<
100K
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu 11:11:58 2001 TITLE: AAL1GATOR_8 COMET_QUAD DESIGN LINE INTERFACE ENGINEER: ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:4 TRUE
REVISIONS
ZONE DESCRIPTION DATE APPR
TR250-180
RING OPTIONAL CHOKE PLACEMENT
2G10>
TXTIP<2>\I
12.7
2F10<
TXCM<2>\I
12.7
4.7UF
T9021
1:2.42
LC01-6
BANTAM
TR250-180
TR10
2F10>
TXRING<2>\I
TR250-180 TR11
RXTIP<2>\I
BANTAM
2G6<
1:2.42
18.2
LC01-6
TR250-180
2G6<
RXRING<2>\I
TR12
TR250-180
RING OPTIONAL CHOKE PLACEMENT
2G10>
12.7
TXTIP<3>\I
1:2.42
TR13
BANTAM
2F10<
TXCM<3>\I
12.7
4.7UF
LC01-6
TR250-180
TR14
2G10>
TXRING<3>\I
1:2.42
TR250-180 TR15
BANTAM LC01-6
2G6<
18.2
RXTIP<3>\I
RXRING<3>\I
TR250-180
2G6<
TR16
PMC-Sierra, Inc.
DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu 11:12:00 2001 DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN LINE INTERFACE ENGINEER: ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:5 TRUE
REVISIONS
ZONE DESCRIPTION DATE APPR
TR250-180
RING OPTIONAL CHOKE PLACEMENT
3G10>
TXTIP<4>\I
12.7
TR17
3F10<
TXCM<4>\I
12.7
4.7UF
T9021
1:2.42
LC01-6
BANTAM
TR250-180
3F10>
TXRING<4>\I
TR18
TR250-180 TR19
BANTAM
18.2
3G6<
RXTIP<4>\I
1:2.42
LC01-6
TR250-180
3G6<
RXRING<4>\I
TR20
TR250-180
RING OPTIONAL CHOKE PLACEMENT
3G10>
TXTIP<5>\I
12.7
1:2.42
TR21
BANTAM
4.7UF
3F10<
TXCM<5>\I
12.7
LC01-6
TR250-180
TR22
3F10>
TXRING<5>\I
1:2.42
TR250-180 TR23
BANTAM LC01-6
3G6<
18.2
RXTIP<5>\I
RXRING<5>\I
TR250-180
3G6<
TR24
PMC-Sierra, Inc.
DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu 11:12:06 2001 DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN LINE INTERFACE ENGINEER: ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:6 TRUE
REVISIONS
ZONE DESCRIPTION DATE APPR
TR250-180
RING OPTIONAL CHOKE PLACEMENT
3G10>
TXTIP<6>\I
12.7
TR25
3F10<
TXCM<6>\I
12.7
4.7UF
T9021
1:2.42
LC01-6
BANTAM
TR250-180
TR26
3F10>
TXRING<6>\I
TR250-180 TR27
RXTIP<6>\I
BANTAM
3G6<
1:2.42
18.2
LC01-6
TR250-180
3G6<
RXRING<6>\I
TR28
TR250-180
RING OPTIONAL CHOKE PLACEMENT
3G10>
12.7
TXTIP<7>\I
1:2.42
TR29
BANTAM
3F10<
TXCM<7>\I
12.7
4.7UF
LC01-6
TR250-180
TR30
3G10>
TXRING<7>\I
1:2.42
TR250-180 TR31
BANTAM LC01-6
3G6<
18.2
RXTIP<7>\I
RXRING<7>\I
TR250-180
3G6<
TR32
PMC-Sierra, Inc.
DRAWING TITLE=LINE_INTERFACE ABBREV=LINE LAST_MODIFIED=Thu 11:12:09 2001 DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN LINE INTERFACE ENGINEER: ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:7 TRUE
REVISIONS
ZONE DESCRIPTION DATE APPR
PLACE EACH SIDE FPGA.
0.1UF 0.1UF C103 0.1UF C104 C102 0.1UF C101
VCCA<9> VCCA<8> VCCA<7> VCCA<6> VCCA<5> VCCA<4> VCCA<3> VCCA<2> VCCA<1> VCCI<8> VCCI<7> VCCI<6> VCCI<5> VCCI<4> VCCI<3> VCCI<2> VCCI<1>
13F5> 13E5> 9C1> 9C1>
RSTB\I CS3B\I RDB\I WRB\I
10D5<>
TL_SYNC<7.0>\I H-MVIP MODE TL_SYNC<0>
10C5<>
TL_CLK<7.0>\I
10E10< 10E10< 10F10>
CGC_VALID\I CGC_SER_D\I CGC_DOUT<3.0>\I
USED EXTERNAL ADAPTIVE ALGORITHM CGC_LINE<3.0>\I 10E10>
10E10> 10E10>
ADAP_STRB\I SRTS_STRB\I
IO_A<41> IO_A<40> IO_A<39> IO_A<38> IO_A<37> IO_A<36> IO_A<35> IO_A<34> IO_A<33> IO_A<32> IO_A<31> IO_A<30> IO_A<29> IO_A<28> IO_A<27> IO_A<26> IO_A<25> IO_A<24> IO_A<23> IO_A<22> IO_A<21> IO_A<20> IO_A<19> IO_A<18> IO_A<17> IO_A<16> IO_A<15> IO_A<14> IO_A<13> IO_A<12> IO_A<11> IO_A<10> IO_A<9> IO_A<8> IO_A<7> IO_A<6> IO_A<5> IO_A<4> IO_A<3> IO_A<2> IO_A<1> IO_B<41> IO_B<40> IO_B<39> IO_B<38> IO_B<37> IO_B<36> IO_B<35> IO_B<34> IO_B<33> IO_B<32> IO_B<31> IO_B<30> IO_B<29> IO_B<28> IO_B<27> IO_B<26> IO_B<25> IO_B<24> IO_B<23> IO_B<22> IO_B<21> IO_B<20> IO_B<19> IO_B<18> IO_B<17> IO_B<16> IO_B<15> IO_B<14> IO_B<13> IO_B<12> IO_B<11> IO_B<10> IO_B<9> IO_B<8> IO_B<7> IO_B<6> IO_B<5> IO_B<4> IO_B<3> IO_B<2> IO_B<1> QCLKA_IO QCLKB_IO MODE DCLK_IO SDI_IO PRA_IO PRB_IO TMS_IO TDI_IO TDO_IO TCK_IO
IO_C<40> IO_C<39> IO_C<38> IO_C<37> IO_C<36> IO_C<35> IO_C<34> IO_C<33> IO_C<32> IO_C<31> IO_C<30> IO_C<29> IO_C<28> IO_C<27> IO_C<26> IO_C<25> IO_C<24> IO_C<23> IO_C<22> IO_C<21> IO_C<20> IO_C<19> IO_C<18> IO_C<17> IO_C<16> IO_C<15> IO_C<14> IO_C<13> IO_C<12> IO_C<11> IO_C<10> IO_C<9> IO_C<8> IO_C<7> IO_C<6> IO_C<5> IO_C<4> IO_C<3> IO_C<2> IO_C<1>
RES_ARRAY_8
BTCLK<7.0>\I
2G6< 3G6<
BTFP<7.0>\I
2G6< 3G6<
50PPM 3.3V 16.384MHZ HCMOS
0.01UF
0.1UF
C100
NC/TS
50PPM 3.3V 4.096MHZ HCMOS
H-MVIP COMMON CLOCK FRAME PLUSE CLOCK
0.01UF
0.1UF
NC/TS
11E7< 9E1<> 3B7<> 2C7<>
RAM_CLK\I COMETQ_FPGA_D<7.0>\I
50PPM 3.3V 38.880MHZ HCMOS
9D1> 10E5<
COMETQ_FPGA_A<2.0>\I AAL1_SYSCLK\I NCLK\I
0.01UF
0.1UF
NC/TS
NETWORK_CLK
HEADER2
IO_D<40> IO_D<39> IO_D<38> IO_D<37> IO_D<36> IO_D<35> IO_D<34> IO_D<33> IO_D<32> IO_D<31> IO_D<30> IO_D<29> IO_D<28> IO_D<27> IO_D<26> IO_D<25> IO_D<24> IO_D<23> IO_D<22> IO_D<21> IO_D<20> IO_D<19> IO_D<18> IO_D<17> IO_D<16> IO_D<15> IO_D<14> IO_D<13> IO_D<12> IO_D<11> IO_D<10> IO_D<9> IO_D<8> IO_D<7> IO_D<6> IO_D<5> IO_D<4> IO_D<3> IO_D<2> IO_D<1> QCLKC_IO QCLKD_IO CLKA_IO CLKB_IO GND_<1> GND_<2> GND_<3> GND_<4> GND_<5> GND_<6> GND_<7> GND_<8> GND_<9> GND_<10> GND_<11> GND_<12> GND_<13>
USED H-MVIP MODE C4B\I C16B\I CMV8MCLK\I CMVFPC\I CMVFPB\I
10B10< 10B5< 2F6< 3F6< 2F6< 3F6< 2F6< 3F6<
XCLK<1.0>\I
2F7< 3F6<
MODE GND, EXCEPT DURING DEVICE PROGRAMMING DEBUGGING
A42MX36_PQ208
NC/TS
50PPM 2.048MHZ HCMOS 3.3V
0.01UF
0.1UF
0.01UF
50PPM 1.544MHZ HCMOS 3.3V
0.1UF
NC/TS
PMC-Sierra, Inc.
P_10 P_11 P_12 P_13 P_14
HDR14
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: DRAWING TITLE=FPGA_BLOCK ABBREV=FPGA_BLOCK LAST_MODIFIED=Thu 11:12:30 2001 TITLE: AAL1GATOR_8 COMET_QUAD DESIGN FPGA BLOCK ENGINEER:
ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:8
REVISIONS
AAL1_A<19.0>\I
ZONE
10G10<
DESCRIPTION
DATE
APPR
74FCT163827
0.01UF
C107 0.01UF
0.01UF
C108 0.01UF
C106 0.01UF C110 0.1UF
PLACE CAPS NEAR EACH
C112 0.1UF
0.1UF
C111 0.1UF
C105
C114
0.1UF
C113
C109
4.7K
163646 CLKAB CLKBA
74FCT
RES_ARRAY_8
74FCT163827
COMETQ_FPGA_D<7.0>\I
2C7<> 3B7<> 8C9<
13E5>
UP_A<21.0>\I
13E5>
DEV_SELB\I
13D10<>
UP_D<15.0>\I AAL1_D<15.0>\I
10F5<>
COMETQ_FPGA_A<10.0>\I
2C10< 3B10< 8C9<
74FCT 163646
74FCT163827
RDB\I
2B7< 3B7< 8G9<
WRB\I
4.7K
CLKAB CLKBA
2B7< 3B7< 8G9<
4.7K
74FCT 163646
MC74HCT138AD
HCT138
DEMUX
13E5> 13E5>
RDB_IN\I WRB_IN\I
74FCT163827
4.7K
13E5>
CS2B\I
CLKAB CLKBA
COMETQ_CSB<1.0>\I
2B7< 3B7<
PMC-Sierra, Inc.
DRAWING TITLE=MEMORY_SYSTEM_BLOCK ABBREV=MEMORY_SYSTEM_BLOCK LAST_MODIFIED=Thu 11:12:43 2001 DOCUMENT NUMBER: 991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN MEMORY SYSTEM BLOCK ENGINEER: ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:9
REVISIONS
ZONE DESCRIPTION DATE APPR
9H6>
AAL1_A<19.0>\I
8E9<
CGC_DOUT<3.0>\I
8E9<
CGC_LINE<3.0>\I SRTS_STRB\I ADAP_STRB\I NCLK\I CGC_SER_D\I CGC_VALID\I
8E9< 8E9< 8C9> 8E9> 8F9>
AA10 AB10 AA12 AB16 AB14 AA15 AB19 AA18 AB18 AA20 AA19 AA16 AA17
AAL1GATOR-8 PM73123 CGC_DOUT3 CGC_DOUT2 CGC_DOUT1 CGC_DOUT0 ACKB CGC_LINE3 INTB CGC_LINE2 TRSTB CGC_LINE1 RSTB CGC_LINE0 SYSCLK SRTS_STB SCAN_MODEB ADAP_STB TCLK NCLK TL_CLK_OE CGC_SER_D CGC_VALID MICRO/JTAG
AAL1GATOR-8 PM73123 PPL_21 PPL_20 PPL_19 PPL_18 PPL_17 PPL_16 PPL_15 PPL_14 PPL_13 PQH_4 PPL_12 PQH_3 PPL_11 PQH_2 PPL_10 PPL_9 PQH_1 PPL_8 PPL_7 PPH_15 PPL_6 PPH_14 PPL_5 PPH_13 PPL_4 PPH_12 PPL_3 PPH_11 PPL_2 PPH_10 PPL_1 PPH_9 PPH_8 PCL_8 PPH_7 PCL_7 PPH_6 PCL_6 PPH_5 PCL_5 PPH_4 PCL_4 PPH_3 PCL_3 PPH_2 PCL_2 PPH_1 PCL_1 PCH_8 PCH_7 PCH_6 PCH_5 PCH_4 PCH_3 PCH_2 PCH_1 PQL_4 PQL_3 PQL_2 PQL_1 POWER SUPPLY
AB11 AB13 AA13 AA14 AA21
AAL1_D<15.0>\I
9D7<>
4.7K
AA11 AB17
4.7K
WRB_IN\I RDB_IN\I AAL1_CSB\I AAL1_ACKB\I AAL1_INTB\I TRSTB\I RSTB\I AAL1_SYSCLK\I TCK\I TMS\I TDI\I AAL1_TDOUT
13E5> 13E5> 13E5> 13E5< 13E2< 13G5> 13F5> 8C9> 13G5> 13H5> 13H5> 11E2<
AB15 AB12 AB21
RL_SYNC<7.0>\I AAL1GATOR-8 PM73123 TL_SYNC7 TL_SYNC6 TL_SYNC5 TL_SYNC4 TL_SYNC3 TL_SYNC2 TL_SYNC1 TL_SYNC0 TL_DATA7 TL_DATA6 TL_DATA5 TL_DATA4 TL_DATA3 TL_DATA2 TL_DATA1 TL_DATA0 TL_SIG7 TL_SIG6 TL_SIG5 TL_SIG4 TL_SIG3 TL_SIG2 TL_SIG1 TL_SIG0 TL_CLK7 TL_CLK6 TL_CLK5 TL_CLK4 TL_CLK3 TL_CLK2 TL_CLK1 TL_CLK0 CTL_CLK LINE_MODE TL_SYNC<7.0>\I
3G2> 2G2>
3F2> 2F2>
RL_DATA<7.0>\I
3G2> 2G2>
RL_SIG<7.0>\I
3G2> 2G2>
RL_CLK<7.0>\I
8E2>
C4B\I C16B USED H-MVIP MODE
AB22 AA22
RL_SYNC7 RL_SYNC6 RL_SYNC5 RL_SYNC4 RL_SYNC3 RL_SYNC2 RL_SYNC1 RL_SYNC0 RL_DATA7 RL_DATA6 RL_DATA5 RL_DATA4 RL_DATA3 RL_DATA2 RL_DATA1 RL_DATA0 RL_SIG7 RL_SIG6 RL_SIG5 RL_SIG4 RL_SIG3 RL_SIG2 RL_SIG1 RL_SIG0 RL_CLK7 RL_CLK6 RL_CLK5 RL_CLK4 RL_CLK3 RL_CLK2 RL_CLK1 RL_CLK0 CRL_CLK
8F9>
TL_DATA<7.0>\I
2F6< 3F6<
TL_SIG<7.0>\I
2G6< 3G6<
TL_CLK<7.0>\I
8F9<>
C16B\I
4.7K
8E2>
LINE INTERFACE
LINE_MODE0 'GND' WHEN DIRECT MODE 'HIGH' WHEN H-MVIP MODE HEADER2
DRAWING: AAL1GATOR_8_1.1 AAL1 11:12:34 2001
0.01UF C127 0.01UF C126 0.01UF C125 0.01UF C124 0.01UF C123 0.01UF C122 0.01UF C121 0.01UF C120 0.01UF 0.01UF 0.01UF C118 0.01UF C117 0.01UF C116 0.01UF
C119
C143
C115
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:10
DECOUPLING CAPS POWER PINS
TITLE: AAL1GATOR_8 COMET_QUAD DESIGN AAL1GATOR-8.1 ENGINEER:
REVISIONS
ZONE DESCRIPTION DATE APPR
INPUT_D<15.0>
RECEPTACLE_RA
RECEPTACLE_RA
AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 PRTY LENB CLAV0 CLAV1 CLAV2 CLAV3 CLKIO EXTREF TRG_IN TRG_OUT
EBBI80
PBGA
AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 PRTY LENB CLAV0 CLAV1 CLAV2 CLAV3 CLKIO EXTREF TRG_IN TRG_OUT
EBBI80
RATM_D15 RATM_D14 RATM_D13 RATM_D12 RATM_D11 RATM_D10 RATM_D9 RATM_D8 RATM_D7 RATM_D6 RATM_D5 RATM_D4 RATM_D3 RATM_D2 RATM_D1 RATM_D0 TPHY_ADD4 TPHY_ADD3 TPHY_ADD2 TPHY_ADD1 TPHY_ADD0 RATM_PAR RATM_ENB RATM_CLAV RATM_CLK RATM_SOC
AAL1GATOR-8 PM73123
OUTPUT_D<15.0> TATM_D15 TATM_D14 TATM_D13 TATM_D12 TATM_D11 TATM_D10 TATM_D9 TATM_D8 TATM_D7 TATM_D6 TATM_D5 TATM_D4 TATM_D3 TATM_D2 TATM_D1 TATM_D0 RPHY_ADD_RSX RPHY_ADD3 RPHY_ADD2 RPHY_ADD1 RPHY_ADD0 TATM_PAR TATM_ENB TATM_CLAV TATM_SOC TATM_CLK
USED AMODE RPHY_ADD<4.0> TATM_PAR TATM_ENB TATM_CLAV TATM_SOC TATM_CLK
UTOPIA INTERFACE
RN10
UTOPIA2 INTERFACE
UTOPIA2 INTERFACE
RATM_ENB RATM_CLAV RATM_CLK TPHY_ADD<4.0> USED AMODE RATM_SOC RATM_PAR
DRAWING: AAL1GATOR_8_1.3 AAL1 11:12:40 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN AAL1GATOR_8.3 ENGINEER: ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:12
REVISIONS
ZONE DESCRIPTION DATE APPR
RAM_D<15.0> RAM_PAR1 RAM_PAR0 RAM_A<16.0> AAL1GATOR-8 PM73123
100MHZ
VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
RAM1_A16 RAM1_A15 RAM1_A14 RAM1_A13 RAM1_A12 RAM1_A11 RAM1_A10 RAM1_A9 RAM1_A8 RAM1_A7 RAM1_A6 RAM1_A5 RAM1_A4 RAM1_A3 RAM1_A2 RAM1_A1 RAM1_A0
RAM1_D15 RAM1_D14 RAM1_D13 RAM1_D12 RAM1_D11 RAM1_D10 RAM1_D9 RAM1_D8 RAM1_D7 RAM1_D6 RAM1_D5 RAM1_D4 RAM1_D3 RAM1_D2 RAM1_D1 RAM1_D0 RAM1_OEB RAM1_WEB1 RAM1_WEB0 RAM1_CSB RAM1_ADSCB RAM1_PAR1 RAM1_PAR0 SCAN_ENB INTERFACE
RAM_WE0B RAM_WE1B RAM_CSB RAM_OEB RAM_R/WB RAM_CLK\I
A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
GS841Z18 (256K
DQA<9> DQA<8> DQA<7> DQA<6> DQA<5> DQA<4> DQA<3> DQA<2> DQA<1> DQB<9> DQB<8> DQB<7> DQB<6> DQB<5> DQB<4> DQB<3> DQB<2> DQB<1>
AAL1_TDOUT AAL1_TDO\I TMS\I TCK\I
10E5> 2B10< 13H5> 13G5>
4.7K
8C9>
4.7K
VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
DRAWING: AAL1GATOR_8_1.2 AAL1 11:12:37 2001
PMC-Sierra, Inc.
0.01UF C131 0.01UF 0.01UF C129 0.01UF C132 C130 C128
0.01UF
0.01UF
C133
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN AAL1GATOR-8.2 ENGINEER:
ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:11
DECOUPLING CAPS
REVISIONS
ZONE
DESCRIPTION
DATE
APPR
4.7K
4.7K
4.7K
C144 0.01UF
0.1UF
HCT08
TRSTB\I
2B10< 3A10< 10E5<
C145
JTAG PORT
TMS\I TDI\I TCK\I TDO1\I
2B10< 3A10< 10E5< 11E2< 10E5< 2B10< 3A10< 10E5< 11E2< 3B10>
PBNO
SENSE HYST
RESET RESET
1.0K
MAX700
RES_ARRAY_15
HCT08
RN11 4.7K
RSTB\I
2B7<
3A7<
8G9<
10E5<
YELLOW YELLOW
COMET-QUADS INTERRUPT LEDS
YELLOW AAL1GATOR-8 INTERRUPT
HCT08
HCT541
9D10<>
UP_D<15.0>\I
DEV_SELB\I
9D5<
AAL1_ACKB\I AAL1_CSB\I CS2B\I CS3B\I RDB_IN\I WRB_IN\I UP_A<21.0>\I
10E5> 10E5< 9A8< 8G9<
4.7K 4.7K
AAL1_INTB\I IRQ2_BUS<1.0>\I
10E5> 2B7> 3A7>
9B8< 10E5< 9B8< 10F5< 9D10<
HCT08
2.5V
C139
0.750A
C140
LT1118CST VOUT
P<1> P<2> P<3> P<4>
SUPER_GREEN
GND1
4.7K
LT1528 SHDN VOUT SENS
47UF 47UF 47UF 47UF
0.47UF
C138
3.000A
C137 C136 C135 C134
VCC1
P<1> P<2> P<3> P<4>
C142 47UF 1.0UF
SUPER_GREEN
SUPER_GREEN
DIN96
C141
CONNECT UNUSED INPUTS
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991089 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR_8 COMET_QUAD DESIGN MICRO_INTERFACE ENGINEER: ISSUE DATE: 00/01/21 REVISION NUMBER: PAGE:13 TRUE
HCT08
DRAWING TITLE=MICRO_INTERFACE ABBREV=MICRO LAST_MODIFIED=Thu 11:12:14 2001
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
NOTES
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-1991089 ISSUE
PM73123 AAL1GATOR-8 PM4354 COMET-QUAD
AAL1GATOR-8 REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, Canada Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Site:
None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement. event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage. 2001 PMC-Sierra, Inc. PMC-1991089 (P2) Issue date: June 2001
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL

PM73123 AAL1GATOR-8 PM4354 COMET-QUAD AAL1GATOR-8 REFERENCE DESIG

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