Freescale Semiconductor, Inc. Introduction Introduction Modi

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DSP56309UMAD/D Rev. 11/2002 DSP56309 User's Manual
Freescale Semiconductor, Inc.
Introduction
Introduction Modified Signal Definitions Operating Mode Register (OMR) Layout Definition.3 Receive Register (SRX) Description Updated Programming Sheets.3
This document provides updated information revision DSP56309 User's Manual (DSP56309UM/D). updates include following: Modified signal definitions Operating Mode Register (OMR) layout definitions Updated Receive Register (SRX) description Updated Timer Registers (TLR, TCPR, TCR) programming sheets
Modified Signal Definitions
Change Description
Change Ground (GND) Ground (GND)5. Note follows: number Ground signals listed 144-pin TQFP package. 196-ball MAP-BGA package, there connections. Change HA10 HA10 Change Change AA0-AA3 AA0-AA3 Change Change Grounds: Grounds4: bottom figure, following note: signals listed 144-pin TQFP package. 196-ball MAP-BGA package, grounds except GNDP GNDP1 connected together referenced GND. There connections.
Area Change
Table 2-1,
Figure 2-1,
Table 2-3,
Change note table following: Note: subsystem signals (GNDQ, GNDA, GNDD, GNDC, GNDH, GNDS) listed 144-pin TQFP package. 196-ball MAP-BGA package, grounds except GNDP GNDP1 connected together inside package referenced GND.
Table 2-8, 2-11 2-12
Change signal State During Reset, Stop, Wait
Reset: Output (deasserted) State during Stop/Wait depends setting: Output, deasserted Maintains last state (that asserted, remains asserted) Change signal State During Reset, Stop, Wait Ignored input
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Modified Signal Definitions
Area Change
Table 2-11, 2-17 2-21
Change Description
Change title third column State During Reset1,2. following notes table: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. Change State During Reset Stop signals Ignored input. Change signal description PB14 Port B14-When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. Change title third column State During Reset1,2. Change State During Reset signals Ignored input. notes that state: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. signals, delete middle paragraph signal description. ESSI0 does support keeper circuits. signals, change PCR0 PCRC PRR0 PRRC. Change title third column State During Reset1,2. Change State During Reset signals Ignored input. notes that state: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. signals, delete middle paragraph signal description. ESSI1 does support keeper circuits. signals, change PCR1 PCRD PRR1 PRRD. Change title third column State During Reset1,2. Change State During Reset signals Ignored input. notes that state: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. signals, delete middle paragraph signal description. does support keeper circuits. signals, change PCRE PRRE. Change title third column State During Reset1,2. Change State During Reset signals Ignored input. notes that state: Notes: Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, these lines tri-stated. Wait processing state does affect signal state. signals, delete middle paragraph signal description. triple timer module does support keeper circuits.
Table 2-12, 2-22 2-25
Freescale Semiconductor, Inc.
Table 2-13, 2-26 2-28
Table 2-14, 2-29 2-30
Table 2-15, 2-31
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Operating Mode Register (OMR) Layout Definition
Operating Mode Register (OMR) Layout Definition
Area Change
Figure 4-3, 4-17 Replace with following:
Change Description
Stack Control/Status (SCS)
Extended Operating Mode (EOM)
Chip Operating Mode (COM)
CDP[1-0]
Reset:
After reset, these bits reflect corresponding value mode input (that MODD, MODC, MODB, MODA, respectively). ATE-Address Tracing Enable APD-Address Priority Disable ABE-Asynch. Arbitration Enable BRT-Bus Release Timing TAS-TA Synchronize Select BE-Burst Mode Enable CDP1-Core-DMA Priority CDP0-Core-DMA Priority Reserved bit. Read zero; write zero future compatibility MS-Memory Switch Mode SD-Stop Delay EBD-External Disable MD-Operating Mode MC-Operating Mode MB-Operating Mode MA-Operating Mode
Freescale Semiconductor, Inc.
SEN-Stack Extension Enable WRP-Extended Stack Wrap Flag EOV-Extended Stack Overflow Flag EUN-Extended Stack Underflow Flag XYS-Stack Extension Space Select
Figure 4-3. Operating Mode Register (OMR)
Receive Register (SRX) Description
Area Change
Section 8.6.4.1, 8-20
Change Description
Change beginning fourth paragraph from Synchronous mode" Asynchronous mode".
Updated Programming Sheets
following examples replace Figure Figure D-21 DSP56309 User's Manual.
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Central Processor
Asynchronous Arbitration Enable, Synchronization disabled Synchronization enabled Release Timing, Fast Release mode Slow Release mode Chip Operating Mode, Bits Refer operating modes table Chapter External Disable, Enables external Disables external Stop Delay Mode, Delay 128K clock cycles Delay clock cycles Memory Switch Mode, Memory switching disabled Memory switching enabled Core-DMA Priority, Bits CPD[1:0] Description Compare SR[CP] active channel priority higher priority than core same priority core lower priority than core Cache Burst Mode Enable, Burst Mode disabled Burst Mode enabled Synchronize Select, synchronized Synchronized
Freescale Semiconductor, Inc.
Address Attribute Priority Disable, Priority mechanism enabled Priority mechanism disabled Address Trace Enable, Address Trace mode disabled Address Trace mode enabled Stack Extension Select, Mapped memory Mapped memory Stack Extension Underflow Flag, stack underflow Stack underflow Stack Extension Overflow Flag, stack overflow Stack overflow Stack Extension Wrap Flag, stack extension wrap Stack extension wrap (sticky bit) Stack Extension Enable, Stack extension disabled Stack extension enabled
CPD1 CPD0
Operating Mode Register Reset $00030X; latched from levels Mode pins
Reserved, Program
Figure D-2. Operating Mode Register (OMR)
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Updated Programming Sheets
Application:
Date: Programmer:
Sheet
Timers
Timer Reload Value
Freescale Semiconductor, Inc.
Timer Load Register
Reset $xxxxxx, value indeterminate after reset
TLR0-X:$FFFF8E Write Only TLR1-X:$FFFF8A Write Only TLR2-X:$FFFF86 Write Only
Value Compared Counter Value
Timer Compare Register
Reset $xxxxxx, value indeterminate after reset
TCPR0-X:$FFFF8D Read/Write TCPR1-X:$FFFF89 Read/Write TCPR2-X:$FFFF85 Read/Write
Timer Count Value
Timer Count Register
Reset $000000
TCR0-X:$FFFF8C Read Only TCR1-X:$FFFF88 Read Only TCR2-X:$FFFF84 Read Only
Figure D-21. Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
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Updated Programming Sheets
Freescale Semiconductor, Inc.
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Updated Programming Sheets
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
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DSP56309UMAD/D

Freescale Semiconductor, Inc. Introduction Introduction Modi

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