LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR FEATURES
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ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
FEATURES
Three banks outputs: bank LVDS outputs banks LVPECL output Selectable crystal oscillator interface LVCMOS/LVTTL single-ended reference clock input independently selectable output frequency each bank: 318.7MHz, 212.5MHz, 159.375MHz 106.25MHz Maximum output frequency: 318.75MHz Crystal input frequency: 25.5MHz VDDO_LVPECL 3.3V 2.5V, allowing device generate 3.3V 2.5V LVPECL levels phase jitter 106.25MHz, using 25.5MHz crystal (637KHz 10Mhz intergration): 4.82ps (typical)
GENERAL DESCRIPTION
ICS843404 phase noise Fibre Channel Clock Generator member HiPerClockSHiPerClockSfamily high performance clock solutions from ICS. device provides banks LVPECL output bank bank LVDS outputs. Each bank independently using their respective frequency select pins following output frequencies: 318.75MHz, 212.5MHz, 159.375MHz 106.25MHz, using 25.5MHz 18pF parallel resonant crystal. ICS843404 also driven from 25.5MHz singleended reference clock. system debug test purposes, bypassed using VCO_SEL pin.
ASSIGNMENT
VCO_SEL o_LVDS LVDS0 nLVDS0 LVDS1 nLVDS1 LVPECL_FSELB0 LVPECL_FSELB1 VDDA LVPECL_FSELA0 LVDS_FSEL0 LVDS_FSEL1 VDDO _LVPECL LVPECLA0 nLVPECLA0 LVPECLB0 nLVPECLB0 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT LVPECL_FSELA1
Phase noise 106.25MHz Offset Noise Power 100Hz -84.6 dBc/Hz 1KHz -105.7 dBc/Hz 10KHz -122.3 dBc/Hz 100KHz -125.9 dBc/Hz Supply voltage modes: VDDA 3.3V VDDO_LVPECL 3.3V 2.5V VDDO_LVDS 3.3V 70°C ambient operating temperature Lead-Free package available Industrial termperature information available upon request
ICS843404
28-Lead TSSOP, 173-MIL 4.4mm 9.7mm 0.92mm body package Package View
BLOCK DIAGRAM
VCO_SEL Pullup
LVPECL_FSELA1:0
VDDO_LVPECL
LVPECLA0 nLVPECLA0
TEST_CLK Pulldown
25.5MHz
LVPECL_FSELB1:0
LVPECLB0 nLVPECLB0
XTAL_IN XTAL_OUT XTAL_SEL Pullup
Phase Detector
637.5MHz
(Fixed)
LVDS_FSEL1:0
LVDS0 nLVDS0
(fixed)
LVDS1 nLVDS1 Pulldown
VDDO_LVDS
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice. 843404AG REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
Type Description Active HIGH Master Reset. When logic HIGH, internal dividers reset causing true outputs LVPECLx/LVDSx Pulldown inver outputs nLVPECLx/nLVDSx high. When logic LOW, internal dividers outputs enabled. LVCMOS/LVTTL interface levels. select pin. When HIGH, enabled. When LOW, Pullup Bypass mode. LVCMOS/LVTTL interface levels. Output supply LVDS outputs. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. connect. Frequency select LVPECLB outputs. Table Pulldown LVCMOS/LVTTL interface levels. Frequency select LVPECLB outputs. Table Pullup LVCMOS/LVTTL interface levels. Analog supply pin. Frequency select LVPECLA outputs. Table Pulldown LVCMOS/LVTTL interface levels. Core supply pin. Frequency select LVPECLA outputs. Table Pullup LVCMOS/LVTTL interface levels. Parallel resonant ystal interface. XTAL_IN input, XTAL_OUT output. Negative supply pin. Pulldown LVCMOS/LVTTL clock input. Selects between ystal TEST_CLK inputs Pullup Reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS/LVTTL interface levels.
TABLE DESCRIPTIONS
Number Name
Input
VCO_SEL VDDO_LVDS LVDS0, nLVDS0 LVDS1, nLVDS1 LVPECL_FSELB0 LVPECL_FSELB1 VDDA LVPECL_FSELA0 LVPECL_FSELA1 XTAL_OUT, XTAL_IN TEST_CLK XTAL_SEL
Input Power Output Output Unused Input Input Power Input Power Input Input Power Input Input
nLVPECLB0, Output Differential output pair. LVPECL interface levels. LVPECLB0 nLVPECLA0, Ouput Differential output pair. LVPECL interface levels. LVPECLA0 VDDO_LVPECL Power Output supply LVPECL outputs. LVDS_FSEL1, Frequency select pins LVDS outputs. Table Input Pulldown LVDS_FSEL0 LVCMOS/LVTTL interface levels. NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
LVDS Output Frequency (MHz) (25.5MHz Crystal) 318.75 (default) 212.5 159.375 106.25
TABLE LVDS FREQUENCY SELECT FUNCTION TABLE
Inputs LVDS_FSEL1 LVDS_FSEL0 LVDS Output Divider
TABLE LVPECLA0 FREQUENCY SELECT FUNCTION TABLE
Inputs LVPECL_FSELA1 LVPECL_FSELA0 LVPECLA0 Output Divider LVPECLA0 Output Frequency (MHz) (25.5MHz Crystal) 318.75 212.5 159.375 (default) 106.25
TABLE LVPECLB0 FREQUENCY SELECT FUNCTION TABLE
Inputs LVPECL_FSELB1 LVPECL_FSELB0 LVPECLB0 Output Divider LVPECLB0 Output Frequency (MHz) (25.5MHz Crystal) 318.75 212.5 159.375 (default) 106.25
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
4.6V -0.5V 0.5V 50mA 100mA 10mA 15mA 49.8°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, (LVPECL Outputs) Continuous Current Surge Current Outputs, (LVDS Outputs) Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
istics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE LVPECL POWER SUPPLY CHARACTERISTICS, VDDO 3.3V±5%, VDDA 2.9V 3.465V, 70°C
Symbol VDDA VDDO_LVPECL IDDA IDDO_LVPECL Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVPECL POWER SUPPLY CHARACTERISTICS, 3.3V±5%, VDDA 2.9V 3.465V, VDDO 2.5V±5%,
70°C Symbol VDDA VDDO_LVPECL IDDA IDDO_LVPECL Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 2.375 Typical Maximum 3.465 3.465 2.625 Units
TABLE LVDS POWER SUPPLY CHARACTERISTICS, VDDO 3.3V±5%, VDDA 2.9V 3.465V, 70°C
Symbol VDDA VDDO_LVDS IDDA IDDO_LVDS
843404AG
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current
Test Conditions
Minimum 3.135 3.135
Typical
Maximum 3.465 3.465 3.465
Units
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
TABLE LVCMOS LVTTL CHARACTERISTICS, 3.3V±5%, VDDO 3.3V±5% 2.5V±5%, VDDA 2.9V 3.465V,
70°C
Symbol Parameter Input High Voltage VCO_SEL, XTAL_SEL, LVPECL_FSELA0:F_SELA1, Input LVPECL_FSELB0:F_SELB1 Voltage LVDS_FSEL0:F_SEL1, TEST_CLK TEST_CLK, LVPECL_FSELA0, LVPECL_FSELB0, Input LVDS_FSEL0, LVDS_FSEL1 High Current LVPECL_FSELA1, LVPECL_FSELB1, VCO_SEL, XTAL_SEL TEST_CLK, LVPECL_FSELA0, LVPECL_FSELB0, Input LVDS_FSEL0, LVDS_FSEL1 Current LVPECL_FSELA1, LVPECL_FSELB1, VCO_SEL, XTAL_SEL
Test Conditions
Minimum Typical -0.3 -0.3
Maximum
Units
3.465V,
3.465V,
3.465V,
3.465V,
-150
TABLE LVPECL CHARACTERISTICS, 3.3V±5%, VDDO 3.3V±5% 2.5V±5%, VDDA 2.9V 3.465V,
70°C Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum VDDO VDDO Typical Maximum VDDO VDDO Units
NOTE Outputs terminated with VDDO
TABLE LVDS CHARACTERISTICS, VDDO 3.3V±5%, VDDA 2.9V 3.465V, 70°C
Symbol Parameter Differential Output Voltage Magnitude Change Offset Voltage Magnitude Change Test Conditions Minimum Typical 1.35 Maximum Units
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using 18pf parallel resonant crystal.
843404AG
Test Conditions
Minimum
Typical Maximum 25.5
Units
Fundamental
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
Test Conditions Minimum Typical 318.75MHz (12KHz 20MHz) 5.64 2.82 5.77 4.82 212.5MHz (1.274MHz 20MHz) 159.375MHz (12k 20MHz) 106.25MHz (637KHz 10MHz) Maximum 318.75 Units
TABLE LVPECL CHARACTERISTICS, VDDO 3.3V±5%, VDDA 2.9V 3.465V, 70°C
Symbol fMAX Parameter Output Frequency Bank Skew; NOTE Output Skew; NOTE Phase Jitter, (Random); NOTE Lock Time Output Rise/Fall Time
tsk(b) tsk(o)
Output Duty Cycle NOTE Defined skew within bank ourputs same voltages with equal load conditions. NOTE Defined skew between outputs same supply voltages with equal load conditions. Measured differential cross point. NOTE This parameter defined accordance with JEDEC Standard NOTE Please refer Phase Noise Plots.
TABLE LVPECL CHARACTERISTICS, 3.3V±5%, VDDA 2.9V 3.465V, VDDO 2.5V±5%, 70°C
Symbol fMAX Parameter Output Frequency Bank Skew; NOTE Output Skew; NOTE 318.75MHz (12KHz 20MHz) Phase Jitter, (Random); NOTE Lock Time Output Rise/Fall Time 212.5MHz (1.274MHz 20MHz) 159.375MHz(12k 20MHz) 106.25MHz (637KHz 10MHz) 5.03 2.73 4.60 3.96 Test Conditions Minimum Typical Maximum 318.75 Units
tsk(b) tsk(o)
Output Duty Cycle NOTES through above.
TABLE LVDS CHARACTERISTICS, VDDO 3.3V±5%, VDDA 2.9V 3.465V, 70°C
Symbol fMAX Parameter Output Frequency Bank Skew; NOTE Output Skew; NOTE 318.75MHz (12KHz 20MHz) Phase Jitter, (Random); NOTE Lock Time Output Rise/Fall Time 212.5MHz (1.274MHz 20MHz) 159.375MHz(12k 20MHz) 106.25MHz (637KHz 10MHz) 4.25 4.19 4.30 3.78 Test Conditions Minimum Typical Maximum 318.75 Units
tsk(b) tsk(o)
Output Duty Cycle NOTES through above.
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
Fibre Channel Filter 106.25MHz
Phase Jitter (Random) 637KHz 10MHz 4.82ps (typical)
TYPICAL PHASE NOISE 106.25MHZ LVPECL
NOISE POWER
-100 -110 -120 -130 -140 -150 -170 -180 -190 -160
Phase Noise Data
Phase Noise Result adding Fibre Channel Filter data
100k 100M
TYPICAL PHASE NOISE 106.25MHZ LVDS
Fibre Channel Filter 106.25MHz
Phase Jitter (Random) 637KHz 10MHz 3.78ps (typical)
NOISE POWER
-100 -110 -120 -130 -140 -150 -160 -170 -180 -190
843404AG
OFFSET FREQUENCY (HZ) Phase Noise Data
Phase Noise Result adding Fibre Channel Filter data
100k 100M
OFFSET FREQUENCY (HZ)
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VDD, VDDA, VDDO
SCOPE
SCOPE
3.3V±5% Power Supply Float
LVPECL
LVDS
-1.3V±0.165V
LVPECL 3.3V CORE/3.3V OUTPUT LOAD TEST CIRCUIT
LVDS 3.3V CORE/3.3V OUTPUT LOAD TEST CIRCUIT
2.8V±0.04V
Phase Noise Plot
Noise Power
VDD, VDDA, VDDO
SCOPE
LVPECL
Phase Noise Mask
-0.5V±0.125V
Offset Frequency
Jitter Area Under Masked Phase Noise Plot
LVPECL 3.3V CORE/2.5V OUTPUT LOAD TEST CIRCUIT
PHASE JITTER
nLVPECLx, nLVDSx LVPECLx, LVDSx nLVPECLy, nLVDSy LVPECLy, LVDSy
nLVPECLx, nLVDSx LVPECLx, LVDSx
Pulse Width PERIOD
sk(o)
OUTPUT SKEW
843404AG
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
nLVPECLA0
LVPECLA0 nLVPECLB1 LVPECLB1
LVDS
Clock Outputs
sk(b)
LVPECL BANK SKEW
nLVDS0
LVDS0 nLVDS1 LVDS1
LVPECL
Clock Outputs
sk(b)
LVDS BANK SKEW BANK SKEW (MAXIMUM
VALUE)
OUTPUT RISE/FALL TIME
Input
LVDS
VOD/
Input
LVDS
VOS/
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS843404 provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA.
3.3V .01µF VDDA .01µF 10µF
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
ICS843404 been characterized with 18pF parallel resonant crystals. capacitor values shown Figure below were determined using 25.5MHz 18pF parallel resonant crystal were chosen minimize error.
XTAL_OUT 18pF Parallel Crystal XTAL_IN
ICS843404
Figure CRYSTAL INPUt INTERFACE
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
receiver input. multiple LVDS outputs buffer, only partial outputs used, recommended terminate un-used outputs.
3.3V
LVDS DRIVER TERMINATION
general LVDS interface shown Figure differential transmission line environment, LVDS drivers require matched load termination across near
3.3V
LVDS_Driv
Differiential Transmission Line Differential Transmission Line
FIGURE TYPICAL LVDS DRIVER TERMINATION
TERMINATION
3.3V LVPECL OUTPUT
designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
ground level. Figure eliminated termination shown Figure
TERMINATION 2.5V LVPECL OUTPUT
Figure Figure show examples termination 2.5V LVPECL driver. These terminations equivalent terminating VDDO 2.5V, VDDO very close
2.5V
2.5V
VDDO=2.5V
2.5V
VDDO=2.5V
2,5V LVPECL Driv
2,5V LVPECL Driv
62.5
62.5
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VDDO=2.5V
2,5V LVPECL Driv
FIGURE 2.5V LVPECL TERMINATION EXAMPLE
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
resonant 25.5MHz crystal used. C1=27pF C2=33pF recommended frequency accuracy. different board layout, slightly adjusted optimizing frequency accuracy.
LAYOUT GUIDELINE
Figure shows schematic example ICS843404. example LVEPCL termination shown this schematic. Additional LVPECL termination approaches shown LVPECL Termination Application Note. this example, 18pF parallel
VDDO
LVDS_FSEL0 LVDS_FSEL1 VCO_SEL VDDO_LVDS VDDO_LVPECL LVPECLA0 LVDS0 nLVPECLA0 nLVDS0 LVPECLB0 LVDS1 nLVPECLB0 nLVDS1 XTAL_SEL LVPECL_FSELB0 TEST_CLK LVPECL_FSELB1 VDDA XTAL_IN LVPECL_FSELA0 XTAL_OUT LVPECL_FSELA1
ICS843404
0.1u
25.5
18pF
22pF
0.1u
(U1,3)
0.1u
VDDO
(U1,26)
0.1u
3.3V VDDO 3.3V
FIGURE ICS843404 SCHEMATIC EXAMPLE
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR RELIABILITY INFORMATION
TABLE
JAVS. FLOW TABLE LEAD TSSOP
Velocity (Linear Feet Minute)
68.7°C/W 43.9°C/W
60.5°C/W 41.2°C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
82.9°C/W 49.8°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS843404 2314
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
LEAD TSSOP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
SYMBOL 0.45 -4.30 0.65 BASIC 0.75 0.10 -0.05 0.80 0.19 0.09 9.60 6.40 BASIC 4.50 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 9.80 Maximum
Reference Document: JEDEC Publication MO-153
843404AG
REV. JUNE 2004
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL LVDS CLOCK GENERATOR
Package Lead TSSOP Lead TSSOP Tape Reel Lead "Lead Free" TSSOP Lead "Lead Free" TSSOP Tape Reel Count tube 1000 tube 1000 Temperature 70°C 70°C 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS843404AG ICS843404AGT ICS843404AGLF ICS843404AGLFT Marking ICS843404AG ICS843404AG ICS843404AGLF ICS843404AGLF
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843404AG
REV. JUNE 2004
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