Topic Page Overview Signal/Connection Descriptions .1-1 Specifications
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DSP56366/D Rev. 1.6, 01/2004 24-Bit Audio Digital Signal Processor
Topic Page Overview Signal/Connection Descriptions .1-1 Specifications .2-1 Packaging .3-1 Design Considerations .4-1 Ordering Information .5-1 Power Consumption Benchmark IBIS Model
Overview
DSP56366 supports digital audio applications requiring sound field processing, acoustic equalization, other digital audio algorithms. DSP56366 uses high performance, single-clock-per-cycle DSP56300 core family programmable CMOS digital signal processors (DSPs) combined with audio signal processing capability Motorola SymphonyDSP family, shown Figure This design provides two-fold performance increase over Motorola's popular Symphony family DSPs while retaining code compatibility. Significant architectural enhancements include barrel shifter, 24-bit addressing, instruction cache, direct memory access (DMA). DSP56366 offers million instructions second (MIPS) using internal clock
Data Sheet Conventions
This data sheet uses following conventions: OVERBAR "asserted" "deasserted" Examples: Used indicate signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/ Symbol Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage*
Note: *Values VIL, VOL, VIH, defined individual product specifications.
This document contains information product. Specifications information herein subject change without notice.
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Overview Features
MEMORY EXPANSION AREA
TRIPLE TIMER
(SPDIF Tx.)
HOST INTER
ESAI INTERFACE ESAI_1
INTER
PROGRA /INSTR. CACHE
PM_EB
MEMOR
XM_EB
MEMOR
YM_EB
EXTERNAL ADDRESS SWITCH
PIO_EB
PERIPHERAL EXPANSION AREA
ADDRESS GENERATI CHANNEL
ADDRESS
24-BIT DSP563
DRAM SRAM EXTERN DATA
CONTROL
INTER
DATA
POWE CLOCK PROGR PROGR PROGR DATA 24X24+56->56-BIT JTAG OnCE
EXTAL RESET PINIT/NMI
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
BITS
Figure DSP56366 Block Diagram
Features
DSP56300 Modular Chassis
Million Instructions Second (MIPS) with clock 3.3V. Object Code Compatible with core. Data with multiplier-accumulator 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support instruction cache support. Six-channel controller.
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Overview Features
based clocking with wide range frequency multiplications 4096), predivider factors power saving clock divider (2i: Reduces clock noise. Internal address tracing support OnCE Hardware/Software debugging. JTAG port. Very low-power CMOS design, fully static design with operating frequencies down STOP WAIT low-power standby modes.
On-chip Memory Configuration
7Kx24 Y-Data 8Kx24 Y-Data ROM. 13Kx24 X-Data 32Kx24 X-Data ROM. 40Kx24 Program ROM. 3Kx24 Program 192x24 Bootstrap ROM. Program used Instruction Cache Program patching. 2Kx24 from Data 5Kx24 from Data switched Program resulting 10Kx24 Program RAM.
Off-chip Memory Expansion
External Memory Expansion Port. Off-chip expansion 24-bit word Data memory. Off-chip expansion 24-bit word Program memory. Simultaneous glueless interface SRAM DRAM.
Peripheral Modules
Serial Audio Interface (ESAI): receivers transmitters, master slave. I2S, Sony, AC97, network other programmable protocols. Serial Audio Interface I(ESAI_1): receivers transmitters, master slave. I2S, Sony, AC97, network other programmable protocols ESAI_1 shares four data pins with ESAI, ESAI_1 does support HCKR HCKT (high frequency clocks) Serial Host Interface (SHI): protocols, multi master capability, 10-word receive FIFO, support 24-bit words. Byte-wide parallel Host Interface (HDI08) with support. Triple Timer module (TEC). Digital Audio Transmitter (DAX): serial transmitter capable supporting SPDIF, IEC958, CP-340 AES/EBU digital audio formats. Pins unused peripherals (except SHI) programmed GPIO lines.
Packaging
144-pin plastic LQFP package.
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Overview Documentation
Documentation
Table lists documents that provide complete description DSP56366 required design properly with part. Documentation available from local Motorola distributor, Motorola semiconductor sales office, Motorola Literature Distribution Center, through Motorola home page Internet (the source latest information).
Table
Document Name DSP56300 Family Manual
DSP56366 Documentation
Description Order Number DSP56300FM/AD
Detailed description 56000-family architecture 24-bit core processor instruction Detailed description memory, peripherals, interfaces Electrical timing specifications; package descriptions Brief description chip
DSP56366 User's Manual DSP56366 Technical Data Sheet DSP56366 Product Brief
DSP56366UM/D DSP56366/D DSP56366P/D
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SECTION SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
input output signals DSP56366 organized into functional groups, which listed Table illustrated Figure 1-1. DSP56366 operated from supply; however, some inputs tolerate special notice this feature added signal descriptions those inputs.
Table DSP56366 Functional Signal Groupings Functional Group
Power (VCC) Ground (GND) Clock Address Data control Interrupt mode control HDI08 ESAI ESAI_1 Digital audio transmitter (DAX) Timer JTAG/OnCE Port
Notes:
Number Signals
Detailed Description
Figure Figure Figure Figure Figure Figure Figure Table Figure 1-10 Table 1-11 Table 1-12 Table 1-13 Table 1-14 Figure 1-15
Port Port Port Port Port
Port external memory interface port, including external address bus, data bus, control signals. Port signals GPIO port signals which multiplexed with HDI08 signals. Port signals GPIO port signals which multiplexed with ESAI signals. Port signals GPIO port signals which multiplexed with signals. Port signals GPIO port signals which multiplexed with ESAI_1 signals.
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Signal/Connection Descriptions Signal Groupings
PORT ADDRESS
A0-A17 VCCA GNDA
DSP56366
OnCE ON-CHIP EMULATION/ JTAG PORT
PORT DATA
D0-D23 VCCD GNDD
PARALLEL HOST PORT (HDI08) Port
HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] HRW/HRD [PB11] HDS/HWR [PB12] HCS/HA10 [PB13] HOREQ/HTRQ [PB14] HACK/HRRQ [PB15] VCCH GNDH
PORT CONTROL
AA0-AA2/RAS0-RAS2 VCCC GNDC
SERIAL AUDIO INTERFACE (ESAI)
SCKT[PC3]
Port
[PC4] HCKT [PC5] SCKR [PC0] [PC1] HCKR [PC2] SDO0[PC11] SDO0_1[PE11] SDO1[PC10] SDO1_1[PE10] SDO2/SDI3[PC9] SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] SDO3_1/SDI2_1[PE8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6]
INTERRUPT MODE CONTROL
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET
CLOCK
EXTAL PINIT/NMI PCAP VCCP GNDP
SERIAL AUDIO INTERFACE(ESAI_1)
SCKT_1[PE3]
Port
T_1[PE4] SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS GNDS
QUIET POWER
VCCQH VCCQL GNDQ
SPDIF TRANSMITTER (DAX)
[PD1] [PD0]
Port
SERIAL HOST INTERFACE (SHI)
MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ
TIMER
TIO0 [TIO0]
Figure Signals Identified Functional Group
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Signal/Connection Descriptions Power
POWER
Table Power Inputs Power Name
VCCP
Description
Power-VCCP dedicated use. voltage should well-regulated input should provided with extremely impedance path power rail. There VCCP input. Quiet Core (Low) Power-VCCQL isolated power internal processing logic. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCQL inputs. Quiet External (High) Power-VCCQH quiet power source lines. This input must tied externally other chip power inputs. user must provide adequate decoupling capacitors. There three VCCQH inputs. Address Power-VCCA isolated power sections address drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There three VCCA inputs. Data Power-VCCD isolated power sections data drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCD inputs. Control Power-VCCC isolated power control drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCC inputs. Host Power-VCCH isolated power HDI08 drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCH input. SHI, ESAI, ESAI_1, Timer Power -VCCS isolated power SHI, ESAI, ESAI_1, Timer. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCS inputs.
VCCQL
VCCQH
VCCA
VCCD
VCCC
VCCH
VCCS
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Signal/Connection Descriptions Ground
GROUND
Table Grounds
Ground Name
GNDP
Description
Ground-GNDP ground dedicated use. connection should provided with extremely low-impedance path ground. VCCP should bypassed GNDP 0.47 capacitor located close possible chip package. There GNDP connection. Quiet Ground-GNDQ isolated ground internal processing logic. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDQ connections. Address Ground-GNDA isolated ground sections address drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDA connections. Data Ground-GNDD isolated ground sections data drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDD connections. Control Ground-GNDC isolated ground control drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDC connections. Host Ground-GNDh isolated ground HD08 drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDH connection. SHI, ESAI, ESAI_1, Timer Ground-GNDS isolated ground SHI, ESAI, ESAI_1, Timer. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDS connections.
GNDQ
GNDA
GNDD
GNDC
GNDH
GNDS
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Signal/Connection Descriptions Clock
CLOCK
Table Clock Signals
Signal Name
EXTAL
Type
State during Reset
Input
Signal Description
Input
External Clock Input-An external clock source must connected EXTAL order supply clock internal clock generator PLL. This input cannot tolerate
PCAP
Input
Input
Capacitor-PCAP input connecting off-chip capacitor filter. Connect capacitor terminal PCAP other terminal VCCP. used, PCAP tied VCC, GND, left floating.
PINIT/N
Input
Input
Initial/Nonmaskable Interrupt-During assertion RESET, value PINIT/NMI written into Enable (PEN) control register, determining whether enabled disabled. After RESET assertion during normal instruction processing, PINIT/NMI Schmitt-trigger input negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized internal system clock. This input cannot tolerate
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Signal/Connection Descriptions External Memory Expansion Port (Port
EXTERNAL MEMORY EXPANSION PORT (PORT
When DSP56366 enters low-power standby mode (stop wait), releases mastership tri-states relevant port signals: A0-A17, D0-D23, AA0/RAS0-AA2/RAS2, CAS.
1.5.1
External Address
Table External Address Signals
Signal Name
A0-A17
Type
State during Reset
Tri-stated
Signal Description
Output
Address Bus-When master, A0-A17 active-high outputs that specify address external program data memory accesses. Otherwise, signals tri-stated. minimize power dissipation, A0-A17 change state when external memory spaces being accessed.
1.5.2
External Data
Table External Data Signals
Signal Name
D0-D23
Type
State during Reset
Tri-stated
Signal Description
Input/Output
Data Bus-When master, D0-D23 active-high, bidirectional input/outputs that provide bidirectional data external program data memory accesses. Otherwise, D0-D23 tri-stated.
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Signal/Connection Descriptions External Memory Expansion Port (Port
1.5.3
External Control
Table External Control Signals
Signal Name
AA0-AA2/ RAS0-RAS2
Type
State during Reset
Tri-stated
Signal Description
Output
Address Attribute Address Strobe-When defined these signals used chip selects additional address lines. When defined RAS, these signals used DRAM interface. These signals tri-statable outputs with programmable polarity. Column Address Strobe- When master, active-low output used DRAM strobe column address. Otherwise, mastership enable (BME) DRAM control register cleared, signal tri-stated. Read Enable-When master, active-low output that asserted read external memory data (D0-D23). Otherwise, tri-stated. Write Enable-When master, active-low output that asserted write external memory data (D0-D23). Otherwise, tri-stated.
Output
Tri-stated
Output
Tri-stated
Output
Tri-stated
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Signal/Connection Descriptions External Memory Expansion Port (Port Table External Control Signals (continued) Signal Name
Type
State during Reset
Ignored Input
Signal Description
Input
Transfer Acknowledge-If master there external activity, master, input ignored. input data transfer acknowledge (DTACK) function that extend external cycle indefinitely. number wait states .infinity) added wait states inserted keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. current cycle completes clock period after asserted synchronous internal system clock. number wait states determined input control register (BCR), whichever longer. used minimum number wait states external cycles. order functionality, must programmed least wait state. zero wait state access cannot extended deassertion, otherwise improper operation result. operate synchronously asynchronously, depending setting operating mode register (OMR). functionality used while performing DRAM type accesses, otherwise improper operation result.
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Signal/Connection Descriptions External Memory Expansion Port (Port Table External Control Signals (continued) Signal Name
Type
State during Reset
Output (deasserted)
Signal Description
Output
Request-BR active-low output, never tri-stated. asserted when requests mastership. deasserted when longer needs bus. asserted deasserted independent whether DSP56366 master slave. "parking" allows deasserted even though DSP56366 master. (See description "parking" signal description.) request hold (BRH) allows asserted under software control even though does need bus. typically sent external arbitrator that controls priority, parking, tenure each master same external bus. only affected requests external bus, never internal bus. During hardware reset, deasserted arbitration reset slave state. Grant-BG active-low input. asserted external arbitration circuit when DSP56366 becomes next master. When asserted, DSP56366 must wait until deasserted before taking mastership. When deasserted, mastership typically given current cycle. This occur middle instruction that requires more than external cycle execution. proper operation, asynchronous arbitration enable (ABE) register must set.
Input
Ignored Input
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Signal/Connection Descriptions Interrupt Mode Control Table External Control Signals (continued) Signal Name
Type
State during Reset
Input
Signal Description
Input/Output
Busy-BB bidirectional active-low input/output. indicates that active. Only after deasserted pending master become master (and then assert signal again). master keep asserted after ceasing activity regardless whether asserted deasserted. This called "bus parking" allows current master reuse without rearbitration until another device requires bus. deassertion done "active pull-up" method (i.e., driven high then released held high external pull-up resistor). proper operation, asynchronous arbitration enable (ABE) register must set. requires external pull-up resistor.
INTERRUPT MODE CONTROL
interrupt mode control signals select chip's operating mode comes hardware reset. After RESET deasserted, these inputs hardware interrupt request lines.
Table Interrupt Mode Control Signal Name
MODA/IRQA
Type
State during Reset
Input
Signal Description
Input
Mode Select A/External Interrupt Request A-MODA/IRQA active-low Schmitt-trigger input, internally synchronized clock. MODA/IRQA selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. processor stop standby state MODA/IRQA pulled GND, processor will exit stop state. This input tolerant.
1-10
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Signal/Connection Descriptions Interrupt Mode Control Table Interrupt Mode Control (continued) Signal Name
MODB/IRQB
Type
State during Reset
Input
Signal Description
Input
Mode Select B/External Interrupt Request B-MODB/IRQB active-low Schmitt-trigger input, internally synchronized clock. MODB/IRQB selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. This input tolerant.
MODC/IRQC
Input
Input
Mode Select C/External Interrupt Request C-MODC/IRQC active-low Schmitt-trigger input, internally synchronized clock. MODC/IRQC selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. This input tolerant.
MODD/IRQD
Input
Input
Mode Select D/External Interrupt Request D-MODD/IRQD active-low Schmitt-trigger input, internally synchronized clock. MODD/IRQD selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. This input tolerant.
RESET
Input
Input
Reset-RESET active-low, Schmitt-trigger input. When asserted, chip placed Reset state internal phase generator reset. Schmitt-trigger input allows slowly rising input (such capacitor charging) reset chip reliably. When RESET signal deasserted, initial chip operating mode latched from MODA, MODB, MODC, MODD inputs. RESET signal must asserted during power stable EXTAL signal must supplied while RESET being asserted. This input tolerant.
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Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
PARALLEL HOST INTERFACE (HDI08)
HDI08 provides fast, 8-bit, parallel data port that connected directly host bus. HDI08 supports variety standard buses directly connected number industry standard microcomputers, microprocessors, DSPs, hardware.
Table Host Interface Signal Name
H0-H7
Type
Input/ output
State during Reset
Signal Description
GPIO Host Data-When HDI08 programmed interface disconnected nonmultiplexed host function selected, these signals lines bidirectional, tri-state data bus. GPIO Host Address/Data-When HDI08 programmed disconnected interface multiplexed host function selected, these signals lines address/data bidirectional, multiplexed, tri-state bus. GPIO Port 0-7-When HDI08 configured GPIO, disconnected these signals individually programmable input, output, internally disconnected. default state after reset these signals GPIO disconnected. These inputs tolerant.
HAD0-HAD7
Input/ output
PB0-PB7
Input, output, disconnected
Input
GPIO Host Address Input 0-When HDI08 programmed disconnected interface nonmultiplexed host function selected, this signal line host address input bus. GPIO Host Address Strobe-When HDI08 programmed disconnected interface multiplexed host function selected, this signal host address strobe (HAS) Schmitt-trigger input. polarity address strobe programmable, configured active-low (HAS) following reset. GPIO Port 8-When HDI08 configured GPIO, this disconnected signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
HAS/HAS
Input
Input, output, disconnected
1-12
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Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08) Table Host Interface (continued) Signal Name
Type
Input
State during Reset
Signal Description
GPIO Host Address Input 1-When HDI08 programmed disconnected interface nonmultiplexed host function selected, this signal line host address (HA1) input bus. GPIO Host Address 8-When HDI08 programmed interdisconnected face multiplexed host function selected, this signal line host address (HA8) input bus. GPIO Port 9-When HDI08 configured GPIO, this disconnected signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
Input
Input, output, disconnected
Input
GPIO Host Address Input 2-When HDI08 programmed disconnected interface non-multiplexed host function selected, this signal line host address (HA2) input bus. GPIO Host Address 9-When HDI08 programmed interdisconnected face multiplexed host function selected, this signal line host address (HA9) input bus. GPIO Port 10-When HDI08 configured GPIO, this disconnected signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
Input
PB10
Input, Output, Disconnected
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Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08) Table Host Interface (continued) Signal Name
Type
Input
State during Reset
Signal Description
GPIO Host Read/Write-When HDI08 programmed interdisconnected face single-data-strobe host function selected, this signal Host Read/Write (HRW) input. GPIO Host Read Data-When HDI08 programmed interdisconnected face double-data-strobe host function selected, this signal host read data strobe (HRD) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HRD) after reset. GPIO Port 11-When HDI08 configured GPIO, this disconnected signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
HRD/
Input
PB11
Input, Output, Disconnected
HDS/
Input
GPIO Host Data Strobe-When HDI08 programmed interdisconnected face single-data-strobe host function selected, this signal host data strobe (HDS) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HDS) following reset. GPIO Host Write Data-When HDI08 programmed interdisconnected face double-data-strobe host function selected, this signal host write data strobe (HWR) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HWR) following reset. GPIO Port 12-When HDI08 configured GPIO, this disconnected signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
HWR/
Input
PB12
Input, output, disconnected
1-14
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Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08) Table Host Interface (continued) Signal Name
Type
Input
State during Reset
Signal Description
GPIO Host Chip Select-When HDI08 programmed interdisconnected face nonmultiplexed host function selected, this signal host chip select (HCS) input. polarity chip select programmable, configured active-low (HCS) after reset. GPIO Host Address 10-When HDI08 programmed interdisconnected face multiplexed host function selected, this signal line host address (HA10) input bus. GPIO Port 13-When HDI08 configured GPIO, this disconnected signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
HA10
Input
PB13
Input, output, disconnected
HOREQ/ HOREQ
Output
GPIO Host Request-When HDI08 programmed interface disconnected single host request host function selected, this signal host request (HOREQ) output. polarity host request programmable, configured active-low (HOREQ) following reset. host request programmed driven open-drain output. GPIO Transmit Host Request-When HDI08 programmed disconnected interface double host request host function selected, this signal transmit host request (HTRQ) output. polarity host request programmable, configured active-low (HTRQ) following reset. host request programmed driven open-drain output. GPIO Port 14-When HDI08 configured GPIO, this disconnected signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
HTRQ/ HTRQ
Output
PB14
Input, output, disconnected
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Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08) Table Host Interface (continued) Signal Name
HACK/ HACK
Type
Input
State during Reset
Signal Description
GPIO Host Acknowledge-When HDI08 programmed disconnected interface single host request host function selected, this signal host acknowledge (HACK) Schmitt-trigger input. polarity host acknowledge programmable, configured active-low (HACK) after reset. GPIO Receive Host Request-When HDI08 programmed disconnected interface double host request host function selected, this signal receive host request (HRRQ) output. polarity host request programmable, configured active-low (HRRQ) after reset. host request programmed driven open-drain output. GPIO Port 15-When HDI08 configured GPIO, this disconnected signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
HRRQ/ HRRQ
Output
PB15
Input, output, disconnected
1-16
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Signal/Connection Descriptions Serial Host Interface
SERIAL HOST INTERFACE
Table 1-10 Serial Host Interface Signals
five signals that configured allow operate either mode.
Signal Name
Signal Type
Input output
State during Reset
Tri-stated
Signal Description
Serial Clock-The signal output when configured master Schmitt-trigger input when configured slave. When configured master, signal derived from internal clock generator. When configured slave, signal input, clock signal from external master synchronizes data transfer. signal ignored defined slave slave select (SS) signal asserted. both master slave devices, data shifted edge signal sampled opposite edge where data stable. Edge polarity determined transfer protocol. Serial Clock-SCL carries clock transactions mode. Schmitt-trigger input when configured slave open-drain output when configured master. should connected through pull-up resistor. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
Input output
Tri-stated
MISO
Input output
Tri-stated
Master-In-Slave-Out-When configured master, MISO master data input line. MISO signal used conjunction with MOSI signal transmitting receiving serial data. This signal Schmitt-trigger input when configured Master mode, output when configured Slave mode, tri-stated configured Slave mode when deasserted. external pull-up resistor required operation. Data Acknowledge-In mode, Schmitt-trigger input when receiving open-drain output when transmitting. should connected through pull-up resistor. carries data transactions. data must stable during high period SCL. data only allowed change when low. When free, high. line only allowed change during time high case start stop events. high-to-low transition line while high unique situation, defined start event. low-to-high transition while high unique situation defined stop event. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
Input open-drain output
Tri-stated
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Signal/Connection Descriptions Serial Host Interface Table 1-10 Serial Host Interface Signals (continued) Signal Name
MOSI
Signal Type
Input output
State during Reset
Tri-stated
Signal Description
Master-Out-Slave-In-When configured master, MOSI master data output line. MOSI signal used conjunction with MISO signal transmitting receiving serial data. MOSI slave data input line when configured slave. This signal Schmitt-trigger input when configured Slave mode. Slave Address 0-This signal uses Schmitt-trigger input when configured mode. When configured slave mode, signal used form slave device address. ignored when configured master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
Input
Input
Tri-stated
Slave Select-This signal active Schmitt-trigger input when configured mode. When configured Slave mode, this signal used enable slave transfer. When configured master mode, this signal should kept deasserted (pulled high). asserted while configured master, error condition flagged. deasserted, ignores clocks keeps MISO output signal high-impedance state. Slave Address 2-This signal uses Schmitt-trigger input when configured mode. When configured Slave mode, signal used form slave device address. ignored master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
Input
HREQ
Input Output
Tri-stated
Host Request-This signal active Schmitt-trigger input when configured master mode active output when configured slave mode. When configured slave mode, HREQ asserted indicate that ready next data word transfer deasserted first clock pulse data word transfer. When configured master mode, HREQ input. When asserted external slave device, will trigger start data word transfer master. After finishing data word transfer, master will await next assertion HREQ proceed next transfer. This signal tri-stated during hardware, software, personal reset, when HREQ1-HREQ0 bits HCSR cleared. There need external pull-up this state. This input tolerant.
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Signal/Connection Descriptions Enhanced Serial Audio Interface
ENHANCED SERIAL AUDIO INTERFACE
Table 1-11 Enhanced Serial Audio Interface Signals
Signal Name
HCKR
Signal Type
Input output
State during Reset
GPIO disconnected
Signal Description
High Frequency Clock Receiver-When programmed input, this signal provides high frequency clock source ESAI receiver alternate core clock. When programmed output, this signal serve high-frequency sample clock (e.g., external digital analog converters [DACs]) additional system clock. Port 2-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Input, output, disconnected
GPIO disconnected
HCKT
Input output
GPIO disconnected
High Frequency Clock Transmitter-When programmed input, this signal provides high frequency clock source ESAI transmitter alternate core clock. When programmed output, this signal serve high frequency sample clock (e.g., external DACs) additional system clock. Port 5-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Input, output, disconnected
GPIO disconnected
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Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-11 Enhanced Serial Audio Interface Signals (continued) Signal Name
Signal Type
Input output
State during Reset
GPIO disconnected
Signal Description
Frame Sync Receiver-This receiver frame sync input/output signal. asynchronous mode (SYN=0), operates frame sync input output used enabled receivers. synchronous mode (SYN=1), operates either serial flag (TEBE=0), transmitter external buffer enable control (TEBE=1, RFSD=1). When this configured serial flag pin, direction determined RFSD RCCR register. When configured output flag OF1, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF1, data value will stored SAISR register, synchronized frame sync normal mode slot network mode.
Input, output, disconnected
GPIO disconnected
Port 1-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Input output
GPIO disconnected
Frame Sync Transmitter-This transmitter frame sync input/output signal. synchronous mode, this signal frame sync both transmitters receivers. asynchronous mode, frame sync transmitters only. direction determined transmitter frame sync direction (TFSD) ESAI transmit clock control register (TCCR).
Input, output, disconnected
Port 4-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
1-20
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Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-11 Enhanced Serial Audio Interface Signals (continued) Signal Name
SCKR
Signal Type
Input output
State during Reset
GPIO disconnected
Signal Description
Receiver Serial Clock-SCKR provides receiver serial clock ESAI. SCKR operates clock input output used enabled receivers asynchronous mode (SYN=0), serial flag synchronous mode (SYN=1). When this configured serial flag pin, direction determined RCKD RCCR register. When configured output flag OF0, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF0, data value will stored SAISR register, synchronized frame sync normal mode slot network mode.
Input, output, disconnected
GPIO disconnected
Port 0-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
SCKT
Input output
GPIO disconnected
Transmitter Serial Clock-This signal provides serial rate clock ESAI. SCKT clock input output used enabled transmitters receivers synchronous mode, enabled transmitters asynchronous mode. Port 3-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Serial Data Output 5-When programmed transmitter, SDO5 used transmit data from serial transmit shift register. Serial Data Input 0-When programmed receiver, SDI0 used receive serial data into serial receive shift register. Port 6-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Input, output, disconnected
GPIO disconnected
SDO5
Output
GPIO disconnected GPIO disconnected GPIO disconnected
SDI0
Input Input, output, disconnected
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Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-11 Enhanced Serial Audio Interface Signals (continued) Signal Name
SDO4
Signal Type
Output
State during Reset
GPIO disconnected GPIO disconnected GPIO disconnected
Signal Description
Serial Data Output 4-When programmed transmitter, SDO4 used transmit data from serial transmit shift register. Serial Data Input 1-When programmed receiver, SDI1 used receive serial data into serial receive shift register. Port 7-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
SDI1
Input
Input, output, disconnected
SDO3/S DO3_1
Output
GPIO disconnected
Serial Data Output 3-When programmed transmitter, SDO3 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output
SDI2/ SDI2_1
Input
GPIO disconnected
Serial Data Input 2-When programmed receiver, SDI2 used receive serial data into serial receive shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Input
PC8/PE8
Input, output, disconnected
GPIO disconnected
Port 8-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input tolerant.
1-22
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Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-11 Enhanced Serial Audio Interface Signals (continued) Signal Name
SDO2/ SDO2_1
Signal Type
Output
State during Reset
GPIO disconnected
Signal Description
Serial Data Output 2-When programmed transmitter, SDO2 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output
SDI3/SDI
Input
GPIO disconnected
Serial Data Input 3-When programmed receiver, SDI3 used receive serial data into serial receive shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Input
PC9/PE9
Input, output, disconnected
GPIO disconnected
Port 9-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input tolerant.
SDO1/ SDO1_1
Output
GPIO disconnected
Serial Data Output 1-SDO1 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output
PC10/ PE10
Input, output, disconnected
GPIO disconnected
Port 10-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input tolerant.
SDO0/S DO0_1
Output
GPIO disconnected
Serial Data Output 0-SDO0 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output
PC11/ PE11
Input, output, disconnected
GPIO disconnected
Port 11-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input tolerant.
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Signal/Connection Descriptions Enhanced Serial Audio Interface_1
ENHANCED SERIAL AUDIO INTERFACE_1
Table 1-12 Enhanced Serial Audio Interface_1 Signals Signal State during Signal Type Name Reset
FSR_1 Input output
Signal Description
GPIO Frame Sync Receiver_1-This receiver frame sync disconnected input/output signal. asynchronous mode (SYN=0), operates frame sync input output used enabled receivers. synchronous mode (SYN=1), operates either serial flag (TEBE=0), transmitter external buffer enable control (TEBE=1, RFSD=1). When this configured serial flag pin, direction determined RFSD RCCR register. When configured output flag OF1, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF1, data value will stored SAISR register, synchronized frame sync normal mode slot network mode.
Input, output, disconnected
GPIO Port 1-When ESAI configured GPIO, this signal disconnected individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate
FST_1
Input output
GPIO Frame Sync Transmitter_1-This transmitter frame disconnected sync input/output signal. synchronous mode, this signal frame sync both transmitters receivers. asynchronous mode, frame sync transmitters only. direction determined transmitter frame sync direction (TFSD) ESAI transmit clock control register (TCCR). GPIO Port 4-When ESAI configured GPIO, this signal disconnected individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate
Input, output, disconnected
1-24
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Signal/Connection Descriptions Enhanced Serial Audio Interface_1 Table 1-12 Enhanced Serial Audio Interface_1 Signals Signal State during Signal Type Name Reset
SCKR_1 Input output
Signal Description
GPIO Receiver Serial Clock_1-SCKR provides receiver serial disconnected clock ESAI. SCKR operates clock input output used enabled receivers asynchronous mode (SYN=0), serial flag synchronous mode (SYN=1). When this configured serial flag pin, direction determined RCKD RCCR register. When configured output flag OF0, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF0, data value will stored SAISR register, synchronized frame sync normal mode slot network mode.
Input, output, disconnected
GPIO Port 0-When ESAI configured GPIO, this signal disconnected individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate
SCKT_1 Input output
GPIO Transmitter Serial Clock_1-This signal provides serial disconnected rate clock ESAI. SCKT clock input output used enabled transmitters receivers synchronous mode, enabled transmitters asynchronous mode. GPIO Port 3-When ESAI configured GPIO, this signal disconnected individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate
Input, output, disconnected
SDO5_1
Output
GPIO Serial Data Output 5_1-When programmed transmitter, disconnected SDO5 used transmit data from serial transmit shift register. GPIO Serial Data Input 0_1-When programmed receiver, SDI0 disconnected used receive serial data into serial receive shift register. GPIO Port 6-When ESAI configured GPIO, this signal indidisconnected vidually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate
SDI0_1
Input Input, output, disconnected
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Signal/Connection Descriptions spdif tRANSMITTER Digital Audio Interface Table 1-12 Enhanced Serial Audio Interface_1 Signals Signal State during Signal Type Name Reset
SDO4_1 Output
Signal Description
GPIO Serial Data Output 4_1-When programmed transmitter, disconnected SDO4 used transmit data from serial transmit shift register. GPIO Serial Data Input 1_1-When programmed receiver, disconnected SDI1 used receive serial data into serial receive shift register. GPIO Port 7-When ESAI configured GPIO, this signal disconnected individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
SDI1_1
Input
Input, output, disconnected
1.10
SPDIF TRANSMITTER DIGITAL AUDIO INTERFACE
Table 1-13 Digital Audio Interface (DAX) Signals
Signal Name
Type
Input
State During Reset
Signal Description
GPIO Audio Clock Input-This clock input. When proDisconnected grammed external clock, this input supplies clock. external clock frequency must 256, 384, times audio sampling frequency (256 respectively). GPIO Port 0-When configured GPIO, this signal Disconnected individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Input, output, disconnected
Output
GPIO Digital Audio Data Output-This signal audio Disconnected non-audio output form AES/EBU, CP340 IEC958 data biphase mark format. GPIO Port 1-When configured GPIO, this signal indiDisconnected vidually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Input, output, disconnected
1-26
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Signal/Connection Descriptions Timer
1.11
TIMER
Table 1-14 Timer Signal
Signal Name
TIO0
Type
State during Reset
Input
Signal Description
Input Output
Timer Schmitt-Trigger Input/Output-When timer functions external event counter measurement mode, TIO0 used input. When timer functions watchdog, timer, pulse modulation mode, TIO0 used output. default mode after reset GPIO input. This changed output configured timer input/output through timer control/status register (TCSR0). TIO0 being used, recommended either define GPIO output immediately beginning operation leave defined GPIO input connected through pull-up resistor order ensure stable logic level this input. This input tolerant.
1.12
JTAG/OnCE INTERFACE
Table 1-15 JTAG/OnCE Interface
Signal Name
Signal Type
Input
State during Reset
Input
Signal Description
Test Clock-TCK test clock input signal used synchronize JTAG test logic. internal pull-up resistor. This input tolerant. Test Data Input-TDI test data serial input signal used test instructions data. sampled rising edge internal pull-up resistor. This input tolerant.
Input
Input
Output
Tri-stated Test Data Output-TDO test data serial output signal used test instructions data. tri-statable actively driven shift-IR shift-DR controller states. changes falling edge TCK. Input Test Mode Select-TMS input signal used sequence test controller's state machine. sampled rising edge internal pull-up resistor. This input tolerant.
Input
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SECTION SPECIFICATIONS
INTRODUCTION
DSP56366 high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs outputs. DSP56366 specifications preliminary from design simulations, fully tested guaranteed. Finalized specifications will published after full characterization device qualifications complete.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields. However, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability operation enhanced unused inputs pulled appropriate logic voltage level (e.g., either VCC). suggested value pullup pulldown resistor
Note:
calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification will never occur same device that "minimum" value another specification; adding maximum minimum represents condition that never exist.
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Specifications Thermal Characteristics
Table Maximum Ratings Rating1
Supply Voltage input voltages excluding tolerant" inputs3 tolerant" input voltages3 Current drain excluding
Symbol
VIN5 TSTG
Value1,
Unit
-0.3 +4.0
-0.3 3.95
Operating temperature range Storage temperature
Notes:
+110 +125
0.16 -40°C +110°C, Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond maximum rating affect device reliability cause permanent damage device. CAUTION: Tolerant" input voltages must more than 3.95 greater than supply voltage; this restriction applies "power on", well during normal operation. case, input voltages cannot more than 5.75 Tolerant" inputs inputs that tolerate
THERMAL CHARACTERISTICS
Table Thermal Characteristics Characteristic Symbol
LQFP Value
Unit
Junction-to-ambient thermal resistance1, Natural Convection Junction-to-case thermal resistance3 Thermal characterization parameter4 Natural Convection
Notes:
°C/W °C/W °C/W
Junction temperature function size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, flow, power dissipation other components board, board thermal resistance. SEMI G38-87 JEDEC JESD51-2 with single layer board horizontal. Thermal resistance between case surface measured cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating temperature difference between package junction temperature JEDEC JESD51-2. When Greek letters available, thermal characterization parameter written Psi-JT.
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Specifications Electrical Characteristics
ELECTRICAL CHARACTERISTICS
Table Electrical Characteristics6 Characteristics Symbol
VIHP
3.14
3.46 3.95
Unit
Supply voltage Input high voltage D(0:23), ESAI_1(except SDO4_1) MOD1/IRQ1, RESET, PINIT/NMI SDO4_1)/SHI(SPI mode) SHI(I2C mode) EXTAL8 Input voltage D(0:23), ESAI_1(except SDO4_1) MOD1/IRQ1, RESET, PINIT/NMI SDO4_1)/SHI(SPI mode) SHI(I2C mode) EXTAL8 Input leakage current High impedance (off-state) input current Output high voltage (IOH -0.4
VIHP VIHX VILP
-0.3 -0.3
3.95
VILP VILX ITSI
-0.3 -0.3
0.01
CMOS (IOH µA)5 Output voltage (IOL open-drain pins mA)5,7 CMOS (IOL µA)5 Internal supply current2 internal clock 120MHz Normal mode ICCI
0.01
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Specifications Electrical Characteristics Table Electrical Characteristics6 (continued) Characteristics
Wait mode Stop mode4 supply current Input capacitance5
Notes:
Symbol
ICCW ICCS
Unit
Refers MODA/IRQA, MODB/IRQB, MODC/IRQC,and MODD/IRQD pins Appendix Power Consumption Benchmark provides formula compute estimated current requirements Normal mode. order obtain these results, inputs must terminated (i.e., allowed float). Measurements based synthetic intensive benchmarks. power consumption numbers this specification measured results this benchmark. This reflects typical applications. Typical internal supply current measured with 110°C. Maximum internal supply current measured with 3.46 110°C. Deleted. order obtain these results, inputs, which disconnected Stop mode, must terminated (i.e., allowed float). Periodically sampled 100% tested 40°C +110°C, This characteristic does apply PCAP. Driving EXTAL VIHX high VILX value cause additional power consumption current). minimize power consumption, minimum VIHX should lower than maximum VILX should higher than VCC.
ELECTRICAL CHARACTERISTICS
timing waveforms shown electrical characteristics section tested with maximum minimum pins except EXTAL, which tested using input levels shown Note previous table. timing specifications, which referenced device input signal, measured production with respect point respective input signal's transition. DSP56366 output levels measured with production test machine reference levels respectively. Note: Although minimum value frequency EXTAL MHz, device test conditions rated speed.
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Specifications Internal Clocks
INTERNAL CLOCKS
Table Internal Clocks Expression1, Characteristics Symbol
MF)/ (PDF Ef/2
Internal operation frequency with enabled
Internal operation frequency with disabled Internal clock high period With disabled With enabled With enabled Internal clock period With disabled With enabled With enabled Internal clock cycle time with enabled Internal clock cycle time with disabled Instruction cycle time
Notes:
0.49 DF/MF 0.47 DF/MF
0.51 DF/MF 0.53 DF/MF
0.49 DF/MF 0.47 DF/MF
DF/MF
0.51 DF/MF 0.53 DF/MF
ICYC
Division Factor External frequency External clock cycle Multiplication Factor Predivision Factor internal clock cycle Clock Generation section DSP56300 Family Manual detailed discussion PLL.
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Specifications EXTERNAL CLOCK OPERATION
EXTERNAL CLOCK OPERATION
DSP56366 system clock externally supplied square wave voltage source connected EXTAL (See Figure 2-1). VIHC EXTAL VILC Midpoint
Note:
midpoint (VIHC VILC).
Figure External Clock Timing Table Clock Operation
Characteristics
Frequency EXTAL (EXTAL Frequency) rise fall time this external clock should maximum.
Symbol
120.0
EXTAL input high1, With disabled (46.7%-53.3% duty cycle4) With enabled (42.5%-57.5% duty cycle4) 3.89 3.54 3.89 3.54 8.33 8.33 ICYC 16.66 8.33
157.0 157.0 273.1 8.53
EXTAL input low1, With disabled (46.7%-53.3% duty cycle4) With enabled (42.5%-57.5% duty cycle4)
EXTAL cycle time2 With disabled With enabled
Instruction cycle time ICYC TC32 With disabled With enabled
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Specifications EXTERNAL CLOCK OPERATION Table Clock Operation (continued)
Notes:
Characteristics
Symbol
Measured input transition maximum value enabled given minimum maximum maximum value enabled given minimum maximum indicated duty cycle specified maximum frequency which part rated. minimum clock high time required correct operation, however, remains same lower operating frequencies; therefore, when lower clock frequency used, signal symmetry vary from specified duty cycle long minimum high time time requirements met.
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Specifications Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table Characteristics Characteristics
Unit
frequency when enabled 2/PDF) external capacitor (PCAP VCCP) (CPCAP1)
580) 780) 1470
Notes:
CPCAP value capacitor (connected between PCAP VCCP). recommended value CPCAP computed from following equations: 680)-120, 1100,
RESET, STOP, MODE SELECT, INTERRUPT TIMING
Table Reset, Stop, Mode Select, Interrupt Timing6
Characteristics
Delay from RESET assertion pins reset value3 Required RESET duration4 Power external clock generator, disabled Power external clock generator, enabled During normal operation
Expression
Unit
26.0
1000
416.7
20.8
Delay from asynchronous RESET deassertion first external address output (internal reset deassertion)5 Minimum Maximum Mode select setup time 29.1 3.25 20.25 7.50 30.0 176.2
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Specifications Reset, Stop, Mode Select, Interrupt Timing Table Reset, Stop, Mode Select, Interrupt Timing6 (continued) Characteristics Expression
Unit
Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width
Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory access address valid Caused first interrupt instruction fetch Caused first interrupt instruction execution Delay from IRQA, IRQB, IRQC, IRQD, assertion general-purpose transfer output valid caused first interrupt instruction execution
4.25 7.25
37.4
62.4 88.3
Delay from address output valid caused first 3.75 10.94 interrupt instruction execute interrupt request deassertion level sensitive fast interrupts1 Delay from assertion interrupt request deassertion level sensitive fast interrupts1 Delay from assertion interrupt request deassertion level sensitive fast interrupts1 DRAM SRAM SRAM SRAM Duration IRQA assertion recover from Stop state 3.5) 10.94 3.5) 10.94 10.94 2.5) 10.94 3.25 10.94
Note
Note
Note Note Note Note
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Specifications Reset, Stop, Mode Select, Interrupt Timing Table Reset, Stop, Mode Select, Interrupt Timing6 (continued) Characteristics Expression Unit
Delay from IRQA assertion fetch first instruction (when exiting Stop)2, active during Stop (PCTL (128 Stop delay enabled PLC/2) (OMR active during Stop (PCTL (23.75 Stop delay enabled (OMR 0.5) active during Stop (PCTL (Implies Stop Delay) Duration level sensitive IRQA assertion ensure interrupt service (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (implies Stop delay) Interrupt Requests Rate HDI08, ESAI, ESAI_1, SHI, DAX, Timer IRQ, (edge trigger) (level trigger) Requests Rate Data read from HDI08, ESAI, ESAI_1, SHI, Data write HDI08, ESAI, ESAI_1, SHI, Timer IRQ, (edge trigger) 50.0 12TC 12TC 100.0 66.7 66.7 100.0 (128K PLC/2) (20.5 0.5) (8.25 0.5)
64.6
72.9
45.8
58.0 16.7
25.0
2-10
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Specifications Reset, Stop, Mode Select, Interrupt Timing Table Reset, Stop, Mode Select, Interrupt Timing6 (continued) Characteristics Expression
4.25
37.4
Unit
Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory (DMA source) access address valid
Notes:
When using fast interrupts IRQA, IRQB, IRQC, IRQD defined level-sensitive, timings through apply prevent multiple interrupt service. avoid these timing restrictions, deasserted Edge-triggered mode recommended when using fast interrupts. Long interrupts recommended when using Level-sensitive mode. This timing depends several settings: disable, using external clock (PCTL stabilization delay required recovery time will defined PCTL settings. enable, PCTL shutdown during Stop. Recovering from Stop requires locked. lock procedure duration, Lock Cycles (PLC), range 1000 cycles. This procedure occurs parallel with stop delay counter, stop recovery will when last these events occurs: stop delay counter completes count lock procedure completion. value disable maximum value 4096 (maximum divided desired internal frequency (i.e., 4096/120 34.1 µs). During stabilization period, will constant, their width vary, timing vary well.
Periodically sampled 100% tested RESET duration measured during time which RESET asserted, valid, EXTAL input active valid. When valid, other "required RESET duration" conditions specified above) have been met, device circuitry will uninitialized state that result significant power consumption heat-up. Designs should minimize this state shortest possible duration. does lose lock 0.16 -40°C 110°C, number wait states (measured clock cycles, number TC). expression compute maximum value.
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Specifications Reset, Stop, Mode Select, Interrupt Timing
RESET Pins Reset Value
A0-A17
First Fetch
AA0460
Figure Reset Timing
First Interrupt Instruction Execution/Fetch
A0-A17
IRQA, IRQB, IRQC, IRQD,
First Interrupt Instruction Execution
General Purpose IRQA, IRQB, IRQC, IRQD,
General Purpose
Figure External Fast Interrupt Timing
2-12
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Specifications Reset, Stop, Mode Select, Interrupt Timing
IRQA, IRQB, IRQC, IRQD, IRQA, IRQB, IRQC, IRQD,
AA0463
Figure External Interrupt Timing (Negative Edge-Triggered)
RESET
MODA, MODB, MODC, MODD, PINIT
IRQA, IRQB, IRQD,
AA0465
Figure Operating Mode Select Timing
IRQA
First Instruction Fetch
AA0466
A0-A17
Figure Recovery from Stop State Using IRQA
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Specifications Reset, Stop, Mode Select, Interrupt Timing
IRQA A0-A17
First IRQA Interrupt Instruction Fetch AA0467
Figure Recovery from Stop State Using IRQA Interrupt Service
A0-A17
Source Address
IRQA, IRQB, IRQC, IRQD, First Interrupt Instruction Execution
AA1104
Figure External Memory Access (DMA Source) Timing
2-14
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Specifications External Memory Expansion Port (Port
2.10
2.10.1
EXTERNAL MEMORY EXPANSION PORT (PORT
SRAM Timing
Table SRAM Read Write Accesses3
Characteristics
Symbol
Expression1
Unit
12.0 46.0 87.0 12.7
Address valid assertion pulse width tRC,
Address valid assertion
0.25 1.25
assertion pulse width
frequencies: 0.5)
25.2 16.7
deassertion address valid
0.25 1.25 2.25 frequencies: 1.25 2.25
14.7
Address valid input data valid
tAA,
0.75)
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Specifications External Memory Expansion Port (Port Table SRAM Read Write Accesses3 (continued) Characteristics Symbol
tOHZ 0.75)
Expression1
0.25)
Unit
10.6 16.7 14.7 23.1 10.6 18.9
assertion input data valid deassertion data valid (data hold time) Address valid deassertion2
Data valid deassertion (data setup time) Data hold time from deassertion
(tDW) 0.25) 0.25 1.25 2.25
assertion data active
0.75 0.25 -0.25
deassertion data high impedance
0.25 1.25 2.25
Previous deassertion data active (write)
1.25 2.25 3.25
2-16
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Specifications External Memory Expansion Port (Port Table SRAM Read Write Accesses3 (continued) Characteristics Symbol Expression1
0.75 1.75 2.75
Unit
10.6 18.9 16.8 25.2 16.7
deassertion time
deassertion time
Address valid assertion assertion pulse width deassertion address valid
0.25) -4.0 0.25 1.25 2.25
setup before deassertion4 hold after deassertion
Notes:
0.25
number wait states specified BCR. Timings 100, guaranteed design, tested. timings measured from case negation: timing relative deassertion edge were remain active
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Specifications External Memory Expansion Port (Port
A0-A17 AA0-AA2
D0-D23 Data
AA0468
Figure SRAM Read Access
A0-A17 AA0-AA2 D0-D23 Data
Figure 2-10 SRAM Write Access
2-18
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Specifications External Memory Expansion Port (Port
2.10.2
DRAM Timing
selection guides provided Figure 2-11 Figure 2-14 should used primary selection only. Final selection should based timing provided following tables. example, selection guide suggests that wait states must used operation when using Page Mode DRAM. However, using information appropriate table, designer choose evaluate whether fewer wait states might used determining which timing prevents operation MHz, running chip slightly lower frequency (e.g., MHz), using faster DRAM becomes available), control factors such capacitive resistive load improve overall system performance. DRAM Type (tRAC Note: This figure should primary selection. exact detailed timings following tables.
Chip Frequency (MHz)
Wait States Wait States
Wait States Wait States
AA047
Figure 2-11 DRAM Page Mode Wait States Selection Guide
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Specifications External Memory Expansion Port (Port
Table DRAM Page Mode Timings, Wait State (Low-Power Applications)1, MHz6 Characteristics Symbol Expression
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion deassertion4 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid tASC tCAH 3.25 156.5 4.25 206.5 6.25 306.5 0.75 21.0 21.0 33.5 102.2 135.5 202.1 12.7 12.7 21.0 tCAC tOFF tRSH tRHCP tCAS tCRP 0.75 0.75 1.75 100.0
MHz6 Unit
66.7
1.25
62.5
41.7
33.5 96.0 33.5 81.5
42.5 67.5
21.0 62.7 21.0 52.3
25.8 42.5
2-20
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table DRAM Page Mode Timings, Wait State (Low-Power Applications)1, MHz6 Characteristics Symbol Expression
Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (Write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid assertion data active deassertion data high impedance tRAL tRCS tRCH tWCH tRWL tCWL tWCS tROH 0.75 0.25 0.75 0.25 1.75 1.75 0.25 0.75 96.0 33.7 20.8 70.5 83.2 83.2 33.5 45.7 71.0 37.2
MHz6 Unit
62.7 21.2 12.5 45.5 54.0 54.0 21.0 29.0 46.0 24.7
42.5 12.5
25.8
MOTOROLA
DSP56366
2-21
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Specifications External Memory Expansion Port (Port Table DRAM Page Mode Timings, Wait State (Low-Power Applications)1, MHz6 Characteristics Symbol Expression
Notes:
MHz6 Unit
number wait states Page mode access specified DCR. refresh period specified DCR. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows Page Mode DRAM with Wait state (See Figure 2-14.).
Table 2-10 DRAM Page Mode Timings, Wait States1, Characteristics Symbol Expression
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width tCAC 45.4
Unit
37.5
1.25
41.1
34.4
15.2 30.4
17.9 36.6 14.8
12.3 24.8
tOFF tRSH tRHCP tCAS 1.75 3.25
22.5 45.2 18.7
2-22
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-10 DRAM Page Mode Timings, Wait States1, (continued) Characteristics Symbol Expression
Last deassertion deassertion5 BRW[1:0] BRW[1:0] tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL 1.25 1.75 1.25 2.75 0.25 0.25 1.75 47.2 62.4 92.8 14.9 11.2 22.5 41.5 15.1 18.5 33.5 33.4 33.6 22.5 37.8 50.3 75.3 11.6 17.9 33.5 11.8 14.6 26.8 26.8 27.0 17.9 tCRP 24.4
Unit
19.0
BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write)
MOTOROLA
DSP56366
2-23
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-10 DRAM Page Mode Timings, Wait States1, (continued) Characteristics Symbol Expression
assertion assertion Last assertion deassertion tWCS tROH 1.75 1.75 deassertion data valid6 assertion data active deassertion data high impedance
Notes:
Unit
27.3
19.0
15.4
10.9 33.9
assertion data valid
0.75 0.25
11.1
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM Control Register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. There DRAMs fast enough wait states Page mode 100MHz (See Figure 2-11)
2-24
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
Table 2-11 DRAM Page Mode Timings, Three Wait States1, Characteristics Symbol Expression Unit
1.25 tCAC tOFF tRSH tRHCP tCAS tCRP 40.0 35.0 21.0 41.0 2.25 3.75 16.0 13.0 23.0
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read)
Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write)
4.75 41.5 6.75 61.5 tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL 11.0
21.0 36.0
1.25 0.75
2.25 18.3 30.5 3.75 33.2 3.25 28.2
MOTOROLA
DSP56366
2-25
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-11 DRAM Page Mode Timings, Three Wait States1, (continued) Characteristics Symbol Expression Unit
tWCS tROH 21.0 1.25 31.0 0.75 0.25 18.0
assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6
assertion data active deassertion data high impedance
Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of page-access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ.
2-26
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
Table 2-12 DRAM Page Mode Timings, Four Wait States1, Characteristics Symbol
Expression
Unit
41.7 37.5 15.9 24.2
Page mode cycle time consecutive accesses same direction. Page mode cycle time mixed (read write) accesses assertion data valid (read)
tCAC tOFF tRSH tRHCP tCAS tCRP
2.75 3.75
Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write)
2.75 4.25
25.2 46.0 16.8
5.25 37.7 7.25 54.4 tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL 1.25 1.25 12.7 25.2 37.7
3.25 22.9 33.0
4.75 35.3 3.75 26.9
MOTOROLA
DSP56366
2-27
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-12 DRAM Page Mode Timings, Four Wait States1, (continued) Characteristics Symbol
tWCS tROH 0.75 0.25
Expression
1.25 3.25
Unit
25.2 33.5 20.1
assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6
assertion data active deassertion data high impedance
Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ.
2-28
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
Last Column Address
A0-A17
Column Address
Column Address
D0-D23
Data Data Data AA0473
Figure 2-12 DRAM Page Mode Write Accesses
MOTOROLA
DSP56366
2-29
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
Column Address
Last Column Address
A0-A17
Column Address
D0-D23
Data Data Data AA0474
Figure 2-13 DRAM Page Mode Read Accesses
2-30
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
DRAM Type (tRAC
Note:
This figure should primary selection. exact detailed timings following tables.
Wait States Wait States
Chip Frequency (MHz)
Wait States Wait States
AA0475
Figure 2-14 DRAM Out-of-Page Wait States Selection Guide Table 2-13 DRAM Out-of-Page Refresh Timings, Four Wait States1, MHz4 Characteristics
MHz4 Unit
166.7 54.3
Symbol
Expression
130.0 55.0 67.5
84.2 34.2 42.5
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion
tRAC tCAC tOFF
2.75 1.25
250.0
1.75
83.5
MOTOROLA
DSP56366
2-31
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-13 DRAM Out-of-Page Refresh Timings, Four Wait States1, (continued) MHz4 Characteristics3 Symbol Expression
assertion pulse width assertion deassertion assertion deassertion tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR 3.25 1.75 2.75 1.25 1.25 2.25 1.75 1.75 1.25 0.25 1.75 3.25 0.75 0.25 158.5 83.5 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 83.5 158.5 96.0 71.2 33.8 70.8 145.8 220.5
MHz4 Unit
104.3 54.3 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 54.3 104.3 62.7 46.2 21.3 45.8 95.8 145.5
77.0 64.5
52.0 43.7
assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width
2-32
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-13 DRAM Out-of-Page Refresh Timings, Four Wait States1, (continued) MHz4 Characteristics3 Symbol Expression
assertion deassertion assertion deassertion Data valid assertion (write) tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 0.25 4.75 4.25 2.25 1.75 3.25 1.25 233.2 208.2 108.5 83.5 158.5 145.7 21.0 58.5 221.0 37.2
MHz4 Unit
154.0 137.4 71.0 54.3 104.3 95.7 12.7 37.7 146.0 24.7
192.5 12.5
125.8
assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid3 assertion data active deassertion data high impedance
Notes:
number wait states page access specified DCR. refresh period specified DCR. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows DRAM out-of-page access with four Wait states (See Figure 2-17.).
MOTOROLA
DSP56366
2-33
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
Table 2-14 DRAM Out-of-Page Refresh Timings, Eight Wait States1, Characteristics4 Symbol Expression3
Random read write cycle time assertion data valid (read) tRAC 4.75 4.75 tCAC 2.25 2.25 tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC 3.25 5.75 3.25 4.75 2.25 1.75 4.25 2.75 3.25 1.75 0.75 136.4 45.2 83.1 45.2 68.0 30.1 35.9 24.5 59.8 37.7 45.2 22.5
Unit
64.5 26.6 40.0 39.9 28.5
112.5 36.6 67.9 36.6 55.5 24.1 29.3 19.9 49.1 30.4 36.6 17.9
52.9 21.6 31.0 33.3 23.9
assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion
2-34
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-14 DRAM Out-of-Page Refresh Timings, Eight Wait States1, (continued) Characteristics4 Symbol Expression3
assertion column address valid assertion column address valid tCAH tRAL tRCS tRCH tRRH 3.25 5.75 1.25 0.25 0.25 assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC 8.75 7.75 4.75 3.25 5.75 1.75 45.2 83.1 56.6 26.5 15.2 41.3 79.1 124.3 128.3 113.1 68.0 45.2 83.1 79.0 18.7 22.5
Unit
36.6 67.9 46.0 21.2 11.9 33.3 64.6 101.8 105.1 92.6 55.4 36.6 67.9 64.5 14.8 17.9
Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion
MOTOROLA
DSP56366
2-35
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-14 DRAM Out-of-Page Refresh Timings, Eight Wait States1, (continued) Characteristics4 Symbol Expression3
assertion deassertion assertion data valid tROH 124.8 11.1
Unit
106.1
102.3
87.3
deassertion data valid4 assertion data active deassertion data high impedance
Notes:
0.75 0.25
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table 2-15 DRAM Out-of-Page Refresh Timings, Eleven Wait States1, Characteristics4 Symbol Expression3
tRAC tCAC tOFF tRAS tRSH tCSH tCAS 4.25 7.75 5.25 6.25 3.75 6.25 3.75
120.0 38.5 73.5 48.5 58.5 33.5
Unit
55.5 30.5 38.0
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width
2-36
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-15 DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (continued) Characteristics4 Symbol Expression3
tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH 1.75 5.75 4.25 4.25 1.75 0.75 5.25 7.75 1.75 0.25 11.5
21.0 13.5 53.5 38.5 38.5 13.5 48.5 73.5 56.0 26.0 13.5 45.8 70.8 110.5
29.0 21.5
Unit
assertion assertion assertion column address valid deassertion assertion deassertion pulse width
address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion
11.75 113.2 10.25 103.2 5.75 5.25 7.75 2.75 11.5 53.5 48.5 73.5 60.7 11.0 23.5 111.0
MOTOROLA
DSP56366
2-37
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-15 DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (continued) Characteristics4 Symbol Expression3
0.75 0.25
Unit
93.0
assertion data valid deassertion data valid4 assertion data active deassertion data high impedance
Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table 2-16 DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, Characteristics3 Symbol
tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH
Expression
8.25 4.75 6.25 9.75 6.25 8.25 4.75 2.75 7.75 6.25 6.25 2.75
133.3 48.1 77.2 48.1 64.7 35.6 27.2 20.9 60.6 48.1 48.1 18.9
63.0 33.9 40.1 31.2 24.9
Unit
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid
2-38
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port Table 2-16 DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, (continued) Characteristics3 Symbol
tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 0.25
Expression
0.75 6.25 9.75 1.75 0.25 15.5 15.75 14.25 8.75 6.25 9.75 4.75 15.5
48.1 77.2 54.3 37.9 10.9 45.8 75.0 124.7 126.9 114.4 68.9 48.1 77.2 74.9 35.6 125.2
111.0
Unit
Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion
deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid3 assertion data active deassertion data high impedance
Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
MOTOROLA
DSP56366
2-39
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
A0-A17
Address Column Address
Data AA0476
D0-D23
Figure 2-15 DRAM Out-of-Page Read Access
2-40
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
A0-A17 Address D0-D23 Data
AA0477
Column Address
Figure 2-16 DRAM Out-of-Page Write Access
MOTOROLA
DSP56366
2-41
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
AA0478
Figure 2-17 DRAM Refresh Access
2.10.3
Arbitration Timings
Table 2-17 Asynchronous Arbitration timing
Characteristics
Expression
25.8
Unit
assertion window from input negation. Delay from assertion assertion
21.7
Comments:
register must enter Asynchronous Arbitration mode Asynchronous Arbitration mode active, none timings Table 2-17 required. order guarantee timings 250, 251, recommended assert inputs different 56300 devices same bus) overlap manner shown Figure 2-18.
2-42
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications External Memory Expansion Port (Port
Figure 2-18 Asynchronous Arbitration Timing
250+251
Figure 2-19 Asynchronous Arbitration Timing
Background explanation Asynchronous Arbitration: asynchronous arbitration enabled internal synchronization circuits inputs. These synchronization circuits delay from external signal until exposed internal logic. result this delay, 56300 part assume mastership assert some time after negated. This reason timing 250. Once asserted, there synchronization delay from assertion time this assertion exposed other 56300 components which potential masters same bus. input asserted before that time, situation asserted, negated, cause another 56300 component assume mastership same time. Therefore some non-overlap period between input active another input active required. Timing ensures that such situation avoided.
MOTOROLA
DSP56366
2-43
More Information This Product, www.freescale.com
Specifications Parallel Host Interface (HDI08) Timing
2.11
PARALLEL HOST INTERFACE (HDI08) TIMING
Table 2-18 Host Interface (HDI08) Timing1,
Characteristics
Read data strobe assertion width4 HACK read assertion width
Expression
Unit
18.3
Read data strobe deassertion width4 HACK read deassertion width
Read data strobe deassertion width4 after "Last Data Regis- 27.4 ter" reads5,6, between consecutive CVR, ICR, reads7 HACK deassertion width after "Last Data Register" reads5,6
Write data strobe assertion width8 HACK write assertion width
13.2
Write data strobe deassertion width8 HACK write deassertion width after ICR, "Last Data Register" writes5 after writes, after TXH:TXM writes (with HBE=0), after TXL:TXM writes (with HBE=1)
27.4
16.5
assertion width deassertion data strobe assertion9 Host data input setup time before write data strobe deassertion8 Host data input setup time before HACK write deassertion
Host data input hold time after write data strobe deassertion8 Host data input hold time after HACK write deassertion
Read data strobe assertion output data active from high impedance4 HACK read assertion output data active from high impedance
2-44
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications Parallel Host Interface (HDI08) Timing Table 2-18 Host Interface (HDI08) Timing1, (continued) Characteristics3
Read data strobe assertion output data valid4 HACK read assertion output data valid Read data strobe deassertion output data high impedance4 HACK read deassertion output data high impedance Output data hold time after read data strobe deassertion4 Output data hold time after HACK read deassertion assertion read data strobe deassertion4 assertion write data strobe deassertion8 assertion output data valid hold time after data strobe deassertion9 Address (AD7-AD0) setup time before deassertion (HMUX=1) Address (AD7-AD0) hold time after deassertion (HMUX=1) A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion9 Read Write A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion9 Delay from read data strobe deassertion host request assertion "Last Data Register" read4, Delay from write data strobe deassertion host request assertion "Last Data Register" write5, Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD 0)5, Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD open drain Host Request)5, 16.7 19.1 300.0 +9.9 18.2 19.1
Expression
Unit
24.2
MOTOROLA
DSP56366
2-45
More Information This Product, www.freescale.com
Specifications Parallel Host Interface (HDI08) Timing Table 2-18 Host Interface (HDI08) Timing1, (continued) Characteristics3
Delay from HACK deassertion HOREQ assertion "Last Data Register" read5 "Last Data Register" write5 19.1 35.8 20.2
Expression
Unit
19.1 31.6
other cases Delay from HACK assertion HOREQ deassertion HROD Delay from HACK assertion HOREQ deassertion "Last Data Register" read write HROD open drain Host Request5,
Notes:
300.0
Host Port Usage Considerations DSP56366 User's Manual. timing diagrams below, controls pins drawn active low. polarity programmable. 0.16 -40°C +110°C, read data strobe dual data strobe mode single data strobe mode. "last data register" register address which last location read written data transfers. This timing applicable only read from "last data register" followed read from RXL, RXM, registers without first polling RXDF HREQ bits, waiting assertion HOREQ signal. This timing applicable only consecutive reads from these registers executed. write data strobe dual data strobe mode single data strobe mode. data strobe host read (HRD) host write (HWR) dual data strobe mode host data strobe (HDS) single data strobe mode. host request HOREQ single host request mode HRRQ HTRQ double host request mode. this calculation, host request signal pulled resistor open-drain mode.
2-46
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications Parallel Host Interface (HDI08) Timing
HACK HD7-HD0
HOREQ
AA1105
Figure 2-20 Host Interrupt Vector Register (IVR) Read Timing Diagram
HA0-HA2
HRD, HD0-HD7 HOREQ, HRRQ, HTRQ
AA0484
Figure 2-21 Read Timing Diagram, Non-Multiplexed
MOTOROLA
DSP56366
2-47
More Information This Product, www.freescale.com
Specifications Parallel Host Interface (HDI08) Timing
HA0-HA2
HWR, HD0-HD7 HOREQ, HRRQ, HTRQ
AA0485
Figure 2-22 Write Timing Diagram, Non-Multiplexed
2-48
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10
HRD,
HAD0-HAD7
Address
Data
HOREQ, HRRQ, HTRQ
AA0486
Figure 2-23 Read Timing Diagram, Multiplexed
MOTOROLA
DSP56366
2-49
More Information This Product, www.freescale.com
Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10
HWR, HAD0-HAD7 Address Data HOREQ, HRRQ, HTRQ
AA0487
Figure 2-24 Write Timing Diagram, Multiplexed
HOREQ (Output) HACK (Input) TXH/M/L Write H0-H7 (Input) Data Valid
Figure 2-25 Host Write Timing Diagram
2-50
DSP56366
MOTOROLA
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Specifications Parallel Host Interface (HDI08) Timing
HOREQ (Output)
HACK (Input)
Read
H0-H7 (Output)
Data Valid
Figure 2-26 Host Read Timing Diagram
MOTOROLA
DSP56366
2-51
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Specifications Serial Host Interface Protocol Timing
2.12
SERIAL HOST INTERFACE PROTOCOL TIMING
Table 2-19 Serial Host Interface Protocol Timing
Characteristics1
Tolerable spike width clock data
Mode
Filter Mode
Bypassed Narrow Wide
Expression
126.5 32.8 122.8 209.8 126.5 32.8 122.8 209.8
2000
Unit
Minimum serial clock cycle tSPICC(min)
Master
Bypassed Narrow Wide
Serial clock high period
Master
Bypassed Narrow Wide
Slave
Bypassed Narrow Wide
Serial clock period
Master
Bypassed Narrow Wide
Slave
Bypassed Narrow Wide
Serial clock rise/fall time
Master Slave
2-52
DSP56366
MOTOROLA
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Specifications Serial Host Interface Protocol Timing Table 2-19 Serial Host Interface Protocol Timing (continued)
Characteristics1
assertion first edge CPHA
Mode
Slave
Filter Mode
Bypassed Narrow Wide
Expression
44.2
Unit
CPHA
Slave
Bypassed Narrow Wide
MAX{(20-TC), MAX{(40-TC), TC+5 TC+55 TC+106
11.7 31.7 30.8 50.8 70.8 13.3 63.3 114.3
49.7 139.7 226.7
Last edge asserted
Slave
Bypassed Narrow Wide
Data input valid edge (data input set-up time)
Master/ Slave
Bypassed Narrow Wide
last sampling edge data input valid
Master/ Slave
Bypassed Narrow Wide
assertion data active deassertion data high impedance2 edge data valid (data delay time)
Slave Slave Master/ Slave
Bypassed Narrow Wide
edge data valid (data hold time)
Master/ Slave
Bypassed Narrow Wide
MOTOROLA
DSP56366
2-53
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Specifications Serial Host Interface Protocol Timing Table 2-19 Serial Host Interface Protocol Timing (continued)
Characteristics1
assertion data valid (CPHA First sampling edge HREQ output deassertion
Mode
Slave Slave
Filter Mode
Bypassed Narrow
Expression
TC+33 TC+6 tSPICC
50.8 100.8 156.8 50.8 14.3 111.8 164.8 200.3
41.3 50.8 140.8 237.8
Unit
Wide Last sampling edge HREQ output deasserted (CPHA Slave Bypassed Narrow Wide deassertion HREQ output deasserted (CPHA deassertion pulse width (CPHA HREQ assertion first edge Slave Slave Master Bypassed Narrow Wide HREQ deassertion last sampling edge (HREQ set-up time) (CPHA First edge HREQ asserted (HREQ hold time)
Notes: 3.16 0.16 -40°C +110°C, Periodically sampled, 100% tested
Master
Master
2-54
DSP56366
MOTOROLA
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Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Output) (CPOL (Output) MISO (Input)
Valid
Valid
MOSI (Output) HREQ (Input)
AA0271
Figure 2-27 Master Timing (CPHA
MOTOROLA
DSP56366
2-55
More Information This Product, www.freescale.com
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Output) (CPOL (Output) MISO (Input)
Valid Valid
MOSI (Output) HREQ (Input)
AA0272
Figure 2-28 Master Timing (CPHA
2-56
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Input) (CPOL (Input) MISO (Output) MOSI (Input) HREQ (Output)
AA0273 Valid Valid
Figure 2-29 Slave Timing (CPHA
MOTOROLA
DSP56366
2-57
More Information This Product, www.freescale.com
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Input) (CPOL (Input) MISO (Output) MOSI (Input) HREQ (Output)
AA0274 Valid Valid
Figure 2-30 Slave Timing (CPHA
2-58
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications Serial Host Interface (SHI) Protocol Timing
2.13
SERIAL HOST INTERFACE (SHI) PROTOCOL TIMING
Table 2-20 Protocol Timing Standard Mode4
Tolerable spike width
Characteristics
1,2,3
Symbol/ Expression
Fast Mode5
Unit
Filters bypassed Narrow filters enabled Wide filters enabled clock frequency clock cycle free time Start condition set-up time Start condition hold time period high period rise time fall time Data set-up time Data hold time clock frequency Filters bypassed Narrow filters enabled Wide filters enabled data valid Stop condition set-up time
1000
FSCL TSCL TBUF TSU;STA THD;STA TLOW THIGH TSU;DAT THD;DAT FDSP
10.6 11.8 13.1 TVD;DAT TSU;STO
28.5 39.7 61.0
MOTOROLA
DSP56366
2-59
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Specifications Serial Host Interface (SHI) Protocol Timing Table 2-20 Protocol Timing (continued) Standard Mode4
HREQ deassertion last edge (HREQ set-up time) tSU;RQI
Characteristics
1,2,3
Symbol/ Expression
Fast Mode5
Unit
First sampling edge HREQ output deassertion Filters bypassed Narrow filters enabled Wide filters enabled Last edge HREQ output deasserted Filters bypassed Narrow filters enabled Wide filters enabled HREQ assertion first edge Filters bypassed Narrow filters enabled Wide filters enabled First edge HREQ asserted (HREQ hold time)
Notes:
TNG;RQO TAS;RQO TAS;RQI TI2CCP 46.7 96.7 151.6 46.7 96.7 151.6 46.7 136.7 224.7 46.7 136.7 224.7
4440 4373 4373 1041
tHO;RQI
3.16 0.16 -40°C +110°C Pull-up resistor: (min) kOhm Capacitive load: (max) recommended enable wide filters when operating Standard Mode. recommended enable narrow filters when operating Fast Mode.
2-60
DSP56366
MOTOROLA
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Specifications Serial Host Interface (SHI) Protocol Timing
2.13.1
Programming Serial Clock
programmed serial clock cycle, I2CCP specified value HDM[7:0] bits HCKR (SHI clock control register). expression I2CCP
I2CCP (HDM[7:0] HRS)
where prescaler rate select bit. When cleared, fixed divide-by-eight prescaler operational. When set, prescaler bypassed. HDM[7:0] divider modulus select bits. divide ratio from (HDM[7:0] $FF) selected. mode, user select value programmed serial clock cycle from
HDM[7:0]
4096
HDM[7:0]
programmed serial clock cycle (TI2CCP rise time (TR), filters selected should chosen order achieve desired serial clock cycle (TSCL), shown Table 2-21.
Table 2-21 Serial Clock Cycle (TSCL) generated Master TI2CCP 45ns Narrow filters enabled TI2CCP 135ns Wide filters enabled TI2CCP 223ns
Filters bypassed EXAMPLE: clock frequency (i.e. 8.33ns), operating standard mode environment (FSCL (i.e. TSCL 10µs), 1000ns), with wide filters enabled:
I2CCP 10µs 223ns 1000ns 8756ns
Choosing gives
HDM[7:0] 8756ns 8.33ns 64.67
Thus HDM[7:0] value should programmed (=65). resulting TI2CCP will
I2CCP (HDM[7:0] HRS) I2CCP [8.33ns I2CCP [8.33ns 8796.48ns
MOTOROLA
DSP56366
2-61
More Information This Product, www.freescale.com
Specifications Enhanced Serial Audio Interface Timing
Stop Start
Stop
HREQ
AA0275
Figure 2-31 Timing
2.14
ENHANCED SERIAL AUDIO INTERFACE TIMING
Table 2-22 Enhanced Serial Audio Interface Timing
Characteristics1,
Symbol
tSSICC
Expression
TXC:max[3*tc; t454]
33.3 25.0 27.2
Condition4 Unit
Clock cycle5
Clock high period internal clock external clock Clock period internal clock external clock rising edge (bl) high
10.0
12.5
10.0
12.5
37.0 22.0
2-62
DSP56366
MOTOROLA
More Information This Product, www.freescale.com
Specifications Enhanced Serial Audio Interface Timing Table 2-22 Enhanced Serial Audio Interface Timing (continued) Characteristics1, Symbol
Expression
19.0 23.0 23.0 19.0
37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0
Condition4 Unit
rising edge (bl) rising edge (wr) high6 rising edge (wr) low6
rising edge (wl) high rising edge (wl) Data setup time before (SCK synchronous mode) falling edge Data hold time after falling edge input (bl, high before falling edge input (wl) high before falling edge input hold time after falling edge Flags input setup before falling edge Flags input hold time after falling edge rising edge (bl) high rising edge (bl) rising edge (wr) high6 rising edge (wr) low6
MOTOROLA
DSP56366
2-63
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Specifications Enhanced Serial Audio Interface Timing Table 2-22 Enhanced Serial Audio Interface Timing (continued) Characteristics1, Symbol
Expression
21.0
21.0 21.0 40.0
30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 27.2 21.0 31.0 16.0 34.0 20.0 27.0 31.0 32.0 18.0 27.5 27.5
Condition4 Unit
rising edge (wl) high rising edge (wl) rising edge data enable from high impedance
rising edge transmitter drive enable assertion rising edge data valid rising edge data high impedance7 rising edge transmitter drive enable deassertion7 input (bl, setup time before falling edge6 input (wl) data enable from high impedance input (wl) transmitter drive enable assertion input (wl) setup time before falling edge input hold time after falling edge Flag output valid after rising edge HCKR/HCKT clock cycle HCKT input rising edge output HCKR input rising edge output
2-64
DSP56366
MOTOROLA
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Specifications Enhanced Serial Audio Interface Timing Table 2-22 Enhanced Serial Audio Interface Timing (continued)
Notes:
Characteristics1,
Symbol
Expression
Condition4 Unit
3.16 0.16 -40°C +110°C, internal clock external clock internal clock, asynchronous mode (asynchronous implies that different clocks) internal clock, synchronous mode (synchronous implies that same clock) length word length word length relative TXC(SCKT pin) transmit clock RXC(SCKR pin) receive clock FST(FST pin) transmit frame sync FSR(FSR pin) receive frame sync HCKT(HCKT pin) transmit high frequency clock HCKR(HCKR pin) receive high frequency clock internal clock, external clock cycle defined Icyc ESAI control register. word-relative frame sync signal waveform relative clock operates same manner bit-length frame sync signal waveform, spreads from serial clock before first clock (same length frame sync signal), until before last clock first word frame. Periodically sampled 100% tested
MOTOROLA
DSP56366
2-65
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Specifications Enhanced Serial Audio Interface Timing
(Input/Output
(Bit)
(Word)
First Last
Data
Transmitter Drive Enable
(Bit) (Word)
Note
Flags Note: network mode, output flag transitions occur start each time slot within frame. normal mode, output flag state asserted entire frame period. AA0490
Figure 2-32 ESAI Transmitter Timing
2-66
DSP56366
MOTOROLA
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Specifications Enhanced Serial Audio Interface Timing
(Input/Output) (Bit)
(Word) Data (Bit) (Word) Flags
AA0491
First
Last
Figure 2-33 ESAI Receiver Timing
HCKT
SCKT(output)
Figure 2-34 ESAI HCKT Timing
MOTOROLA
DSP56366
2-67
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Specifications Digital Audio Transmitter Timing
HCKR
SCKR (output)
Figure 2-35 ESAI HCKR Timing
2.15
DIGITAL AUDIO TRANSMITTER TIMING
Table 2-23 Digital Audio Transmitter Timing Characteristic Expression
frequency (see note)
Note:
Unit
12.5
16.7
period high duration duration rising edge valid
order assure proper operation DAX, frequency should less than DSP56366 internal clock frequency. example, DSP56366 running internally, frequency should less than MHz.
AA1280
Figure 2-36 Digital Audio Transmitter Timing
2-68
DSP56366
MOTOROLA
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Specifications Timer Timing
2.16
TIMER TIMING
Table 2-24 Timer Timing Characteristics Expression
High 18.7 18.7
Unit
Note:
0.16 -40°C +110°C,
AA0492
Figure 2-37 Timer Event Input Restrictions
MOTOROLA
DSP56366
2-69
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Specifications GPIO Timing
2.17
GPIO TIMING
Table 2-25 GPIO Timing
Characteristics1
Expression Unit
10.2 6.75 TC-1.8 54.5 32.8
4902 EXTAL edge GPIO valid (GPIO delay time) EXTAL edge GPIO valid (GPIO hold time) GPIO valid EXTAL edge (GPIO set-up time)
EXTAL edge GPIO valid (GPIO hold time) 4942 Fetch EXTAL edge before GPIO change GPIO rise time GPIO fall time
Notes:
0.16 -40°C +110°C, Valid only when enabled with multiplication factor equal one.
EXTAL (Input) GPIO (Output) GPIO (Input) Valid
A0-A17 Fetch instruction MOVE X0,X:(R0); contains value GPIO contains address GPIO data register. GPIO (Output)
Figure 2-38 GPIO Timing
2-70
DSP56366<b
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