400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Int

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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Int

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19-1687; 7/00
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
MAX1284/MAX1285 12-bit analog-to-digital converters (ADCs) combine high-bandwidth track/hold (T/H), serial interface with high conversion speed, internal +2.5V reference, power consumption. MAX1284 operates from single +4.5V +5.5V supply; MAX1285 operates from single +2.7V +3.6V supply. 3-wire serial interface connects directly SPITM/QSPITM/ MICROWIREdevices without external logic. devices external serial-interface clock perform successive-approximation analog-to-digital conversions. power, ease use, small package size make these converters ideal remote-sensor data-acquisition applications other circuits with demanding power consumption space requirements. MAX1284/MAX1285 available 8-pin packages. These devices pin-compatible, higher-speed versions MAX1240/MAX1241; more information, refer respective data sheets.
_Features
Single-Supply Operation +4.5V +5.5V (MAX1284) +2.7V +3.6V (MAX1285) ±1LSB (max) DNL, ±1LSB (max) 400ksps Sampling Rate (MAX1284) Internal Track/Hold Internal +2.5V Reference Power: 2.5mA (400ksps) SPI/QSPI/MICROWIRE 3-Wire Serial Interface Pin-Compatible, High-Speed Upgrades MAX1240/MAX1241 8-Pin Package
MAX1284/MAX1285
Ordering Information
PART MAX1284BCSA MAX1284BESA* MAX1285BCSA MAX1285BESA TEMP. RANGE +70°C -40°C +85°C +70°C -40°C +85°C PINSUPPLY PACKAGE VOLTAGE
_Applications
Portable Data Logging Data Acquisition Medical Instruments Battery-Powered Instruments Digitizers Process Control
*Future product-contact factory availability.
Configuration
VIEW
SCLK DOUT SHDN SCLK CONTROL LOGIC
Functional Diagram
SHDN
MAX1284 MAX1285
CLOCK
OUTPUT SHIFT REGISTER
DOUT
12-BIT
QSPI trademarks Motorola, Inc. MICROWIRE trademark National Semiconductor Corp.
+2.5V REFERENCE
MAX1284 MAX1285
Maxim Integrated Products
free samples latest literature, visit www.maxim-ic.com phone 1-800-998-8800. small orders, phone 1-800-835-8769.
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
ABSOLUTE MAXIMUM RATINGS
.-0.3V GND.-0.3V (VDD 0.3V) .-0.3V (VDD 0.3V) Digital Inputs GND.-0.3V DOUT GND.-0.3V (VDD 0.3V) DOUT Current .±25mA Continuous Power Dissipation +70°C) 8-Pin (derate 5.88mW/°C above +70°C) .471mW Operating Temperature Ranges MAX1284BCSA/MAX1285BCSA .0°C +70°C MAX1284BESA/MAX1285BESA .-40°C +85°C Storage Temperature Range.-60°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS-MAX1284
(VDD +4.5V +5.5V; fSCLK 6.4MHz, duty cycle, clocks/conversion cycle (400ksps); 4.7µF capacitor REF, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error (Note Gain Error Temperature Coefficient DYNAMIC SPECIFICATIONS (100kHz sine wave, 2.5Vp-p, clock 6.4MHz) Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle ANALOG INPUT (AIN) Input Voltage Range Input Capacitance VAIN tSCLK tCONV tACQ SINAD SFDR fIN1 99Hz, fIN2 102Hz -3dB point SINAD 68dB harmonic ±0.8 missing codes over temperature ±1.0 ±1.0 ±6.0 ±6.0 Bits ppm/°C SYMBOL CONDITIONS UNITS
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS-MAX1284 (continued)
(VDD +4.5V +5.5V; fSCLK 6.4MHz, duty cycle, clocks/conversion cycle (400ksps); 4.7µF capacitor REF, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER INTERNAL REFERENCE Output Voltage Short-Circuit Current Output Tempco Load Regulation (Note Capacitive Bypass DIGITAL INPUTS (SCLK, SHDN) Input High Voltage Input Voltage Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUT (DOUT) Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER SUPPLY Positive Supply Voltage (Note Positive Supply Current (Note Shutdown Supply Current Power-Supply Rejection ISHDN 5.5V SCLK VDD, SHDN ±10%, midscale input ±0.5 ±2.0 COUT ISINK ISOURCE VINH VINL VHYST VREF output load VREF +25°C 2.48 2.50 2.52 ppm/°C mV/mA SYMBOL CONDITIONS UNITS
MAX1284/MAX1285
ELECTRICAL CHARACTERISTICS-MAX1285
(VDD +2.7V +3.6V; fSCLK 4.8MHz, duty cycle, clocks/conversion cycle (300ksps); 4.7µF capacitor REF, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER ACCURACY (Note Resolution Relative Accuracy (Note Differential Nonlinearity Offset Error Gain Error (Note Gain Error Temperature Coefficient ±1.6 missing codes over temperature ±1.0 ±1.0 ±6.0 ±6.0 Bits ppm/°C SYMBOL CONDITIONS UNITS
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
ELECTRICAL CHARACTERISTICS-MAX1285 (continued)
(VDD +2.7V +3.0V; fSCLK 4.8MHz, duty cycle, clocks/conversion cycle (300ksps); 4.7µF capacitor REF, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle ANALOG INPUT (AIN) Input Voltage Range Input Capacitance INTERNAL REFERENCE Output Voltage Short-Circuit Current Output Tempco Load Regulation (Note Capacitive Bypass DIGITAL INPUTS (SCLK, SHDN) Input High Voltage VINH Input Voltage VINL Input Hysteresis VHYST Input Leakage Input Capacitance DIGITAL OUTPUTS (DOUT) Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance COUT POWER SUPPLY Positive Supply Voltage (Note Positive Supply Current (Note Shutdown Supply Current ISHDN Power-Supply Rejection VREF VREF 0.75mA output load ISINK ISOURCE 0.5mA 3.6V SCLK VDD, SHDN 2.7V 3.6V, midscale input ±0.5 ±2.0 +25°C 2.48 2.50 2.52 ppm/°C mV/mA mV/mA VAIN fSCLK tCONV tACQ SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (75kHz sine wave, 2.5Vp-p, fSAMPLE 300ksps, fSCLK 4.8MHz) SINAD SFDR fIN1 73kHz, fIN2 77kHz -3dB point SINAD 68dB harmonic
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS-MAX1284 (Figures
(VDD +4.5V +5.5V, TMIN TMAX, unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width Fall SCLK Rise Setup SCLK Rise Rise Hold SCLK Rise Fall Ignore Rise SCLK Rise Ignore SCLK Rise DOUT Hold SCLK Rise DOUT Valid Rise DOUT Disable Fall DOUT Enable Pulse Width High SYMBOL tCSS tCSH tCSO tCS1 tDOH tDOV tDOD tDOE tCSW CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CONDITIONS UNITS
MAX1284/MAX1285
TIMING CHARACTERISTICS-MAX1285 (Figures
(VDD +2.7V +3.6V, TMIN TMAX, unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width Fall SCLK Rise Setup SCLK Rise Rise Hold SCLK Rise Fall Ignore Rise SCLK Rise Ignore SCLK Rise DOUT Hold SCLK Rise DOUT Valid Rise DOUT Disable Fall DOUT Enable Pulse Width High SYMBOL tCSS tCSH tCSO tCS1 tDOH tDOV tDOD tDOE tCSW CLOAD 20pF CLOAD 20pF CLOAD 20pF CLOAD 20pF CONDITIONS UNITS
Note Tested VDD,MIN. Note Relative accuracy deviation analog value code from theoretical value after full-scale range been calibrated. Note Internal reference, offset, reference errors nulled. Note Conversion time defined number clock cycles multiplied clock period; clock duty cycle. Note External load should change during conversion specified accuracy. Guaranteed specification limit 2mV/mA production test limitations. Note Electrical characteristics guaranteed from VDD,MIN VDD,MAX. operations beyond this range, Typical Operating Characteristics. Note MAX1284 tested with 20pF DOUT fSCLK 6.4MHz, MAX1285 tested with same loads, fSCLK 4.8MHz, DOUT full scale.
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
_Typical Operating Characteristics
(MAX1284: +5.0V, fSCLK 6.4MHz; MAX1285: +3.0V, fSCLK 4.8MHz; CLOAD 20pF, 4.7µF capacitor REF, +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY DIGITAL OUTPUT CODE
MAX1284/5 toc01
DIFFERENTIAL NONLINEARITY DIGITAL OUTPUT CODE
(LSB) -0.1
MAX1284/5 toc02
OFFSET ERROR SUPPLY VOLTAGE
MAX1284/5 toc03
(LSB) -0.1 -0.2 -0.3 -0.4 1000 2000 3000 4000
OFFSET ERROR (LSB) -0.5 -1.0
-0.2 -0.3 -0.4 5000 1000 2000 3000 4000 5000 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE
OFFSET ERROR TEMPERATURE
MAX1284/5 toc04
GAIN ERROR SUPPLY VOLTAGE
GAIN ERROR (LSB) -0.2 -0.4 -0.6 -0.8 -1.0 -2.0 -2.5
MAX1284/5 toc05
GAIN ERROR TEMPERATURE
MAX1284/5 toc06
OFFSET ERROR (LSB)
GAIN ERROR (LSB) -0.5 -1.0 -1.5
TEMPERATURE (°C)
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE SUPPLY VOLTAGE
2.508 2.506 REFERENCE VOLTAGE 2.504 2.502 2.500 2.498 2.496 2.494 2.492 2.490 SUPPLY VOLTAGE
MAX1284/5 toc07
INTERNAL REFERENCE VOLTAGE TEMPERATURE
2.508 REFERENCE VOLTAGE 2.506 2.504 2.502 2.500 2.498 2.496 2.494 2.492 2.490 TEMPERATURE (°C)
MAX1284/5 toc08
2.510
2.510
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
Typical Operating Characteristics (continued)
(MAX1284: +5.0V, fSCLK 6.4MHz; MAX1285: +3.0V, fSCLK 4.8MHz; CLOAD 20pF, 4.7µF capacitor REF, +25°C, unless otherwise noted.)
SUPPLY CURRENT SUPPLY VOLTAGE
MAX1284/5 toc09
SUPPLY CURRENT TEMPERATURE
CONVERTING SUPPLY CURRENT (mA)
MAX1284/5 toc10
3.00 2.75 SUPPLY CURRENT (mA) 2.50 2.25 2.00 1.75 1.50
CODE 1111 1111 1111 10pF
CONVERTING SCLK 6.4MHz
CONVERTING
CONVERTING SCLK 4.8MHz
STATIC
STATIC
STATIC
SUPPLY VOLTAGE TEMPERATURE (°C)
Description
NAME SHDN DOUT SCLK Positive Supply Voltage Sampling Analog Input, VREF range Active-Low Shutdown Input. Pulling SHDN shuts down device reduces supply current (typ). Reference Voltage Analog-to-Digital Conversion. Internal 2.5V reference output. Bypass with 4.7µF capacitor. Analog Digital Ground Serial Data Output. DOUT changes state SCLK's rising edge. High impedance when high. Active-Low Chip Select. Initiates conversions falling edge. When high, DOUT high impedance. Serial Clock Input. SCLK drives conversion process clocks data rates 6.4MHz (MAX1284) 4.8MHz (MAX1285). FUNCTION
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
DOUT DGND High-Z High-Z CLOAD 20pF DOUT CLOAD 20pF DGND
Figure Load Circuits DOUT Enable Time
DOUT DGND High-Z High-Z CLOAD 20pF DOUT CLOAD 20pF DGND
Figure Load Circuits DOUT Disable Time
Detailed Description
Converter Operation
MAX1284/MAX1285 input successive-approximation register (SAR) circuitry convert analog input signal digital 12-bit output. Figure shows MAX1284/MAX1285 simplest configuration. internal reference trimmed 2.5V. serial interface requires only three digital lines (SCLK, DOUT) provides easy interface microprocessors (µPs). MAX1284/MAX1285 have modes: normal shutdown. Pulling SHDN shuts device down reduces supply current below (typ), while pulling SHDN high puts device into operational mode. Pulling initiates conversion that driven SCLK. conversion result available DOUT unipolar serial format. serial data stream consists three zeros, followed data bits (MSB first). transitions DOUT occur 20ns after rising edge SCLK. Figures show interface timing information.
Analog Input
Figure illustrates sampling architecture ADC's comparator. full-scale input voltage internal reference (VREF +2.5V). Track/Hold track mode, analog signal acquired stored internal hold capacitor. hold mode, switch opens maintains constant input ADC's section. During acquisition, analog input (AIN) charges capacitor CHOLD. Bringing ends acquisition interval. this instant, switches input side CHOLD GND. retained charge CHOLD represents sample input, unbalancing node ZERO comparator's input. hold mode, capacitive digital-to-analog converter (DAC) adjusts during remainder conversion cycle restore node ZERO within limits 12bit resolution. This action equivalent transferring charge from CHOLD binary-weighted capacitive DAC, which turn forms digital representation analog input signal. conversion's end, input
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
10µF
0.1µF
4.7µF
SCLK
SERIAL INTERFACE
ANALOG INPUT VREF SHUTDOWN INPUT
MAX1284 MAX1285 SHDN DOUT
signal acquired. Acquisition time calculated tACQ 9(RS RIN) 12pF where 800, input signal's source impedance, never less than 468ns (MAX1284) 625ns (MAX1285). Source impedances below significantly affect ADC's performance. Higher source impedances used 0.01µF capacitor connected analog input. Note that input capacitor forms filter with input source impedance, limiting ADC's input signal bandwidth. Input Bandwidth ADCs' input tracking circuitry 6MHz (MAX1284) 3MHz (MAX1285) small-signal bandwidth, possible digitize high-speed transient events measure periodic signals with bandwidths exceeding ADC's sampling rate using undersampling techniques. avoid aliasing unwanted highfrequency signals into frequency band interest, anti-alias filtering recommended. Analog Input Protection Internal protection diodes, which clamp analog input GND, allow input swing from 0.3V 0.3V without damage. analog input exceeds 50mV beyond supplies, limit input current 2mA. Internal Reference MAX1284/MAX1285 have on-chip voltage reference trimmed 2.5V. internal reference output connected also drives internal capacitive DAC. output used reference voltage source other components source 800µA. Bypass with 4.7µF capacitor. Larger capacitors increase wake-up time when exiting shutdown (see Using SHDN Reduce Supply Current section). internal reference disabled shutdown (SHDN
Figure Typical Operating Circuit
CAPACITIVE CHOLD 12pF
ZERO
COMPARATOR
CSWITCH* HOLD
TRACK
AUTOZERO RAIL *INCLUDES INPUT PARASITICS
Figure Equivalent Input Circuit
side HOLD switches back AIN, HOLD charges input signal again. time required acquire input signal function quickly input capacitance charged. input signal's source impedance high, acquisition time lengthens more time must allowed between conversions. acquisition time (tACQ) maximum time device takes acquire signal, also minimum time needed
Serial Interface
Initialization after Power-Up Starting Conversion
When power first applied, SHDN pulled low, takes fully discharged 4.7µF reference bypass capacitor provide adequate charge specified accuracy. conversions should performed during this time.
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
start conversion, pull low. CS's falling edge, enters hold mode conversion initiated. Data then shifted serially with external clock.
Timing Control
Conversion-start data-read operations controlled SCLK digital inputs. timing diagrams Figures outline serial-interface operation. falling edge initiates conversion sequence: stage holds input voltage, begins convert, DOUT changes from high impedance logic low. SCLK used drive conversion process, shifts data each conversion determined. SCLK begins shifting data after rising edge third SCLK pulse. DOUT transitions 20ns after each SCLK rising edge. third rising clock edge produces conversion DOUT, followed remaining bits. Since there data bits three leading zeros, least rising clock edges needed shift these bits. Extra clock pulses occurring after conversion result been clocked out, prior rising edge produce trailing zeros DOUT have effect converter operation. Pull high after reading conversion's LSB. maximum throughout, pulled again initiate next conversion immediately after specified minimum time (tCS).
Using SHDN Reduce Supply Current
Power consumption reduced significantly shutting down MAX1284/MAX1285 between conversions. Figure shows plot average supply current versus conversion rate. wake-up time (tWAKE) time from when SHDN deasserted time when conversion initiated (Figure This time depends time shutdown (Figure because external 4.7µF reference bypass capacitor loses charge slowly during shutdown long 2ms.
3.0V DOUT 10pF
SUPPLY CURRENT (µA)
Output Coding Transfer Function
100k
CONVERSION RATE (sps)
Figure Supply Current Conversion Rate
data output from MAX1284/MAX1285 binary, Figure depicts nominal transfer function. Code transitions occur halfway between successiveinteger value VREF 2.5V, 1LSB 610µV 2.5V/4096.
COMPLETE CONVERSION SEQUENCE tWAKE SHDN
DOUT CONVERSION POWERED POWERED DOWN CONVERSION POWERED
Figure Shutdown Sequence
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
1.50 REFERENCE POWER-UP DELAY (ms) CREF 4.7µF 1.25 1.00 0.75 0.50 0.25 0.0001
Applications Information
Connection Standard Interfaces
MAX1284/MAX1285 serial interface fully compatible with SPI/QSPI MICROWIRE (Figure 11). serial interface available, CPU's serial interface master mode generates serial clock. Choose clock frequency 6.4MHz (MAX1284) 4.8MHz (MAX1285). general-purpose line pull low. Keep SCLK low. Activate SCLK minimum clock cycles. first clocks produce zeros DOUT. DOUT output data transitions 20ns after third SCLK rising edge available MSB-first format. Observe
MAX1284/MAX1285
0.001
0.01
TIME SHUTDOWN
Figure Reference Power-Up Time Shutdown
SCLK DOUT HIGH-Z HIGH-Z
STATE
HOLD/CONVERT
ACQUISITION
Figure Interface Timing Sequence
tCSW ttCSO tCSS tCSH tCSI
SCLK tDOH tDOE DOUT tDOV tDOD
Figure Detailed Serial-Interface Timing
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
OUTPUT CODE 11.111 11.110 11.101 FULL-SCALE TRANSITION MISO SCLK DOUT
VREF 1LSB 1LSB VREF 4096 00.011 00.010 00.001 00.000 INPUT VOLTAGE (LSBs) 3/2LSB
MAX1284 MAX1285
MISO
SCLK DOUT
QSPI
MAX1284 MAX1285
Figure Unipolar Transfer Function, Full Scale (FS) VREF 1LSB, Zero Scale (ZS)
SCLK DOUT
SCLK DOUT valid timing characteristic. Data clocked into SCLK rising edge. Pull high after 15th rising clock edge. remains low, trailing zeros clocked after LSB. With high, wait minimum specified time, tCS, before initiating conversion pulling low. conversion aborted pulling high before conversion completes, wait minimum acquisition time, tACQ, before starting conversion. must held until data bits clocked out. Data output bytes continuously, shown Figure bytes contain result conversion padded with three leading zeros three trailing zeros.
MAX1284 MAX1285
MICROWIRE
Figure Common Serial-Interface Connections MAX1284/MAX1285
QSPI
Unlike SPI, which requires 1-byte reads acquire bits data from ADC, QSPI allows minimum number clock cycles necessary clock data. MAX1284/MAX1285 require clock cycles from clock bits data. Figure shows transfer using CPOL CPHA conversion result contains zeros followed bits data MSB-first formatted.
MICROWIRE
When using MICROWIRE, CPOL CPHA Conversion begins with falling edge. DOUT goes low, indicating conversion progress. consecutive 1-byte reads required full bits from ADC. DOUT output data transitions SCLK's rising edge clocked into following rising edge. first byte contains three leading zeros, bits conversion result. second byte contains remaining bits trailing zero. Figure connections Figure timing.
Layout, Grounding, Bypassing
best performance, boards. Wire-wrap boards recommended. Board layout should ensure that digital analog signal lines separated from each other. analog digital (especially clock) lines parallel another, digital lines underneath package.
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
Figure shows recommended system ground connections. Establish single-point analog ground ("star" ground point) GND, separate from logic ground. Connect other analog grounds DGND this star ground point further noise reduction. other digital system ground should connected this single-point analog ground. ground return power supply this ground should impedance short possible noise-free operation. High-frequency noise power supply affect ADC's high-speed comparator. Bypass this supply single-point analog ground with 0.1µF 10µF bypass capacitors. Minimize capacitor lead lengths best supply noise rejection. reduce effects supply noise, resistor connected lowpass filter attenuate supply noise (Figure 14).
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) deviation values actual transfer function from straight line. This straight line either best-straight-line line drawn between endpoints transfer function, once offset gain errors have been nullified. static linearity parameters MAX1284/MAX1285 measured using endpoints method.
Differential Nonlinearity
Differential nonlinearity (DNL) difference between actual step width ideal value 1LSB. error specification 1LSB less guarantees missing codes monotonic transfer function.
SCLK
DOUT
HIGH-Z
HIGH-Z
FIRST BYTE READ
SECOND BYTE READ
Figure SPI/MICROWIRE Serial Interface Timing (CPOL CPHA
SCLK
HIGH-Z DOUT
HIGH-Z
Figure QSPI Serial Interface Timing (CPOL CPHA
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) ratio fundamental input frequency's amplitude equivalent other output signals.
SUPPLIES
SINAD (dB) (SignalRMS/NoiseRMS)
Effective Number Bits
Effective number bits (ENOB) indicates global accuracy specific input frequency sampling rate. ideal ADC's error consists quantization noise only. With input range equal full-scale range ADC, calculate effective number bits follows:
4.7µF
0.1µF DGND
ENOB (SINAD 1.76) 6.02
MAX1284 MAX1285
*OPTIONAL
DIGITAL CIRCUITRY
Total Harmonic Distortion
Total harmonic distortion (THD) ratio first five harmonics input signal fundamental itself. This expressed
Figure Power-Supply Grounding Condition
Aperture Jitter
Aperture jitter (tAJ) sample-to-sample variation time between samples.
Aperture Delay
Aperture delay (tAD) time defined between falling edge instant when actual sample taken.
where fundamental amplitude, through amplitudes through 5th-order harmonics.
Signal-to-Noise Ratio
waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) ratio full-scale analog input (RMS value) quantization error (residual error). theoretical minimum analog-to-digital noise caused quantization error, results directly from ADC's resolution, bits): (6.02 1.76)dB reality, there other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, computed taking ratio signal noise, which includes spectral components minus fundamental, first five harmonics, offset.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) ratio amplitude fundamental (maximum signal component) value next-largest distortion component.
_Chip Information
TRANSISTOR COUNT: 4286 PROCESS: BiCMOS
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
_Package Information
SOICN.EPS
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
NOTES
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2000 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Int

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