SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER Fully integrated singl

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SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER Fully integrated singl

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ICS87950I
SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER
Fully integrated single ended 3.3V LVCMOS/LVTTL outputs Selectable single ended crystal inputs Maximum output frequency: 250MHz Maximum range: 240MHz 500MHz Cycle-to-cycle jitter: ±100 (typical) Output skew: 375ps (maximum) outputs same frequency 3.3V operating supply -40°C 85°C ambient operating temperature
VDDO VDDO
VDDO
GENERAL DESCRIPTION
ICS87950I voltage, skew LVCMOS/LVTTL Clock Generator memHiPerClockSber HiPerClockSfamily High Performance Clock Solutions from ICS. With output frequencies 250MHz ICS87950I targeted high performance clock applications. Along with fully integrated ICS87950I contains frequency configurable outputs.
ASSIGNMENT
CLK_SEL
VDDA FBDIV_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD XTAL1
XTAL2 MR/nOE VDDO VDDO
32-Lead LQFP 1.4mm package body package View
PLL_SEL
ICS87950I
DIV_SELA Pulldown Pulldown PLL_SEL Pulldown Pulldown CLK_SEL XTAL1 XTAL2 PHASE DETECTOR 240-500MHz
FBDIV_SEL Pulldown DIV_SELB Pulldown
DIV_SELC Pulldown MR/nOE Pulldown Power-On Reset DIV_SELD Pulldown
compatible with MPC950
BLOCK DIAGRAM
÷8/÷16
87950BYI
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ICS87950I
SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER
Type Power Input Input Input Input Input Power Input Input Pulldown Pulldown Pulldown Pulldown Pulldown Description Analog supply pin. Selects divide value Bank feedback output described Table LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects divide value Bank outputs described Table LVCMOS LVTTL interface levels. Selects divide value Bank outputs described Table LVCMOS LVTTL interface levels. Power supply ground. ystal oscillator interface. XTAL1 input, XTAL2 output. Active High Master Reset. Active Output Enable. When logic HIGH, internal dividers reset outputs tri-stated Pulldown (HiZ). When logic LOW, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Output supply pins. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Bank clock output. typical output impedance. LVCMOS LVTTL interface levels. Bank clock output. typical output impedance. LVCMOS LVTTL interface levels. Pulldown LVCMOS LVTTL phase detector reference clock input. Selects between reference clock input Pulldown dividers. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS LVTTL interface levels. Clock select input. When HIGH, selects CLK. When LOW, Pulldown selects XTAL1, XTAL LVCMOS LVTTL interface levels.
TABLE DESCRIPTIONS
Number Name VDDA FBDIV_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD XTAL1, XTAL2 MR/nOE
VDDO QD4, QD3, QD2, QD1, QC1, PLL_SEL CLK_SEL
Power Output Output Output Output Input Input Input
NOTE: Pulldown refers internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pulldown Resistor Output Impedance VDDA, VDDO 3.47V Test Conditions Minimum Typical Maximum Units
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ICS87950I
SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER
Outputs
TABLE OUTPUT CONTROL FUNCTION TABLE
Inputs MR/nOE Enabled Enabled QC0, Enabled QD0:QD4 Enabled
TABLE OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL Operating Mode Bypass
TABLE INPUT FUNCTION TABLE
Inputs CLK_SEL Input XTAL Oscillator
TABLE PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE
Inputs FBDIV_SEL Function
FBDIV_SEL
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ICS87950I
SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER
Outputs DIV_SELD VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8
TABLE PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE
Inputs DIV_SELA DIV_SELB DIV_SELC
TABLE INPUT REFERENCE
OUTPUT FREQUENCY RELATIONSHIP
Outputs DIV_SELD FBDIV_SEL FBDIV_SEL
Inputs DIV_SELA DIV_SELB DIV_SELC
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ICS87950I
SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER
4.6V -0.5V VDDA -0.5V VDDO 0.5V 42.1°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA IDDO Parameter Analog Supply Voltage Output Supply Voltage Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage Input Current Output High Voltage; NOTE Output Voltage; NOTE =VIN 3.465V Test Conditions Minimum -0.3 Typical Maximum ±120 Units
NOTE Outputs terminated with VDDO/2.
TABLE CRYSTAL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Test Conditions Minimum Typical Maximum Units Fundamental
TABLE INPUT REFERENCE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units fREF Input Reference Frequency; NOTE 62.5 NOTE Maximum minimum input reference limited lock range feedback divider input.
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SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER
Test Conditions fMAX 150MHz fMAX 150MHz ±100 0.8V tPERIOD/2 1000 tPERIOD/2 1000 Minimum Typical Maximum 62.5 Units
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol fMAX fVCO Parameter Output Frequency Lock Range Same Frequency Output Skew; NOTE Different Frequency Cycle-to-Cycle Jitter; NOTE Lock Time; NOTE Output Rise/Fall Time Output Pulse Width; NOTE Output Enable Time
tsk(o) tjit(cc)
tPZL, tPZH
tPLZ,, tPHZ Output Disable Time parameters measured fMAX unless noted otherwise. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDO/2. NOTE Jitter performance using Xtal inputs. NOTE Measured using CLK. NOTE This parameter defined accordance with JEDEC Standard
87950BYI
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ICS87950I
SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
VDDA, VDDO
SCOPE
LVCMOS
sk(o)
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
OUTPUT SKEW
VDDO
VDDO PERIOD
VDDO
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
0.8V
Clock Outputs
OUTPUT RISE/FALL TIME
87950BYI
QCx,
tcycle
QCx,
PERIOD
OUTPUT PULSE WIDTH/PERIOD
0.8V
REV. APRIL 2004
ICS87950I
SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87950I provides separate power supplies isolate high switching noise from outputs internal PLL. VDDO VDDA should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA pin.
3.3V VDDO .01µF
VDDA .01µF 10µF
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
ICS87950I been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF parallel resonant crystal were chosen minimize error. These same capacitor values will tune 18pF parallel resonant crystal over frequency range other parameters specified this data sheet. optimum values slightly adjusted different board layouts.
XTAL_IN
18pF Parallel stal
XTAL_OUT
ICS84332
Figure CRYSTAL INPUt INTERFACE
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ICS87950I
SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87950I 2674
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SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER
LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
87950BYI
REV. APRIL 2004
ICS87950I
SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER
Marking ICS87950BYI ICS87950BYI Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87950BYI ICS87950BYIT
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87950BYI
REV. APRIL 2004

SKEW, 1-TO-9 LVCMOS LVTTL CLOCK MULTIPLIER Fully integrated singl

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