SST31LH103 FEATURES: Organized Flash SRAM Single 3.0-3.6V Read Wr
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Megabit Flash Kilobit SRAM ComboMemory
SST31LH103
FEATURES: Organized Flash SRAM Single 3.0-3.6V Read Write Operations (2.7-3.6V without concurrent operation) Concurrent Operation Read from write SRAM while erase/ program Flash Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Flash SRAM Read Standby Current: (typical) Sector Erase Capability Uniform KWord sectors Fast Read Access Times: Flash: SRAM: PRODUCT DESCRIPTION SST31LH103 ComboMemory device integrates CMOS flash memory bank with CMOS SRAM memory bank monolithic silicon, manufactured with SST's proprietary, high performance SuperFlash technology. SST31LH103 device writes (SRAM programs erases flash) with 3.0-3.6V power supply. monolithic SST31LH103 device conforms JEDEC standard Software Data Protect (SDP) commands. Featuring high performance word program, flash memory bank provides maximum word program time µsec. entire flash memory bank erased programmed word-by-word typically seconds, when using interface features such Toggle Data# Polling indicate completion Program operation. protect against inadvertent flash write, SST31LH103 device on-chip hardware software data protection schemes. Designed, manufactured, tested wide spectrum applications, SST31LH103 device offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST31LH103 operates independent memory banks with respective bank enable signals. SRAM Flash memory banks superimposed same memory address space. Both memory banks share common address lines, data lines, OE#. memory bank selection done memory bank enable signals. SRAM bank enable signal, BES# selects
1999 Silicon Storage Technology, Inc. 355-06 5/99
Latched Address Data Flash Flash Fast Sector Erase Word Program: Sector Erase Time: typical Bank Erase Time: typical Word Program Time: typical Bank Rewrite Time: seconds typical Flash Automatic Erase Program Timing Internal Generation Flash Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Command Packages Available 40-Pin TSOP (10mm 14mm)
SRAM bank flash memory bank enable signal, BEF# selects flash memory bank. signal used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. command sequence protects data stored flash memory bank from accidental alteration. SST31LH103 provides added functionality being able simultaneously read from write SRAM bank while erasing programming flash memory bank. SRAM memory bank read written while flash memory bank performs Sector Erase, Bank Erase, Word Program concurrently. flash memory Erase Program operations will automatically latch input address data signals complete operation background without further input stimulus requirement. Once internally controlled erase program cycle flash bank commenced, SRAM bank accessed read write. SST31LH103 device suited applications that both nonvolatile flash memory volatile SRAM memory store code data. system applications, SST31LH103 device significantly improves performance reliability, while lowering power consumption, when compared with multiple chip solutions. SST31LH103 inherently uses less energy during erase program than alternative flash technologies. total energy consumed function applied voltage, current, time application. Since
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. monolithic ComboMemory eliminates redundant functions when using separate memories similar architecture; therefore, reducing total power consumption. SuperFlash technology provides fixed Erase Program times, independent number Erase/ Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST31LH103 device also improves flexibility using single package common signals perform functions previously requiring separate devices. meet high density, surface mount requirements, SST31LH103 device offered 40-pin TSOP package. Figure pinout. Device Operation ComboMemory uses BES# BEF# control operation either SRAM flash memory bank. contention eliminated monolithic device will recognize both bank enables being simultaneously active. both bank enables asserted (i.e., BEF# BES# both low), BEF# will dominate while BES# ignored appropriate operation will executed flash memory bank. does recommend that both bank enables simultaneously asserted. other address, data, control lines shared; which minimizes power consumption area. device goes into standby when both bank enables raised VIHC. SRAM Operation With BES# BEF# high, SST31LH103 operates CMOS SRAM, with fully static operation requiring external clocks timing strobes. SRAM mapped into first KWord address space device. Read Write cycle times equal. SRAM Read SRAM Read operation SST31LH103 controlled BES#, both have with high system obtain data from outputs. BES# used SRAM bank selection. When BES# BEF# high, both memory banks deselected. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details. SRAM Write SRAM Write operation SST31LH103 controlled BES#, both have must high system write SRAM. BES# used SRAM bank selection. During Word Write operation, addresses data referenced rising edge either BES# WE#, whichever occurs first. write time measured from last falling edge first rising edge BES# WE#. Refer Write cycle timing diagram, Figure further details. Flash Operation With BEF# active, SST31LH103 operates flash memory. flash memory bank read using common address lines, data lines, OE#. Erase Program operations initiated with JEDEC standard command sequences. Address data latched during commands during internally timed Erase Program operations. Flash Read Read operation SST31LH103 device controlled BEF# OE#, both have low, with high, system obtain data from outputs. BEF# used flash memory bank selection. When BEF# BES# high, both banks deselected only standby power consumed. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram (Figure further details. Flash Erase/Program Operation commands used initiate flash memory bank Program Erase operations SST31LH103. commands loaded flash memory bank using standard microprocessor write sequences. command loaded asserting while keeping BEF# high. address latched falling edge BEF#, whichever occurs last. data latched rising edge BEF#, whichever occurs first.
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information Flash Word Program Operation flash memory bank SST31LH103 device programmed word-by-word basis. Program operation consists three steps. first step three-word-load sequence Software Data Protection. second step load word address word data. During Word Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed, within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid Flash Read operations Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands loaded during internal Program operation will ignored. Flash Sector Erase Operation Sector Erase operation allows system erase flash memory bank sector sector basis. sector architecture based uniform sector size KWords. Sector Erase operation initiated executing six-word-command load sequence software data protection with sector erase command (0030H) sector address (SA) last cycle. address lines A12-A16 will used determine sector address. sector address latched falling edge sixth pulse, while command (0030H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands loaded during Sector Erase operation will ignored. Flash Bank Erase Operation SST31LH103 flash memory bank provides Bank Erase operation, which allows user erase entire flash memory bank array "1's" state. This useful when entire bank must quickly erased. Bank Erase operation initiated executing six-word software data protection command sequence with Bank Erase command (0010H) with address 5555H last word sequence. internal Erase operation begins with rising edge sixth BEF# pulse, whichever occurs first. During internal Erase operation, only valid Flash Read operations Toggle Data# Polling. Table command 1999 Silicon Storage Technology, Inc.
quence, Figure timing diagram, Figure flowchart. commands loaded during Bank Erase operation will ignored. Flash Write Operation Status Detection SST31LH103 flash memory bank provides software means detect completion flash memory bank Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes four status bits: Data# Polling (DQ7) Toggle (DQ6). write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Flash Data# Polling (DQ7) When SST31LH103 flash memory bank internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. flash memory bank then ready next operation. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth BEF#) pulse Program operation. Sector Bank Erase, Data# Polling valid after rising edge sixth BEF#) pulse. Figure Data# Polling timing diagram Figure flowchart. Flash Toggle (DQ6) During internal Program Erase operation, consecutive attempts read will produce alternating 1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. flash memory bank then ready next operation. Toggle valid after rising edge fourth BE#) pulse Program operation. Sector Bank Erase, Toggle valid after rising edge sixth BEF#) pulse. Figure Toggle timing diagram Figure flowchart.
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information Flash Memory Data Protection SST31LH103 flash memory bank provides both hardware software features protect nonvolatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: BEF# pulse less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Flash Write operation. This prevents inadvertent writes during power-up power-down. Flash Software Data Protection (SDP) SST31LH103 provides JEDEC approved software data protection scheme flash memory bank data alteration operations, i.e., Program Erase. Program operation requires inclusion series three-word sequence. three word-load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-word load sequence. SST31LH103 device shipped with software data protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device read mode, within Read Cycle Time (TRC). Concurrent Read Write Operations SST31LH103 provides unique benefit being able read from write SRAM, while simultaneously erasing programming Flash. This allows data alteration code executed from SRAM, while altering data Flash. following table lists valid states. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase SRAM Read Write Product Identification product identification mode identifies device SST31LH103 manufacturer SST. This mode accessed hardware software operations. hardware device read operation typically used programmer identify correct algorithm SST31LH103 flash memory bank. Users wish software product identification operation identify part (i.e., using device code) when using multiple manufacturers same socket. details, Table hardware operation Table software operation, Figure software entry read timing diagram Figure entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION TABLE Address Manufacturer's Code Device Code 0000H 0001H Data 00BF 0119
T1.2
Product Identification Mode Exit/Reset order return standard read mode, Software Product Identification mode must exited. Exiting accomplished issuing Exit command sequence, which returns device Read operation. Please note that software-reset command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart. Design Considerations recommends high frequency ceramic capacitor placed close possible between VSS, e.g., less than away from device. Additionally, frequency electrolytic capacitor from should placed within pin.
device will ignore commands when Erase Program operation progress. Note that Product Identification commands SDP; therefore, these commands will also ignored while Erase Program operation progress.
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information FUNCTIONAL BLOCK DIAGRAM SST31LH103
Address Buffers SRAM Cell Array
BES# BEF#
Control Logic
Buffers
DQ15
Address Buffers Latches
Flash Cell Array
B1.3
BES# BEF# DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
Standard Pinout View
F01.0-P2
FIGURE ASSIGNMENTS 40-PIN TSOP PACKAGE (10mm 14mm) TABLE DESCRIPTION Symbol Name A15-A0 Address Inputs
DQ15-DQ0 Data Input/output
BES# BEF#
SRAM Memory Bank Enable Flash Memory Bank Enable Output Enable Write Enable Power Supply Ground
Functions provide memory addresses. During Flash Sector Erase A18-A12 address lines will select sector. A15-A0 provide flash address, A13-A0 provide SRAM addresses. output data during read cycles receive input data during write cycles. Data internally latched during Flash Erase/Program cycle. outputs tri-state when BES# BEF# high. activate SRAM memory bank when BES# low. activate Flash memory bank when BEF# low. gate data output buffers. control write operations. provide 3.0-3.6V supply (2.7-3.6V concurrent operation)
T2.2
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information TABLE OPERATION MODES SELECTION Mode BES# BEF# Flash Read Flash Program Flash Erase SRAM Read SRAM Write Standby Flash Write Inhibit VIHC VIHC DOUT DOUT High High Z/DOUT High Z/DOUT High Z/DOUT Address Sector address, Bank Erase
Product Identification Hardware Mode Software Mode
Manufacturer VIL, Code (00BF) Device Code (0119) VIL, Code Table
T3.2
TABLE SOFTWARE COMMAND SEQUENCE FLASH MEMORY BANK
Command Sequence Word Program Sector Erase Bank Erase Software Entry Software Exit
Notes: Address format A14-A0 (Hex), Addresses "Don't Care" Command sequence. Sector Erase; uses A15-A12 address lines Program Word address Notes Software Entry Command Sequence With Manufacturer Code BFH, read with 31LH103 Device Code 0119H, read with device does remain Software Product Mode powered down.
Write Cycle Addr(1) Data 5555H 00AAH 5555H 00AAH 5555H 00AAH 5555H 00AAH 5555H 00AAH
Write Cycle Write Cycle Addr(1) Data Addr(1) Data 2AAAH 0055H 5555H 00A0H 2AAAH 0055H 5555H 0080H 2AAAH 0055H 5555H 0080H 2AAAH 0055H 5555H 0090H 2AAAH 0055H 5555H 00F0H
Write Cycle Addr(1) Data BA(3) Data 5555H 00AAH 5555H 00AAH
Write Cycle Addr(1) Data 2AAAH 0055H 2AAAH 0055H
Write Cycle Addr(1) Data SAx(2) 0030H 5555H 0010H
T4.0
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VDD+ 1.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1)
Note: Outputs shorted more than second. more than output shorted time.
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information OPERATING RANGE Range Ambient Temp Commercial Industrial CONDITIONS TEST 3.0-3.6V 3.0-3.6V Input Rise/Fall Time Output Load Figures
TABLE OPERATING CHARACTERISTICS 3.0-3.6V Limits Symbol Parameter Power Supply Current Read Flash SRAM Concurrent Operation Write Flash SRAM Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage 0.7VDD Input High Voltage (CMOS) VDD-0.3 Output Voltage Output High Voltage VDD-0.2 Supervoltage 11.4 Supervoltage Current
Units
Test Conditions Max, open, Address input VIL/VIH, f=1/TRC Min. VIL, BEF# VIL, BES# BEF# VIH, BES# BEF# VIH, BES# VIH, BEF# VIL, BES# BEF# VIH, BES# Max. BEF# BES# VIHC =GND VDD, Max. VOUT =GND VDD, Max. Min. Max. Max. Min. -100µA, Min. BEF# =VIL, BEF# VIL, VIH, Max.
T5.2
T6.0
VIHC
12.6
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ TPU-WRITE(1)
Minimum
Units
Power-up Read Operation Power-up Write Operation
TABLE CAPACITANCE Mhz, other pins open) Parameter Description Test Condition CI/O CIN(1)
Maximum
T7.0
Capacitance Input Capacitance
VI/O
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information TABLE RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification NEND TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1)
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T8.0
Endurance Data Retention Susceptibility Human Body Model Susceptibility Machine Model Latch
10,000 2000
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM MEMORY BANK READ CYCLE TIMING PARAMETERS 3.0-3.6V SST31LH103-15 Symbol Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time TBLZ BES# Active Output TOLZ Output Enable Active Output TBHZ(1) BES# High-Z Output TOHZ Output Disable High-Z Output Output Hold from Address Change
SST31LH103-25
Unit
T9.2
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS 3.0-3.6V SST31LH103-15 Symbol Parameter Write Cycle Time Bank Enable Write Address Valid Write Address Set-up Time Write Pulse Width Write recovery Time TOES High Setup Time TOEH High Hold Time Data Set-up Time Data Hold from Write Time
SST31LH103-25
Unit
T10.2
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information CHARACTERISTICS TABLE FLASH READ CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter Read Cycle time Bank Enable Access Time Address Access Time Output Enable Access Time TBLZ BEF# Active Output TOLZ Active Output TBHZ(1) BEF# High High-Z Output TOHZ(1) High High-Z Output Output Hold from Address Change
Units
T11.1
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter Word Program time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time TOES High Setup Time TOEH High Hold Time BEF# Pulse Width Pulse Width TWPH Pulse Width High TBPH BEF# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time TIDA Sector Erase TSBE Bank Erase
Units
T12.1
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
ADDRESS A13-0
BES#
TOLZ
TOHZ TBHZ HIGH-Z DATA VALID
DQ15-0
HIGH-Z
TBLZ
DATA VALID
F02.1
FIGURE SRAM READ CYCLE TIMING DIAGRAM
ADDRESS A13-0 ADDRESS TOES BES# DQ15-0 DATA VALID
F03.1
TOEH
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
ADDRESS A15-0
BEF#
TOLZ
TOHZ TBHZ HIGH-Z DATA VALID
F18.1
DQ15-0
HIGH-Z
TBLZ
DATA VALID
FIGURE FLASH READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS A15-0 5555 BEF# DQ15-0 00AA 0055 00A0 DATA WORD (ADDR/DATA) TWPH 2AAA 5555 ADDR
F04.1
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
INTERNAL PROGRAM OPERATION STARTS ADDRESS A15-0 5555 BEF# DQ15-0 00AA 0055 00A0 DATA WORD (ADDR/DATA) TCPH 2AAA 5555 ADDR
F05.1
FIGURE BEF# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A15-0 BEF# TOEH TOES
F06.1
FIGURE DATA# POLLING TIMING DIAGRAM
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
ADDRESS A15-0 BEF# TOEH TOES
READ CYCLES WITH SAME OUTPUTS F07.1
FIGURE TOGGLE TIMING DIAGRAM
SIX-WORD CODE SECTOR ERASE ADDRESS A15-0 5555 2AAA 5555 5555 2AAA
BEF#
00AA
Note:
DQ15-0
0055
0080
00AA
0055
0030
F08.2
device also supports BEF# controlled Sector Erase operation. BEF# signals interchangeable long minimum timings met. (See table Sector Address
FIGURE CONTROLLED SECTOR ERASE TIMING DIAGRAM
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
SIX-WORD CODE BANK ERASE ADDRESS A14-0 5555 2AAA 5555 5555 2AAA 5555
TSBE
BEF#
DQ15-0
00AA
Note:
0055
0080
00AA
0055
0010
F17.1
device also supports BEF# controlled Bank Erase operation. BEF# signals interchangeable long minimum timings met. (See table
FIGURE CONTROLLED BANK ERASE TIMING DIAGRAM
Three-word sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
BEF#
TWPH DQ15-0 00AA 0055 0090 00BF 0119 DEVICE
F09.2
TIDA
FIGURE SOFTWARE ENTRY READ
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
THREE-WORD SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
00AA
0055
00F0 TIDA
BEF#
F10.0
FIGURE SOFTWARE EXIT RESET
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
VIHT
INPUT REFERENCE POINTS
OUTPUT
VILT
F11.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.7 VDD) (0.8 Input rise fall times (10% 90%)
Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE TESTER HIGH
F12.0
FIGURE TEST LOAD EXAMPLE
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Start
Load data: 00AA Address: 5555
Load data: 0055 Address: 2AAA
Load data: 00A0 Address: 5555
F13.1
Load Word Address/Word Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
FIGURE WORD PROGRAM ALGORITHM
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Internal Timer Word Program/Erase Initiated
Toggle Word Program/Erase Initiated
Data# Polling Word Program/Erase Initiated
Wait TBP, TSBE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match?
Program/Erase Completed
Program/Erase Completed
F14.0
FIGURE WAIT OPTIONS
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Software Product Entry Command Sequence Load data: 00AA Address: 5555 Software Product Exit Reset Command Sequence Load data: 00AA Address: 5555 Load data: 00F0 Address:
Load data: 0055 Address: 2AAA
Load data: 0055 Address: 2AAA
Wait TIDA
Return normal operation
Load data: 0090 Address: 5555
Load data: 00F0 Address: 5555
Wait TIDA
Wait TIDA
Read Software
Return normal operation
F15.1
FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Flash Bank Erase Command Sequence Load data: 00AA Address: 5555
Sector Erase Command Sequence Load data: 00AA Address: 5555
Load data: 0055 Address: 2AAA
Load data: 0055 Address: 2AAA
Load data: 0080 Address: 5555
Load data: 0080 Address: 5555
Load data: 00AA Address: 5555
Load data: 00AA Address: 5555
Load data: 0055 Address: 2AAA
Load data: 0055 Address: 2AAA
Load data: 0010 Address: 5555
Load data: 0030 Address:
Wait TSBE
Wait
Bank erased FFFFH
Sector erased FFFFH
F16.2
FIGURE ERASE COMMAND SEQUENCE
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Concurrent Operation Load Command Sequence
Flash Program/Erase Initiated
Wait Write Indication
Read Write SRAM
Wait
Flash Operation Completed
Concurrent Operation
F19.0
FIGURE CONCURRENT OPERATION FLOWCHART
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information Device SST31LH103 Speed Suffix1 Suffix2 Package Modifier leads Numeric modifier Package Type TSOP 10mm 14mm Unencapsulated Temperature Range Commercial 70°C Industrial -40° 85°C Minimum Endurance 10,000 cycles Read Access Speed SRAM Flash SRAM Flash
SST31LH103 Valid combinations SST31LH103-15-4C-WI SST31LH103-15-4C-U1 SST31LH103-15-4I-WI SST31LH103-25-4C-WI SST31LH103-25-4I-WI SST31LH103-25-4C-U1
Example Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
Advance Information PACKAGING DIAGRAMS
IDENTIFIER 1.05 0.95
.270 .170
10.10 9.90
12.50 12.30
0.15 0.05
0.60 0.40 14.20 13.80
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions metric (min/max). 40.TSOP-WI-ILL.1 Coplanarity: (±.05)
40-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 10MM 14MM PACKAGE CODE:
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Megabit Flash Kilobit SRAM ComboMemory SST31LH103
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(61) 3-762 7644 (32) 1540-0080 (852) 2727-3978 (86) 21-6482-8021 (86) 755-376-2763 (86) 28-553-2896 (86) 10-6261-0042 (86) 27-8788-7226 (86) 29-831-4585 (852) 2421-2379 (86) 10-6858-2188 (86) 21-6485-7530 (86) 28-5577-415 (86) 591-378-1033 (86) 755-321-9726 (852) 2950-0820 (86) 28-524-0208 (86) 21-6473-2080 (86) 755-212-9076 (45) 7010-4888 (358)9 8880 (33) 0414 (33) 7900
North American Sales Representatives
Alabama M-Squared, Inc. Huntsville Arizona QuadRep, Inc. California Costar Northern Falcon Sales Technology Marcos Westar Company, Inc. Calabasas Westar Company, Inc. Irvine Colorado Lange Sales, Inc. Florida M-Squared, Inc. Clearwater M-Squared, Inc. Coral Springs M-Squared, Inc. Longwood Georgia M-Squared, Inc. Atlanta Illinois Oasis Sales Corporation Northern Rush West Associates Southern Indiana Applied Data Management Iowa Rush West Associates Kansas Rush West Associates Maryland Nexus Technology Sales Massachusetts Sales Michigan Applied Data Management Minnesota Cahill, Schmitz Cahill Missouri Rush West Associates North Carolina M-Squared, Inc. Charlotte M-Squared, Inc. Raleigh Jersey Nexus Technology Sales Mexico QuadRep, Inc. York Nexus Technology Sales Reagan/Compar Endwell Reagan/Compar Rochester Ohio Applied Data Management Cincinnati Applied Data Management Cleveland Oregon Thorson Pacific, Inc. Pennsylvania Nexus Technology Sales Texas Technical Marketing, Inc. Carrollton Technical Marketing, Inc. Houston Technical Marketing, Inc. Austin Utah Lange Sales, Inc. Washington Thorson Pacific, Inc. Wisconsin Oasis Sales Corporation Canada Electronics Sales Professionals Ottawa Electronics Sales Professionals Toronto Electronics Sales Professionals Montreal Thorson Pacific, Inc. B.C.
(205) 830-0498 (602) 839-2102 (408) 946-9339 (760) 591-0504 (818) 880-0594 (949) 453-7900 (303) 795-3600 (727) 669-2408 (954) 753-5314 (407) 682-6662 (770) 447-6124 (847) 640-1850 (314) 965-3322 (317) 257-8949 (319) 398-9679 (913) 764-2700 (301) 663-4159 (978) 851-5400 (734) 741-9292 (651) 699-0200 (314) 965-3322 (704) 522-1150 (919) 848-4300 (201) 947-0151 (505) 332-2417 (516) 843-0100 (607) 754-2171 (716) 218-4370 (513) 579-8108 (440) 946-6812 (503) 293-9001 (215) 675-9600 (972) 387-3601 (713) 783-4497 (512) 343-6976 (801) 487-0843 (425) 603-9393 (414) 782-6660 (613) 828-6881 (905) 856-8448 (514) 344-0420 (604) 294-3999
(49) 4192-897910 (49) 7452-60070 (91) 80-526-1102 (91) 40-231130 (91) 11-220-5624 (353) 316116 (972) 3-6498404 (39) 2-424-1471 (81) 3-3350-5418 (81) 93-511-6471 (81) 6-6263-5080 (81) 3-5300-5515 (81) 6-6399-3443 (81) 3-5396-6218 (81) 3-3795-6461 (82) 2-832-8881 (60)4-658-4276 (60) 4-657-0204 (60) 3-737-1243 (31) 40-265-9399 (47) (65) 748-4844 (65) 280-0200 (27) 845-5011 (34) 371-7768 (46)8-459-7900 (41) 27-721-7440/43 (886) 2-2555-0880 (886) 2-2698-0098 (886) 2-2651-0011 (44) 1296-397396
Revised 6-2-99
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
1999 Silicon Storage Technology, Inc.
355-06 5/99
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