56F803 Chip Errata 56F803 Hybrid Controller This docume

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DSP56F803E/D Rev. 3/2004
56F803
Chip Errata
56F803 Hybrid Controller
This document reports errata information chip revision Errata numbers form n.m, where number errata item identifies document revision number. This document prepublication draft. Note: Differences between Chip Revisions listed page errata information chip revisions prior revision have been archived requested from Motorola Sales.
Freescale Semiconductor, Inc.
Chip Revision Errata Information:
following errata items apply Revision 56F803 devices. These parts either marked DSP56F803 PC56F803 with date codes 0137 greater (bottom line marking).
Errata Number Description Quad Timer, when Pulse Output Mode, clock rate yields pluses. outputs disabled during DEBUG mode. Impact Work Around Impact: clock rate creates extra pulse. Work Around: Program pulses only when operating Maximum clock rate. Impact: Safety considerations outputs disabled prior entering DEBUG mode. Work Around: Disable outputs prior entering DEBUG mode. module will continue operate while DEBUG mode unless explicitly disabled. Program Flash Interface Unit (PFIU) address register read returns wrong value when writing out-of-row address. Analog input voltages measured properly. Impact: When verifying out-of-row write, PFIU returns address applied Flash pins, which concatenation register ADDRESS[4:0] bits. Work Around: None. Impact: Inputs 24mV yield measurements Work Around: Bias Analog inputs above Optimal Setup Impact: Better Accuracy Work Around: Recommended values ADCDIV Register:
Motorola, Inc., 2004. rights reserved.
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Chip Revision Errata Information:
following errata items apply Revision 56F803 devices. These parts either marked DSP56F803 PC56F803 with date codes 0137 greater (bottom line marking).
Errata Number Description register available cycle immediately after value change. Impact Work Around Impact: case index+ offset move into register, available cycle immediately following change value. Example: move (R2) Work Around: no-operation (NOP) will need inserted between statements. assembler will modified flag this problem. Timer GPIO interrupts cleared when clearing other interrupts. Impact: timer GPIO modules have several interrupts cleared writing same register. Unfortunately, clearing interrupt unintentionally result clearing interrupt that occurred between time status register read written back. Work Around: enable multiple interrupts single register. Slave Mode (transmitter empty) flag early. Impact: problem only occurs Slave mode when CPHA Transmitter Empty (TE) flag early, thus allowing user software write data value into transmit buffer before current contents loaded into transmit shift register. Work Around: receiver full flag indication when write data into transmit buffer. Slave Mode transmit shift register data corruption. Impact: problem only occurs Slave mode when external master deselected internal (SS=1) provided shift clock internal SPI. This scenario expected system with multiple slave devices. deselected slave transmitter shift register will shift response applied shift clock. This action will cause existing data transmitter shift register become corrupted. Work Around: Modify communications protocol first word returned Slave after being reselected (SS=1 discarded. second subsequent data words after being reselected valid. 10.6 Stabilization Time Impact: Maximum stabilization time 200ms under worst case (-40C) conditions. Typical stabilization time remains 10ms (25C above). Work Around: Insert 200ms delay after power allow settle verify Loss Lock bits (LCK0 LCK1) Status Register (PLLSR) prior program execution.
Freescale Semiconductor, Inc.
56F803 Technical Data
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Chip Revision Errata Information:
following errata items apply Revision 56F803 devices. These parts either marked DSP56F803 PC56F803 with date codes 0137 greater (bottom line marking).
Errata Number 11.8 Description Missed MSCAN transmitter empty interrupt Impact Work Around Impact: When disabling enabling MSCAN transmitter empty interrupt enable (TXEIE) bits transmitter control register (CANTCR) while transmitting peripheral will sometimes miss transmitter empty event. missed event means that ITCN peripheral will notified interrupt service routine transmitter empty interrupt will invoked. sequence below required problem: Start message transmitting TXEIE CANTCR enable MSCAN transmit interrupt. Before message transmission completes clear TXEIE CANTCR disable MSCAN transmit interrupt. very small time window around completion transmission TXEIE CANTCR enable MSCAN transmit interrupt. rare instances above sequence will cause MSCAN peripheral miss transmit empty interrupt. Work Around: most direct work around enable MSCAN transmitter empty interrupt CANTCR then disable enable interrupt using TXEIE bits during active transmissions. disable enable MSCAN transmit empty interrupts during active transmission ITCN peripheral interrupt vector bits. disable transmit interrupt PLR14 bits GPR2 register should zero. enable interrupt PLR14 bits priority above. Using ITCN perform interrupt enabling/disabling function corrects issues never misses transmit empty interrupts.
Freescale Semiconductor, Inc.
56F803 Technical Data
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Chip Revision Errata Information:
following errata items apply Revision 56F803 devices. These parts either marked DSP56F803 PC56F803 with date codes 0137 greater (bottom line marking).
Errata Number 12.8 Description pipeline dependency problem occurs secondary data when read addresses second parallel read crosses address boundary. Instruction sequences which induce this problem combination following: Dual Move Dual Move coupled with MAC, MACR, ADD, SUB, MPYR. memory boundary that issue DSP56F803 0X3FF0X400. Impact Work Around Impact: This problem only applicable assembly coded algorithms will occur algorithms written entirely also applicable when code uses certain libraries primitives that written assembly when data structure local variable (i.e. allocated stack). Typically, second read dual parallel read coefficients filter. Calculating FIRs context primitives affected this condition, with exception (xfr16mult). libraries that affected this erratum V.22, Caller G.165 Function library (dfr16FIR, dfr16FIRs, dfr16FIRInt, dfr16FIRDec xfr16Mult). more details please Motorola FAQs http://www.motorola.com/ semiconductors under Technical Support Contacts. Example:
y0,x0,a y0,x0,a x:(r1)+,y0 x:(r1)+,y0 x:(r3)+,x0 x:(r3)+,x0
Freescale Semiconductor, Inc.
yields different final result than,
y0,x0,a y0,x0,a x:(r1)+,y0 x:(r1)+,y0 x:(r3)+,x0 x:(r3)+,x0
when initial value 0X3FF (1023). same problem occurs when decremented move from above boundary below. This problem only occurs sequential read accesses which secondary data which cross word boundary internal data RAM. problem results from incorrect logic used mediate between multiple internal 1Kx16 memory blocks. Work Around: Work arounds code written user order preference): Move constant coefficient tables from data data FLASH. (Define coefficients const appconst.c, then linker command file will automatically them into data FLASH.) Don't change your project check link located debug folder that coefficient table crosses boundary data RAM. your project MyProject.mcp, will find file MyProject.elf.xMAP debug daughter folder your Codewarrior project.) Dynamically allocate coefficient tables (out internal memory heap space) modify linker command file, breaking heap space crossing boundary into separate pieces memory. Statically allocate coefficient tables that don't have worry about location them heap space. Then modify linker command file that coefficient tables equivalent) cross boundary data RAM. (This require moving coefficients into separate source files.) Define coefficient tables local variables that they allocated stack space. Verify that stack space defined linker command file) does cross boundary. (This approach don't filtering filters relatively short.) other instruction between sequential accesses.
56F803 Technical Data
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Chip Revision Errata Information:
following errata items apply Revision 56F803 devices. These parts either marked DSP56F803 PC56F803 with date codes 0137 greater (bottom line marking).
Errata Number 13.8 Description Problem with Automatic Fault Clearing feature block explained below. fault pins used disable output pins. output pins enabled automatically when fault returns logic zero half cycle begins FMODEx control logic one. only issue with this fault protection mechanism that when fault returns logic zero, channel enabled next clock cycle instead next half cycle. Note that channel always enabled manually after disabled FMODEx logic zero described User's Manual. Impact Work Around Impact: automatic fault clearing used cycle cycle current limiting. This requires cycle-based fault input control. this issue fault input continuously changes voltage thus making difficult output devices respond.
Freescale Semiconductor, Inc.
Work Around: None
56F803 Technical Data
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Chip Revision Errata Information:
following errata items apply Revision 56F803 devices. These parts either marked DSP56F803 PC56F803 with date codes 0137 greater (bottom line marking).
Errata Number 14.13 Description MSCAN extended rejected STUFF between ID16 ID15. Impact Work Around Impact: 32-bit 16-bit identifier acceptance modes, extended frame with stuff between ID16 ID15 erroneously rejected, depending IDAR0, IDAR1, IDMR1. Extended (ID28-ID0) which generate stuff between ID16 ID15
Freescale Semiconductor, Inc.
where (don't care) pattern ID28 ID18 (see following).
Affected extended (ID28 ID18) patterns:
xxxxxxxxx01
exceptions: 01111100001 xxxx1000001 except: 11111000001
xxxxx100000 xxxx0111111 x0111110000 10000000000 11111111111 10000011111
exception: 01111100000
When affected received, incorrect value compared byte filter (IDAR1 IDAR5, plus IDAR3 IDAR7 16-bit mode). This incorrect value shift register contents before ID15 shifted (i.e. right shifted Work Around: problematic cannot avoided, workaround mask certain bits with IDMR1 (and IDMR5, plus IDMR3 IDMR7 16-bit mode). Example receive message xxxx xxxx x011 111x xxxx xxxx xxxx xxxx IDMR1 etc. must 111x xxx1, i.e. ID20,19,18,15 must masked. Example receive message xxxx 0111 1111 111x xxxx xxxx xxxx xxxx IDMR1 etc. must 1xxx xxx1, i.e. ID20 ID15 must masked. general, using IDMR1 etc. 1111 xxx1, i.e. masking ID20,19,18,SRR,15, hides problem. 15.14 halts receiver overflow when being used transmit only. Impact: Same description. Work Around: Read receiver transmit Interupt Service Routine (ISR).
56F803 Technical Data
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Chip Revision Errata Information:
following errata items apply Revision 56F803 devices. These parts either marked DSP56F803 PC56F803 with date codes 0137 greater (bottom line marking).
Errata Number 16.14 Description misses data word double loading Xmit register when double buffering. counter reset each transmission. Impact: Same description. Work Around: only single buffering inside Impact: Must reset part external master malfunctions this way. This only happens slave mode external master generates extra clocks. Work Around: External, master must working correctly generate extra clocks. 18.14 Value from data transmit register moved shift register. Impact: When using CPHA=0, value from data transmit register does move shift register when value been double buffered previous transmission. Work Around: CPHA=1 19.14 receiver shift register residual after overflow resulting duplicate transmission. Impact: Same description. Work Around: software should mask value expected word length during access receive register. Impact: Same description. Work Around: problem eliminated control toggled after receiver full flag Slave mode baud rates slow enough Master side such that signal de-asserted before last inactive edge SPICK signal. Impact: This occurs since clock common MOSI MISO "1s" latched into data register. After transmitting words, OVRF flag while receive data register read software. re-initiate transmission, needs disabled then re-enabled. Clearing OVRF flag will re-initiate transmission this point. Note: This does occur with 16-bit words. Work Around: Always read receive data, even discarded. 22.15 interrupt controller uses COPR SIM_RSTSTS register determine whether reset vector vector table. Impact: user must clear this startup after reset, subsequent resets will reset vector. Workaround: Clear Reset STATUS register. Impact Work Around
17.14
Freescale Semiconductor, Inc.
20.14
Intermittent duplicate transmission slave mode when CPHA=0.
21.14
While enabled master mode transmit data register (less than bits) filled, OVRF flag stops further transmission.
56F803 Technical Data
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Differences between Chip Revisions
Chip Rev.
Date codes 0012 0039
Chip Rev.
marked "Pilsen_B"
Chip Rev.
Date codes 0108 0110
Chip Rev.
Date codes 0111 0128
Chip Rev.
Date codes 0129 0130
Chip Rev.
Date codes 0137
Data memory accesses that immediately preceded peripheral access required instruction inserted between data memory access peripheral access. When external program data memories were used, there potential contention problems
Accesses peripherals longer affect preceding data memory accesses. Corrected
Freescale Semiconductor, Inc.
External signals longer overlap. signal shortened (delayed) ensure that external address stable prior assertion signal. Corrected CLKO external timing more closely aligned with internal processor clocks. Corrected COPR, EXTR bits System Status (SYS_STS) readwriteable. Corrected Five general purpose 16-bit read/writeable registers (TST_REG0 TST_REG4) were added. These registers cleared reset. Corrected read-only registers (MSH_ID LSH_ID) were added. user read JTAG (chip) directly software. Corrected JTAG recorded error errata $11F250D instead $11F2501D. Corrected
CLKO external timing aligned with internal processor clocks. Issue with COPR, EXTR bits System Status (SYS_STS) always read-writeable. TST_REG0 TST_REG4 were available.
MSH_ID LSH_ID were available.
JTAG $01F2501D.
56F803 Technical Data
More Information This Product, www.freescale.com
Differences between Chip Revisions
Chip Rev.
Date codes 0012 0039
Chip Rev.
marked "Pilsen_B"
Chip Rev.
Date codes 0108 0110
Chip Rev.
Date codes 0111 0128
Chip Rev.
Date codes 0129 0130
Chip Rev.
Date codes 0137
Timer module "glitches" clock output signal "Gated Clock".
Freescale Semiconductor, Inc.
Timer module longer "glitches" clock output signal "Gated Clock" Output Mode. silicon will generate "extra" pulse operating maximum frequency rate). using gated clock output mode IPCLK rate, program pulses obtain pulses. Corrected timer disabled power-up Control Register (COPCTL) after reset. Corrected Quadrature Decoder module properly counts index pulses. Corrected Quadrature Decoder module's quadrature bypass mode "ph1" works properly. Corrected current source always enabled (regardless state PLLPD Control Register) ensure circuit powered during power-up. Corrected power-on circuitry 21-bit timer that creates long duration (0.25 sec. MHz) power-on reset RESET input deasserted (held high inactive) during first clock cycles after poweron voltage detection senses power-on sequence. RESET input signal asserted (low active) during first three input clock cycles following power-on sequence, reset period standard clock cycles duration. Corrected
timer disabled power-up.
Quadrature Decoder module properly count index pulses. Quadrature Decoder module's quadrature bypass mode "ph1"did work properly. circuit operate properly power-up.
power-on circuitry operate properly under reset conditions.
56F803 Technical Data
More Information This Product, www.freescale.com
Differences between Chip Revisions
Chip Rev.
Date codes 0012 0039
Chip Rev.
marked "Pilsen_B"
Chip Rev.
Date codes 0108 0110
Chip Rev.
Date codes 0111 0128
Chip Rev.
Date codes 0129 0130
Chip Rev.
Date codes 0137
fault inputs asynchronous.
Freescale Semiconductor, Inc.
fault inputs asynchronous. This enables outputs disabled event loss clock signal (crystal oscillator failure). fault inputs must still least clock cycle duration MHz) fault signal "latched". Shorter fault signals faults that occur during loss clock will disable outputs, outputs will become asserted again when fault signal removed (deasserted). Corrected XTAL input buffer threshold circuit that eliminates spurious noise oscillator start-up. This provides more reliable chip start-up behavior. Corrected module, read accesses PWMVAL1 PWMVAL5 registers work properly when VLMODE[1:0] Corrected ENHA (bit Channel Control Register (PMCCR) read-writeable. Corrected Device meet flash data retention specification years. Improved flash data retention. Data retention specification years 25oC after 10,000 program-erase cycles meet. Same Same Flash endurance data retention meet 5,000 program cycles yrs. over full temp. range. Corrected
XTAL input does buffer spurious noise oscillator start-up.
module, read accesses PWMVAL1 PWMVAL5 registers work properly when VLMODE[1:0] ENHA (bit Channel Control Register (PMCCR) always read zero. Flash endurance specification 10,000 cycles met.
56F803 Technical Data
More Information This Product, www.freescale.com
Differences between Chip Revisions
Chip Rev.
Date codes 0012 0039
Chip Rev.
marked "Pilsen_B"
Chip Rev.
Date codes 0108 0110
Chip Rev.
Date codes 0111 0128
Chip Rev.
Date codes 0129 0130
Chip Rev.
Date codes 0137
Intermittent internal data memory) corruption.
Same
intermittent internal data memory) corruption. Corrected Corrected
voltage VDDA cause inaccurate measurement.
Same
Freescale Semiconductor, Inc.
Intermittent incorrect data return from Data, Program BootFLASH modules. Quad Timer, when Pulse Output Mode, clock rate yields pluses. errata item additional information. this errata error stating corrected. Slave Mode data corrupted MISO output. this errata error stating corrected. outputs disabled during DEBUG mode. errata item additional information. PFIU address register read returns wrong value when writing out-of-row address. errata item additional information. Analog input voltages measured properly. errata item 4for additional information. Optimizing setup. errata item additional information.
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Corrected
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Corrected
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56F803 Technical Data
More Information This Product, www.freescale.com
Differences between Chip Revisions
Chip Rev.
Date codes 0012 0039
Chip Rev.
marked "Pilsen_B"
Chip Rev.
Date codes 0108 0110
Chip Rev.
Date codes 0111 0128
Chip Rev.
Date codes 0129 0130
Chip Rev.
Date codes 0137
register available cycle immediately after value change. errata item additional information. Timer GPIO interrupts cleared when clearing other interrupts. errata item additional information. Slave Mode flag early. errata item additional information. Slave Mode transmit shift register data corruption. errata item additional information. Stabilization Time. errata item additional information. Slow ramp Powerup (>10ms) Missed MSCAN transmitter empty interrupt. errata item additional information. pipeline dependency problem occurs secondary data when dual parallel reads XRAM adjacent instruction cycles, read addresses straddle address boundary. errata item additional information. automatic fault clearing issue. errata item additional information.
Same
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Freescale Semiconductor, Inc.
Same
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Corrected
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56F803 Technical Data
More Information This Product, www.freescale.com
Differences between Chip Revisions
Chip Rev.
Date codes 0012 0039
Chip Rev.
marked "Pilsen_B"
Chip Rev.
Date codes 0108 0110
Chip Rev.
Date codes 0111 0128
Chip Rev.
Date codes 0129 0130
Chip Rev.
Date codes 0137
MSCAN extended rejected STUFF between ID16 ID15. errata item additional information. channel-swapping feature used while operating without risking deadtime violation enabled.
Same
Same
Same
Same
Same
Freescale Semiconductor, Inc.
channel swapping mask logic moved ahead dead time insertion logic. This enables channel-swapping feature used while operating without risking deadtime violation.This changed operation module when operating Complementary mode: Swapper swaps second generator output instead complement primary channel. Corrected Same Same Same Same Same
halts receiver overflow when being used transmit only. errata item additional information. misses data word double loading Xmit register when double buffering. errata item additional information. counter reset each transmission. errata item additional information. Value from data transmit register moved shift register. errata item additional information.
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
56F803 Technical Data
More Information This Product, www.freescale.com
Differences between Chip Revisions
Chip Rev.
Date codes 0012 0039
Chip Rev.
marked "Pilsen_B"
Chip Rev.
Date codes 0108 0110
Chip Rev.
Date codes 0111 0128
Chip Rev.
Date codes 0129 0130
Chip Rev.
Date codes 0137
receiver shift register residual after overflow resulting duplicate transmission. errata item additional information. Intermittent duplicate transmission slave mode when CPHA=0. errata item additional information. While enabled master mode transmit data register (less than bits) filled, OVRF flag stops further transmission. errata item additional information. interrupt controller uses COPR SIM_RSTSTS register determine whether reset vector vector table. errata item clarification.
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Same
Freescale Semiconductor, Inc.
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
56F803 Technical Data
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
56F803 Technical Data
More Information This Product, www.freescale.com
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Freescale Semiconductor, Inc.
Motorola Stylized Logo registered U.S. Patent Trademark Office. digital trademark Motorola, Inc. This product incorporates SuperFlash® technology licensed from SST. other product service names property their respective owners. Motorola, Inc. Equal Opportunity/Affirmative Action Employer Motorola, Inc. 2004
DSP56F803/D
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56F803 Chip Errata 56F803 Hybrid Controller This docume

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