CLOCK RECOVERY MK1575-01 clock recovery Phase-Locked Loop (PLL) d
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MK1575-01
CLOCK RECOVERY
MK1575-01 clock recovery Phase-Locked Loop (PLL) designed clock synthesis synchronization cost sensitive applications. device optimized accept low-frequency reference clock generate high-frequency data graphics pixel clock. External loop filter components allow tailoring loop frequency response characteristics. jitter phase noise requirements refer MK2069 products.
Pre-Configured Input/Output Frequency Combinations:
Telecom Clock Modes (rising edge aligned):
Addr FS2:0
Input Clock
Output Clocks (MHz) CLK1 CLK2
3.088 16.384 34.368 44.736 1.544 2.048 17.184 22.368
Clock Type
Features
Long-term output jitter nsec over µsec period External clock feedback path enable "zero
delay" clock skew configuration Selectable internal feedback divider provides popular telecom video clock frequencies (see tables below) optionally external feedback divider generate other output frequencies. Single supply, low-power CMOS Power-down mode output tri-state (pin Packaged 16-pin TSSOP Available (lead) free package Industrial temperature range available
Video Clock Modes (falling edge aligned):
Addr Input FS2:0 Clock (kHz)
15.625 15.734 15.625 15.734
Output Clocks (MHz) CLK1 CLK2
35.468 28.636 17.734 14.318
Clock Type
NTSC 4xfsc NTSC 4xfsc
Block Diagram
standard external clock feedback configuration shown. this configuration pre-configured input/output frequency combinations listed above.
CHGP
Phase Charge Detector Pump
CHPR
Clock Input
REFIN
Divider CLK2 Divider
CLK1 CLK2
FBIN
Divider
FCLK Divider
FCLK
FS2:0
External Feedback Clock Connection
1575-01
Race Stre 5126
Revision 062504 97-12
MK1575-01 CLOCK RECOVERY
Assignment
REFIN VDDA VDDD GNDA GNDD CHGP FBIN FCLK CLK2 CLK1 CHPR
4.40 body, 0.65 pitch TSSOP
Descriptions
Number
Name
REFIN VDDA VDDD GNDA GNDD CHGP CHPR CLK1 CLK2 FCLK FBIN
Type
Input Input Power Power Input
Reference clock input. Connect input clock this pin. Rising Falling edge triggered Detailed Mode Selection Table, page Frequency Selection Input selects internal divider values Detailed Mode Selection Table, page Power supply connection internal other analog circuits. Power supply connection internal digital circuits output buffers. Frequency Selection Input selects internal divider values Detailed Mode Selection Table, page
Ground Ground connection internal other analog circuits. Ground Ground connection internal digital circuits output buffers. Output Input Output Input Output Input Loop filter connection, active node. Loop filter connection, reference node. connect ground. Output clock Frequency Selection Input selects internal divider values Detailed Mode Selection Table, page Output clock Output Enable, tristates CLK1, CLK2, FCLK powers down when high. Internal pull-up. Feedback clock output, connect FBIN pre-configured frequency combinations listed tables page internal connection, connect ground. Feedback clock input. Connect CLK1, CLK2, FCLK, output external feedback divider, depending application. Refer document text more information.
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY
Detailed Mode Selection Table
Refer this table when using standard external clock feedback configuration shown page
Address FS2:0
Internal Divider Settings Divider
CLK2 Divider FCLK Divider
2048 4296 5592 3456 3432 2270 1820
FBIN, REFIN Clock Edge
Rising Rising Rising Rising Falling Falling Falling Falling
CLK1 Output Frequency Range
Block Diagram, Showing Device Configuration Options
CHGP
Phase Charge Detector Pump
CHPR
Clock Input
REFIN
Divider CLK2 Divider
CLK1 CLK2
FBIN
Divider
FCLK Divider
FCLK
FS2:0
Divider Optional External Feedback Divider
Feedback Clock Options (only connect output)
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY
Functional MK1575-01 (phase-locked loop) based clock generator that generates output clocks synchronized input reference clock. device used standard configuration described page optionally external divider clock feedback path produce other frequency multiplication factors. External components used control loop response. external loop components enables lower loop bandwidth which needed when accepting frequency input clocks such those listed tables page
page output clock frequency increased. Refer Output Frequency Calculation table below.
CLK1 FBIN
When external feedback divider used, this option configures device zero-delay buffer frequency CLK1 same input reference clock. Including external divider feedback path will increase output clock frequency. Refer Output Frequency Calculation table below.
CLK2 FBIN
Like above configuration, this option configures device zero-delay buffer when external feedback divider used, frequency CLK2 same input reference clock. Including external divider feedback path will increase output clock frequency. Refer Output Frequency Calculation table below.
Clock Feedback Options
FCLK FBIN
This standard configuration that used pre-configured input output frequency combinations listed page including external divider feedback path ("FB Divider" Block Diagram
Frequency Bandwith Calculations
Feedback Path Option Output Clock Frequency CLK1 CLK2 FCLK Frequency
Factor
FCLK FBIN CLK1 FBIN CLK2 FBIN
FCLK
FCLK -CLK2 -CLK2
-FCLK CLK2 -FCLK
FCLK
FCLK
CLK2
CLK2
CLK2
Notes: when feedback divider used. Refer Detail Mode Selection Table page possible divider combinations. frequency needs considered applications (see table below). external loop filter also needs considered. Minimum frequency MHz. Maximum frequency MHz. minimize output jitter, highest possible frequency allowed application.
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY
Setting Loop Bandwidth Damping Factor
frequency response MK1575-01 approximated following equation:
Normalized Bandwidth
applications, higher damping factor usually desirable. higher damping factor will create less passband gain peaking which will minimize gain network clock wander amplitude. higher damping factor also increase output clock jitter when there excess digital noise system application, reduced ability respond therefore compensate for, phase noise ingress.
Notes setting value
associated damping factor calculated follows:
another general rule, following relationship should maintained between components external loop filter:
Damping factor,
Where: gain Hz/Volt (use MHz/V) Charge pump current, 12.5 Total feedback divide from VCO, (Refer Value table, below) External loop filter capacitor Farads Loop filter resistor Ohms Where:
External bypass capacitor Farads Note that MK1575-01 contains internal filter which connected parallel with external device This helps reduce output clock jitter. some applications external device will required. establishes second pole loop filter. higher damping factors (>1), calculate value based value that would used damping factor This will minimize baseband peaking loop instability that lead output jitter. also helps damp input voltage modulation caused charge pump correction pulses. value that will result increased output phase noise phase detector frequency this. extreme cases where input jitter high, charge pump current high, small, input voltage supply ground rail resulting non-linear loop response. best value External Loop Filter Solver
above bandwidth equation calculates "normalized" loop bandwidth which approximately equal bandwidth. This approximate calculation does take into account effects damping factor third pole imposed does, however, provide useful approximation filter performance. prevent jitter output clocks modulation input reference frequency, following general rule should observed: Bandwidth
Phase Detector
general, loop damping factor should greater ensure output stability. video applications, damping factor (0.7 1.0) generally desired fast genlocking. telecom
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY
Loop Filter Capacitor Type
Clock Jitter input-to-output skew performance MK1575-01 affected loop filter capacitor type. Cost performance trade-offs made when choosing capacitor types. Performance
differences best determined through experimentation. Recommended capacitors found
Example Loop Filter Component Values Pre-Configured Frequency Combinations Listed Page
Addr Input Frequency
15.625 15.734 15.625 15.734
Output Frequency Factor (MHz) CLK1 CLK2
Loop Loop Passband Damp Peaking (-3dB)
4.46 3.24 4.67 3.16 4.56 2.62 4.69 0.72 0.73 0.73 0.19 0.06 0.12 0.05 0.13 0.06 0.17 0.05 2.16 2.15 2.15 2.42
Notes
3.088 3.088
1.544 1.544
24704 24704 32768 32768 34368 34368 22368 22368 13824 13728 18160 14560
16.384 2.048 16.384 2.048 34.368 17.184 34.368 17.184 44.736 22.368 44.736 22.368
0.068 0.068 0.068 0.068
35.468 17.734 28.636 14.318
Notes: This loop filter selection optimized cost component size. provides stable clock outputs moderate input reference jitter attenuation. This configuration could used when producing internal system clock, which will used data transmit clock when locked recovered data clock. This loop filter selection optimized pass-band peaking. This configuration should used when generating data transmit clock that locked recovered data clock. This will ensure that data clock conforms with Belcore GR-1244-CORE wander transfer specifications. loop bandwidth damping factor typical video genlock applications. This combination assures minimal Hsync frequency modulation pixel clock genlocking. Example vendors part numbers above capacitor selections: 0.15 0.68
1575-01 grated Circuit Systems
Panasonic ECP-U1C154MA5 (SMT film type, 1206 size, available from DigiKey) Panasonic ECP-U1C684MA5 (SMT film type, 1206 size, available from DigiKey) MuRata GRM42-2X5R106K10 Panasonic ECH-U1C103JB5 (SMT film type, size, available from DigiKey) Panasonic ECH-U1C333JB5 (SMT film type, 1206 size, available from DigiKey)
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY
Input-to-Output Skew Induced Loop Filter Leakage
Leakage across loop filter, contamination poor quality loop filter capacitors, increase input-to-output clock skew error. Concern regarding input-to-output skew error usually limited "zero delay" configurations, where CLK1 CLK2 directly connected FBIN. sever cases loop filter leakage, however, output clock jitter also increased. capacitors external loop filter maintain frequency control voltage between charge pump pulses, which design coincide with phase detector events. frequency phase adjustments made these charge pump pulses, pumping current into external loop filter capacitors adjust control voltage needed. Like capacitors, CHGP (pin high-impedance node; charge pump current source, which high impedance definition, input also high impedance. During normal (locked) operation, event current leakage loop filter, charge pump will need deliver equal opposite charge form longer charge pump pulses. increased length charge pump pulse will translated directly increased input-to-output clock skew. This also result higher output jitter higher reference clock feedthrough (where reference clock fREFIN), depending loop filter attenuation characterisitcs. Input-to-Output skew parameters Electrical Specifications assume minimal loop filter leakage. Additional skew loop filter leakage calculated follows:
Leakage Leakage Induced Skew (sec) REFIN
open clock feedback path with MK1575-01 enabled. MK1575-01 enabled does feedback clock into FBIN, output frequency will forced maximum value PLL. external divider feedback path delay before becoming active, hold high until divider ready work. This could occur, example, divider implemented FPGA. Holding high powers down MK1575-01 dumps charge loop filter. external divider used feedback path, circuit that operate well beyond intended output clock frequency.
Power Supply Considerations
with integrated clock device, MK1575-01 special power supply requirements:
feed from system power supply must
filtered noise that cause output clock jitter. Power supply noise sources include system switching power supply other system components. noise interfere with device components such phase detector.
Each must decoupled individually
prevent power supply noise generated device circuit block from interfering with another circuit block.
Clock noise from device pins must onto
power plane system problems result. This above requirements served circuit illustrated Optimum Power Supply Connection, below. main features this circuit follows:
Only connection made power
plane.
capacitors ferrite chip ferrite bead)
common device supply form lowpass `pi' filter that remove noise from power supply well clock noise back toward supply. bulk capacitor should tantalum type, minimum. other capacitors should ceramic type.
Avoiding Lockup
some applications, MK1575-01 "lock it's maximum operating frequency. avoid this problem observe following rules:
power supply traces individual pins
should common supply filter reduce interaction between device circuit blocks.
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY decoupling capacitors pins should
ceramic type should close possible. There should vias between decoupling capacitor supply pin.
Because each input selection includes internal pull-up device, those inputs requiring logic high state ("1") left unconnected. pins requiring logic state ("0") grounded.
Optimum Power Supply Connection
Connection 3.3V Power Plane Ferrite Chip BULK VDDA
Loss Reference Clock
loss occurs REFIN clock, output frequency will decrease rate 4250 Hz/s
0.01
0.01
VDDD
where: value divider (from table page input held low, output will stop high low, might toggle several
Frequency Operation Series Termination Resistor
Output clock traces over inch should series termination maintain clock signal integrity reduce EMI. series terminate trace, which commonly used trace impedance, place resistor series with clock line close clock output possible. nominal impedance clock output output frequency extended below adding divider output path. this configuration, desirable take feedback signal from CLK1 rather than output divider. However, zero delay operation required, feedback signal must come from divider output.
Layout Recommendations
optimum device performance lowest output phase noise, following printed circuit board layout recommendations should observed. Each 0.01µF power supply decoupling capacitor should mounted close possible. trace should kept short possible, should trace ground via. Distance ferrite chip bulk decoupling from device less critical. loop filter components (RZ, must also placed close CHGP pins. should closest device. Coupling noise from other system signal traces should minimized keeping traces short away from active signal traces. vias should avoided. minimize series termination resistor, needed, should placed close clock output.
MK1575-01 Typical Transfer Curve
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY
Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK1575-01. These ratings, which standard values commercially rated parts, stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature (industrial version) Ambient Operating Temperature (commercial version) Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5 VDD+0.5 +85°C +70°C +150°C 125°C 260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (industrial version) Ambient Operating Temperature (commercial version) Power Supply Voltage (measured respect GND)
Min.
+3.15
Typ.
Max.
Units
+3.3
+3.45
Electrical Characteristics
Unless stated otherwise, ±5%, Ambient Temperature +70°
Parameter
Operating Voltage Supply Current
Symbol
Conditions
Clock outputs unloaded,
Min.
3.15
Typ.
Max.
3.45
Units
Supply Current Power Down Charge Pump Current Input High Voltage Input Voltage Input High Current Input Current Input Capacitance, except
12.5
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY
Parameter
Output High Voltage (CMOS Level) Output High Voltage
Symbol
Conditions
CLK1, CLK2 FCLK
Min.
VDD-0.4
Typ.
Max.
Units
Output Voltage
CLK1, CLK2 FCLK
Short Circuit Current Nominal Output Impedance
ZOUT
CLK1, CLK2 FCLK
Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +70°
Parameter
Input Clock Frequency (into pins REFIN FBIN) Internal Frequency Output Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle Jitter, Absolute Peak-to-peak
Symbol
fREF fVCO fCLK
Conditions
Min.
Typ.
Max.
Units
VDD/2 Single cycle measurement; Deviation from mean trigger delay
Long Term Timing Jitter, pk-pk Gain
tJLT
MHz/V
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY
Package Outline Package Dimensions (16-pin TSSOP, 4.40 Body, 0.65 Pitch)
Package dimensions kept current with JEDEC Publication MO-153
Millimeters Symbol
Inches
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 -0.004
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
MK1575-01 CLOCK RECOVERY
Marking Diagram (commercial)
Marking Diagram (industrial)
1575-01G ###### YYWW
1575-01GI ###### YYWW
Marking Diagram free, commercial)
1575-01GL ###### YYWW
Notes: ###### number. YYWW last digits year week number that part assembled. designates (lead) free package. designates industrial temperature grade.
Ordering Information
Part Order Number
MK1575-01G MK1575-01GTR MK1575-01GI MK1575-01GITR MK1575-01GLF MK1575-01GLFTR
Marking
1575-01G 1575-01G 1575-01GI 1575-01GI 1575-01GL 1575-01GL
Shipping Packaging
Tubes Tape Reel Tubes Tape Reel Tubes Tape Reel
Package
16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP
Temperature
"LF" denotes (lead) free package. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
1575-01 grated Circuit Systems
Street, Jose, 9512
Revision 062504 297-1
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