DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR differential LVDS

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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR differential LVDS

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ICS8745BI-21
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
differential LVDS output pair designed meet exceed requirements ANSI TIA/EIA-644, differential feedback output pair Differential CLK, nCLK input pair CLK, nCLK pair accept following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Output frequency range: 31.25MHz 700MHz Input frequency range: 31.25MHz 700MHz range: 250MHz 700MHz External feedback "zero delay" clock regeneration with configurable frequencies Programmable dividers allow following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, Cycle-to-cycle jitter: 30ps (maximum) Output skew: 40ps (maximum) Static phase offset: 25ps 125ps 3.3V supply voltage -40°C 85°C ambient operating temperature
GENERAL DESCRIPTION
ICS8745BI-21 highly versatile LVDS Clock Generator member HiPerClockSHiPerClockSTMfamily High Performance Clock Solutions from ICS. ICS8745BI-21 fully integrated configured zero delay buffer, multiplier divider, output frequency range 31.25MHz 700MHz. Reference Divider, Feedback Divider Output Divider each programmable, thereby allowing following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. external feedback allows device achieve "zero delay" between input clock output clock. PLL_SEL used bypass system test debug purposes. bypass mode, reference clock routed around into internal output dividers.
BLOCK DIAGRAM
PLL_SEL
÷16, ÷32,
ASSIGNMENT
nQFB
nCLK nFB_IN FB_IN SEL2 VDDO nQFB SEL1 SEL0 PLL_SEL VDDA SEL3 VDDO
nCLK
8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
FB_IN nFB_IN
ICS8745BI-21
20-Lead, 300-MIL SOIC 7.5mm 12.8mm 2.3mm body package Package View
SEL0 SEL1 SEL2 SEL3
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Type Description
TABLE DESCRIPTIONS
Number Name nCLK nFB_IN FB_IN SEL2 VDDO SEL3 VDDA PLL_SEL SEL0 SEL1 Input Input Input Input Input Input Power Power Output Input Power Input Power Input Input Pullup Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Active HIGH Master Reset. When logic HIGH, internal dividers reset causing true outputs inver outputs Pulldown high. When logic LOW, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Pullup Feedback input phase detector regenerating clocks with "zero delay". Pullup Pulldown Feedback input phase detector regenerating clocks with "zero delay". Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Output supply pins. Differential feedback outputs. LVDS interface levels. Power supply ground. Differential clock outputs. LVDS interface levels. Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Analog supply pin. Selects between reference clock input dividers. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS LVTTL interface levels. Core supply pin.
nQFB, Output
Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Pulldown Determines output divider values Table LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL Enable Mode
TABLE CONTROL INPUT FUNCTION TABLE
Inputs SEL3 SEL2 SEL0 Reference Frequency Range (MHz)* 62.5 31.25 87.5 62.5 -700 62.5 31.25 87.5 62.5 31.25 87.5 31.25 87.5
*NOTE: frequency range configurations above 250MHz 700MHz.
TABLE BYPASS FUNCTION TABLE
Inputs SEL3
8745BMI-21
Outputs PLL_SEL Bypass Mode
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
4.6V -0.5V 0.5V 10mA 15mA 46.2°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage Input High Current CLK_SEL, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, SEL0, SEL1, SEL2, SEL3 PLL_SEL 3.465V 3.465V 3.465V, 3.465V, -150 Test Conditions Minimum -0.3 Typical Maximum Units
Input Current
TABLE DIFFERENTIAL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter VCMR Input High Current Input Current CLK, FB_IN nCLK, nFB_IN CLK, FB_IN nCLK0, nFB_IN Test Conditions 3.465V 3.465V 3.465V, 3.465V, -150 0.15 0.85 Minimum Typical Maximum Units
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE
NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage CLK, nCLK 0.3V.
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum 1.05 Typical Maximum 1.35 Units
TABLE LVDS CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Differential Output Voltage Magnitude Change Offset Voltage Magnitude Change
TABLE INPUT FREQUENCY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input Frequency CLK, nCLK Test Conditions PLL_SEL PLL_SEL Minimum 31.25 Typical Maximum Units
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE Static Phase Offset; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter NOTE Phase Jitter NOTE Output Duty Cycle Lock Time PLL_SEL 700MHz PLL_SEL 3.3V -100 Test Conditions Minimum Typical Maximum Units
tsk(o) tjit(cc) tjit()
Output Rise/Fall Time; NOTE NOTE Measured from differential input crossing point differential output crossing point. NOTE Defined time difference between input reference clock averaged feedback input signal across conditions, when locked input reference frequency stable. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE Phase jitter dependent input source used. NOTE This parameter defined accordance with JEDEC Standard NOTE Characterized frequency 622MHz. NOTE Measured from points. Guaranteed characterization. production tested.
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V
SCOPE
nCLK
3.3V±5% Power Supply Float
LVDS
Cross Points
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nCLK nFB_IN FB_IN
sk(o)
mean Phase Jitter
mean Static Phase Offset
(where random sample, mean average sampled cycles measured controlled edges)
PHASE JITTER
STATIC PHASE OFFSET
OUTPUT SKEW
nQFB
tcycle
tcycle
Clock Outputs
jit(cc) tcycle -tcycle
1000 Cycles
CYLE-TO-CYCLE JITTER
8745BMI-21
OUTPUT RISE/FALL TIME
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
nCLK nQFB
nQFB
Pulse Width
PERIOD
PERIOD
PROPAGATION DELAY
OUPUT DUTY/CYCLE/PULSE WIDTH/PERIOD
Input
LVDS
VOS/
Input
LVDS
VOD/
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VDD/2 generated bias resistors This bias circuit should located close possible input pin. ratio
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Single Ended Clock Input V_REF nCLK 0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
general LVDS interface shown Figure differential transmission line environment, LVDS drivers require matched load termination across near receiver input. multiple LVDS outputs buffer, only partial outputs used, recommended terminate un-used outputs.
3.3V
3.3V
LVDS_Driv
Differiential Transmission Line
FIGURE TYPICAL LVDS DRIVER TERMINATION
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8745BI-21 provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA pin.
3.3V .01µF VDDA .01µF
FIGURE POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
3.3V 3.3V
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V
3.3V
LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
8745BMI-21
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
depend selected component types density P.C. board.
LAYOUT GUIDELINE
schematic ICS8745BI-21 layout example shown Figure ICS8745BI-21 recommended board layout this example shown Figure This layout example used general guideline. layout actual system will
3.3V
(155.52 MHz)
3.3V PECL Driv
SEL2 VDDO
nCLK nFB_IN FB_IN SEL2 VDDO nQFB
SEL1 SEL0 VDDI PLL_SEL VDDA SEL3 VDDO
SEL1 SEL0 PLL_SEL VDDA SEL3
0.1uF
0.01u
VDDO
Space (i.e. intstalled)
ICS8745B-21
(77.76 MHz)
PLL_SEL SEL0 SEL1 SEL2 SEL3
Bypass capacitors located near power pins
(U1-7)
VDDO
(U1-11)
VDD=3.3V
LVDS_input
VDDO=3.3V
0.1uF
erential
0.1uF
SEL[3:0] 0101, Divide
FIGURE ICS8745BI-21 LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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REV. MARCH 2004
following component footprints used this layout example: resistors capacitors size 0603.
ICS8745BI-21
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. differential output traces should have equal length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. series termination resistors should located close driver pins possible.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VDDA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace
ICS8745B-21
VDDO
VDDA
Differential Traces
FIGURE BOARD LAYOUT ICS845BI-21
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD SOIC
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 46.2°C/W
65.7°C/W 39.7°C/W
57.5°C/W 36.8°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8745BI-21 2772
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
LEAD SOIC
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
SYMBOL 10.00 0.25 0.40 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 Millimeters Minimum 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication MS-013, MO-119
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
TABLE ORDERING INFORMATION
Part/Order Number ICS8745BMI-21 ICS8745BMI-21T Marking ICS8745BMI-21 ICS8745BMI-21 Package Lead SOIC Lead SOIC Tape Reel Count tube 1000 Temperature -40°C 85°C -40°C 85°C
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8745BMI-21
REV. MARCH 2004
ICS8745BI-21
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET Description Change LVDS Characteristics Table modified 0.90V min. 1.05V min, 1.15V typical 1.2V typical, 1.4V max. 1.35V max. Date 3/17/04
Table
Page
8745BMI-21
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR differential LVDS

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