This document describes corrections MPC885 PowerQUICCUser's Manual, Re

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MPC885 RMAD Rev. 6/2004 Errata MPC885 PowerQUICCReference Manual Rev.
This document describes corrections MPC885 PowerQUICCUser's Manual, Rev.1 convenience, chapter number page number each erratum provided. Items bold since last revision this document. locate published updates this document, refer worldwide
Table Document Revision History
Revision Initial release document Significant Changes
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Chapter, Page General erratum 10.4.1, pg.10-5 Changes Replace instances term `60x' with `external.' Figure Table 10-2, 0-13 bits only instead 0-15 bits. reserved bits. restricted containing only value order prevent conflicts between Internal Memory SEC's memory map. addition, part number, `PARTNUM', should 0000_1001 0x09 instead 000_0000 that stated. first bullet note dealing with internal clock EXTCLK, following: "Assuming EXTCLK between 50Mhz 80Mhz". description, inductor value bypass capacitor values provide two-pole filter with cutoff frequency Hz.", change Figure 14-13 Table 14-9, PLPRCR, field FIOPD should removed replaced with "RESERVED". Table 18-4. RCCR Field Descriptions please chnage External interrupt enable. Configure instructed download process Motorola-supplied microcode package. DREQ0 cannot interrupt DREQ0 will interrupt This must enable host generation. 19.1.2, pg.19-3 31.7.1, pg.31-10 31.7.2, pg.31-12 31.7.2, pg.31-12 Table 19-1, replace term Core' with `PTEC Core'. Figure 31-5, arrow bottom `Preamble' should point opposite direction. Figure 31-6, `dreq0' signal should point opposite direction. last paragraph, please change (Also erratum 18.6.1, pg.18-6) DREQ0 should configured external interrupt should RCCR. When there hardware originated requests enters stall state. Configuring DREQ0 external interrupt request ensures that only hardware interrupt request wake host controller. 31.13, pg.31-30 35.2.1, pg.35-4 36.5, pg.36-8 45.2.1, pg.45-3 45.2.5, pg.45-7 45.3.1, pg.45-12 value bits 7(OPCODE) stated Note should change from "1101" "1111". First bullet should reference SPS=0 second bullet should reference SPS=1. Figure 36-2, replace term Core' with `PTEC Core'. Table 45-2, `(input)' next signal descriptions `Transmit Clock' `Receive Clock'. Figure 45-2, promiscuous mode check bottom should indicate when R_CNTRL[PROM] state machine leads False. following note below Table 45-6: NOTE auto-negotiation used, then recommended configure RMIIx_RATE_FECx after finished auto-negotiation. user then read line speed from status registers using management frames, then configure RMIIx_RATE_FECx accordingly.
14.3.1.3, pg.14-14 14.4.3, pg.14-18
14.6.2, pg.14-23
18.6.1, pg.18-6
Errata MPC885 PowerQUICCReference Manual Rev. More Information This Product, www.freescale.com
MOTOROLA
Chapter, Page 45.3.2.13, pg.45-26 Changes last paragraph following: MPC88x MPC87x, management interface transactions must done through FEC1 registers. This includes MII_SPEED MII_DATA registers." Figure 45-17, remove address offset(s) FEC_2, 0x1E80 0x1E82. Figure 45-18, remove address offset(s) FEC_2, 0x1E84 0x1E86. Under first bullet, remove sentence that says time-slot assigner implemented. following note below second paragraph: NOTE actual number active address signals selected UTMODE [ADDPIN]; Section "UTOPIA Mode Register (UTMODE)." When address signal activated, reverts function defined PBDIR alone becomes don't care). example, assuming that UTOPIA interface been initialized properly, only seven PHYs used UTOPIA master application, SMC1 data signals still available because RxAddr TxAddr active.
45.3.2.13, pg.45-25 45.3.2.14, pg.45-26 Appendix 42.2.2, pg.42-5
MOTOROLA
Errata MPC885 PowerQUICCReference Manual Rev. More Information This Product, www.freescale.com
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Information this document provided solely enable system software implementers Motorola products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without
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Motorola Stylized Logo registered U.S. Patent Trademark Office. digital trademark Motorola, Inc. described product contains PowerPC processor core. PowerPC name trademark Corp. used under license. other product service names property their respective owners. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Motorola, Inc. 2004
MPC885UMAD/D
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This document describes corrections MPC885 PowerQUICCUser's Manual, Re

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