INTRODUCTION Various Semiconductor components packaged advanced Quad F

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INTRODUCTION Various Semiconductor components packaged advanced Quad F

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AND8121/D Board Mounting Notes NIS3001 Leadless Package-in-a-Package (PINPAK)
INTRODUCTION Various Semiconductor components packaged advanced Quad Flat-pack No-Lead Package (QFN) commonly referred Leadless Package. Because QFN(Leadless) platform represent latest surface mount packaging technology, important that design Printed Circuit Board (PCB), well assembly process, follow suggested guidelines outlined this document.
NIS3001 Package Overview
while pads have solder mask over edge metallization, shown Figure With Pads, solder mask restricts flow solder paste metallization which prevents solder from flowing along side metal pad. This different from NSMD configuration where solder will flow around both sides metallization.
Solder Mask Opening
platform offers versatility, which allows either single multiple semiconductor devices connected together within leadless package. this case NIS3001 Package contains multiple semiconductor devices within package. This package style chosen excellent thermal dissipation reduced electrical parasitics. When surface mounting this package onto PCB, critical issues must considered: Printed Circuit Board Design Board Mounting Process. This document will address both these critical issues. Printed Circuit Board Design Considerations
NSMD configurations
Solder Mask Overlay
Solderable
NSMD
Figure Comparison NSMD versus pads.
There different types configurations commonly used surface mount leadless style packages. These different configurations are: Solder masked Defined (NSMD) Solder Masked Defined (SMD) their titles describe, NSMD contact pads have solder mask pulled away from solderable metallization,
Typically, NSMD pads preferred over configuration since defining location size copper easier control than solder mask. This based fact that copper etching process capable tighter tolerance than solder masking process. addition, pads will inherently create stress concentration point where solder wets lead. This stress concentration point eliminated when solder allowed flow down sides leads NSMD configuration.
Semiconductor Components Industries, LLC, 2003
June, 2003 Rev.
Publication Order Number: AND8121/D
AND8121/D
NSMD Configurations
When dimensionally possible, solder mask should located least ±0.076mm (0.003in) away from edge solderable pad. This spacing used compensate registration tolerances solder mask, well insure that solder inhibited mask reflows along sides metal pad. dimensions soldermask openings shown Figure preferred non-soldermask configuration. dimensions PCB's solderable pads should match those pads package shown Figure ratio between package's configuration, that PCB's, desired optimal placement accuracy reliability. Please note that NIS3001 Footprint shows smaller exposed openings compared with recommended layout. attach pads footprint were divided into smaller exposed pads help reduce risk solder voiding during reflow mounting package
0.508
3.810
1.765
0.941
9.992 6.274
4.720
1.765
6.745
Figure NSMD Openings Layout
0.356 1.612
0.356 0.789
1.689 1.612
3.658
3.261 3.439
0.789
3.261
9.840
2.169
R0.380
4.568
2.861
1.612 3.096 NIS3001 Footprint
1.612
6.592
Recommended Pattern NIS3001 Footprint
Figure Recommended Layout NIS3001 footprint Thermal/Electrical Vias
Vias normally placed larger attach pads improve electrical thermal performance. vias required larger attach pads, recommendation filled-vias. Filled-vias will help prevent solder from flowing down into holes, thereby reducing solder volume required solder joint this attach pad. Filled-vias normally filled with some type conductive epoxy. through-hole vias used, recommend that size less than equal 0.25mm(10 mils). number vias placed over attach also critical should exceed total exposed area copper pattern. other words, excessive through-hole vias will allow solder flow down into thereby decrease solder volume needed have sufficient
solder joint. These vias plugged with solder mask material avoid soldering wiching.
NIS3001 Board Mounting Process
board mounting process optimized first defining controlling following processes: Creating maintaining solderable metallization contacts. Choosing proper solder paste. Screening/stenciling solder paste onto PCB. Placing package onto PCB. Reflowing solder paste. Final solder joint inspection. Recommendations each these processes located below.
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AND8121/D
Solderable metallization
There common plated solderable metallizations, which used surface mount devices. either case, imperative that plating uniform, conforming, free impurities insure consistent solderable system. first metallization consists Organic Solderability Preservative coating (OSP) over copper plated pad. organic coating assists reducing oxidation order preserve copper metallization soldering. second recommended solderable metallization consists plated electroless nickel over copper pad, followed immersion gold. thickness electroless nickel layer determined allowable internal material stresses temperature excursions board will subjected throughout lifetime. Even though gold metallization typically self-limiting process, thickness should least 0.05 thick, consist more than overall solder volume. Having excessive gold solder joint create gold embitterment which affect reliability joint.
Solder Type
0.356
0.700
1.015
0.789
Attach Pads
1.621
1.000
0.811 0.928 1.856
Figure Solder stencil design illustrating smaller stencil openings over larger exposed pads. Solder Reflow
Solder paste such Cookson Electronics' WS3060 with Type smaller sphere size recommended. WS3060 water-soluble flux cleaning. Cookson Electronics' PNC0106A used no-clean flux preferred.
Solder Screening onto
Less than 2°C/sec
Figure Typical reflow profile eutectic tin/lead solder.
Package Placement onto
Pick place equipment with standard tolerance ±0.05 better recommended. package will tend center itself correct slight placement errors during reflow process surface tension solder.
general, temperature part should raised more than 2°C/sec during initial stages reflow profile. soak zone then occurs when part approximately 150°C should last seconds. Typically, extending time soak zone will reduce
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Time Soak Above Zone Liquidus sec)
Time (sec)
Stencil screening solder onto board commonly used industry. recommended stencil thickness used 0.075 (0.003 sidewalls stencil openings should tapered approximately degrees facilitate release paste when stencil removed from PCB. Note that 0.127 (0.005 thick stencil used also, will require smaller stencil openings reduce amount solder applied equal amount solder applied using 0.075 thick stencil. typical edge terminal pad, stencil opening should same size size package. However, cases where soldered PCB, stencil opening must divided into smaller openings shown Figure Dividing larger pads into smaller screen openings reduces risk solder voiding allows solder joints smaller terminal pads same height larger ones.
Once package placed board along with solder paste, standard surface mount reflow process used mount part. Figure example standard reflow profile. exact profile will determined, available, manufacture paste since chemistry viscosity flux matrix will vary. These variations will require small changes profile order achieve optimized process.
Peak 225°C
Temperature (5C)
AND8121/D
risk voiding within solder. temperature then raised will above liquidus solder seconds depending mass board. peak temperature profile should between 225°C eutectic Sn/Pb solder. required, removal residual solder flux completed using recommended procedures forth flux manufacturer.
Final Solder Inspection
inspection solder joints commonly performed with X-ray inspection system. With this tool, locate defects such shorts between pads, open contacts, voids within solder well extraneous solder. addition searching defects, mounted device should rotated side inspect sides solder joints with X-ray inspection system. solder joints should have enough solder volume with proper stand-off height that "Hour Glass" shaped connection formed shown below Figure "Hour Glass" solder joints reliability concern must avoided.
Preferred Solder Joint
Figure Side view NIS3001 illustrating preferred undesirable solder joints. Rework Procedure
fact that NIS3001 leadless device, entire package must removed from board there issue with solder joints. important minimize chance overheating neighboring devices during removal package since devices typically close proximity with each other.
Undesirable "Hour Glass" Solder Joint
Standard rework systems recommended this procedure since airflow temperature gradients carefully controlled. also recommend that board placed oven 125°C hours prior heating parts remove excess moisture from packages. order control region, which will exposed reflow temperatures, board should heated 100°C conduction through backside board location NIS3001 Package. Typically, heating nozzles then used increase temperature locally. Once NIS3001's solder joints heated above their liquidus temperature, package quickly removed pads board cleaned. cleaning pads typically performed with blade-style conductive tool with de-soldering braid. clean flux used during this process order simplify procedure. Solder paste then deposited screened onto site preparation mounting device. close proximity neighboring packages most board configurations, miniature stencil individual component typically required. same stencil design that originally used mount package applied mini-stencil redressing pad. small configurations NIS3001, since pads underside package, manual pick place procedure without magnification recommended. dual image optical system where underside package aligned board should used instead. Reflowing component onto board accomplished either passing board through original reflow profile, selectively heating NIS3001 Package with same process that used remove benefit with subjecting entire board second reflow that packages will mounted consistently profile that already defined. disadvantage that other devices mounted with same solder type will reflowed second time. subjecting parts second either concern unacceptable specific application, than localized reflow option would recommended procedure.
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AND8121/D
Notes
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AND8121/D
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer.
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AND8121/D

INTRODUCTION Various Semiconductor components packaged advanced Quad F

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