16/32-bit microcontrollers with CAN, 10-bit external memory interface
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LPC2290
16/32-bit microcontrollers with CAN, 10-bit external memory interface
Rev. February 2004 Preliminary data
LPC2290 based 16/32 ARM7TDMI-SCPU with real-time emulation embedded trace support. critical code size applications, alternative 16-bit Thumb Mode reduces code more than with minimal performance penalty. With package, power consumption, various 32-bit timers, 8-channel 10-bit ADC, advanced channels, channels external interrupt pins this microcontroller particularly suitable automotive industrial control applications well medical systems fault-tolerant maintenance buses. LPC2290 provides GPIO depending configuration. With wide range additional serial communications interfaces, also suited communication gateways protocol converters well many other general-purpose applications.
Features
features
16/32-bit ARM7TDMI-S microcontroller LQFP144 package. on-chip Static RAM. Serial boot-loader using UART0 provides in-system download programming capabilities. EmbeddedICE-RT Embedded Trace interfaces offer real-time debugging with on-chip RealMonitor software well high speed real-time tracing instruction execution. interconnected interfaces with advanced acceptance filters. Additional serial interfaces include UARTs (16C550), Fast (400 kbits/s) SPIsTM. Eight channel 10-bit converter with conversion time 2.44 32-bit timers (with capture compare channels), unit outputs), Real Time Clock Watchdog. Vectored Interrupt Controller with configurable priorities vector addresses. Configurable external memory interface with four banks, each 8/16/32 data width. general purpose pins tolerant). edge/level sensitive external interrupt pins available.
Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
maximum clock available from programmable on-chip Phase-Locked Loop. On-chip crystal oscillator with operating range MHz. power modes, Idle Power-down. Processor wake-up from Power-down mode external interrupt. Individual enable/disable peripheral functions power optimization. Dual power supply: operating voltage range 1.65 1.95 (1.8 ±0.15 power supply range (3.3 ±10%) with tolerant pads.
Ordering information
Table Ordering information Package Name LPC2290FBD144 LQFP144 Description plastic profile quad flat package, leads, body Version SOT486-1 Type number
Ordering options
Table Part options Flash memory channels Temperature range (°C) Type number LPC2290FBD144
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Preliminary data
Rev. February 2004
Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
Block diagram
TRST(1) TMS(1) TCK(1) TDI(1) TDO(1)
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
system clock
SYSTEM FUNCTIONS
ARM7TDMI-S
BRIDGE ARM7 LOCAL
VECTORED INTERRUPT CONTROLLER
AMBA (Advanced High-performance Bus)
INTERNAL SRAM CONTROLLER
DECODER BRIDGE DIVIDER (VLSI peripheral bus) CS3:0* A23:0* BLS3:0* D31:0*
SRAM
EXTERNAL MEMORY CONTROLLER
EINT3:0
EXTERNAL INTERRUPTS
SERIAL INTERFACE
CAP0
SCK0,1 CAPTURE/ COMPARE TIMER SERIAL INTERFACES MOSI0,1 MISO0,1 SSEL0,1 TxD0,1 CONVERTER RxD0,1 UART
DSR1,CTS1, DCD1,
Ain3:0 Ain7:4
P0.30:0 P1.31:16, P2.31:0 P3.31:0 GENERAL PURPOSE TD2:1 RD2:1
PWM6:1
PWM0
WATCHDOG TIMER
REAL TIME CLOCK
SYSTEM CONTROL
*Shared with GPIO
002aaa796
When test/debug interface used, GPIO/other function sharing these pins available.
Block diagram.
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Preliminary data
Rev. February 2004
RESET
XTAL1
XTAL2
Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
Pinning information
Pinning
P0.19/MAT1.2/MOSI1/CAP1.2 P0.18/CAP1.3/MISO1/MAT1.3 P0.20/MAT1.3/SSEL1/EINT3
VSSA VSSA_PLL
P1.30/TMS
P1.27/TDO
P1.29/TCK
P2.21/D21
P2.20/D20
P2.19/D19
P2.18/D18
P2.17/D17
P2.16/D16
P2.15/D15
P2.14/D14
P2.13/D13
P2.12/D12
P2.11/D11
P2.10/D10
P1.28/TDI
P2.9/D9
P2.8/D8
P2.7/D7
P2.6/D6
P2.5/D5
handbook, full pagewidth
P2.4/D4
RESET
V18A XTAL1
XTAL2
P2.22/D22 P0.21/PWM5/CAP1.3 P0.22/CAP0.0/MAT0.0 P0.23/RD2 P1.19/TRACEPKT3 P0.24/TD2 P2.23/D23 P2.24/D24 P2.25/D25 P2.26/D26/BOOT0 P1.18/TRACEPKT2 P2.27/D27/BOOT1 P2.28/D28 P2.29/D29 P2.30/D30/AIN4 P2.31/D31/AIN5 P0.25/RD1 P0.27/AIN0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 P0.28/AIN1/CAP0.2/MAT0.2 P3.29/BLS2/AIN6 P3.28/BLS3/AIN7 P3.27/WE P3.26/CS1 P0.29/AIN2/CAP0.3/MAT0.3 P0.30/AIN3/EINT3/CAP0.0 P1.16/TRACEPKT0 P3.25/CS2 P3.24/CS3
P2.3/D3 P2.2/D2 P2.1/D1 P1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/RI1/EINT2 P2.0/D0 P3.30/BLS1 P3.31/BLS0 P1.21/PIPESTAT0 P0.14/DCD1/EINT1
LPC2290
P1.0/CS0 P1.1/OE P3.0/A0 P3.1/A1 P3.2/A2 P1.22/PIPESTAT1 P0.13/DTR1/MAT1.1 P0.12/DSR1/MAT1.0 P0.11/CTS1/CAP1.1 P1.23/PIPESTAT2 P3.3/A3 P3.4/A4 P0.10/RTS1/CAP1.0 P0.9/RxD1/PWM6/EINT3 P0.8/TxD1/PWM4 P3.5/A5 P3.6/A6
002aaa797
P0.1/RxD0/PWM3/EINT0
P0.2/SCL/CAP0.0
P0.4/SCK0/CAP0.1
P1.25/EXTIN0
P0.5/MISO0/MAT0.1
P3.13/A13
P3.12/A12
P3.11/A11
P3.10/A10
P0.6/MOSI0/CAP0.2
P0.7/SSEL0/PWM2/EINT2
P0.3/SDA/MAT0.0/EINT1
P1.24/TRACECLK
P3.23/A23/XCLK
P3.22/A22
P0.0/TxD0/PWM1
P1.31/TRST
P3.21/A21
P3.20/A20
P3.19/A19
P3.18/A18
P3.17/A17
P1.26/RTCK
P3.16/A16
P3.15/A15
P3.14/A14
P3.9/A9
P3.8/A8
LQFP144 pinning.
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Preliminary data
Rev. February 2004
P3.7/A7
Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
description
Table Symbol P0.0 P0.31 description Type Description Port Port 32-bit bi-directional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins port available. 83-85, 100, 101, 121-123, 4-6, P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10
P0.0
TxD0 Transmitter output UART0. PWM1 Pulse Width Modulator output RxD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input clock input/output. Open drain output (for compliance). CAP0.0 Capture input Timer0, channel data input/output. Open drain output (for compliance). MAT0.0 Match output Timer0, channel EINT1 External interrupt input. SCK0 Serial clock SPI0. clock output from master input slave. CAP0.1 Capture input Timer0, channel MISO0 Master Slave SPI0. Data input master data output from slave. MAT0.1 Match output Timer0, channel MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0.2 Capture input Timer0, channel SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. TxD1 Transmitter output UART1. PWM4 Pulse Width Modulator output RxD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. RTS1 Request Send output UART1. CAP1.0 Capture input Timer1, channel
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Preliminary data
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Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
Table Symbol P0.11 P0.12 P0.13 P0.14
description.continued Type Description CTS1 Clear Send input UART1. CAP1.1 Capture input Timer1, channel DSR1 Data Ready input UART1. MAT1.0 Match output Timer1, channel DTR1 Data Terminal Ready output UART1. MAT1.1 Match output Timer1, channel DCD1 Data Carrier Detect input UART1. EINT1 External interrupt input. Note: this while RESET forces on-chip boot-loader take over control part after reset.
P0.15 P0.16
Ring Indicator input UART1. EINT2 External interrupt input. EINT0 External interrupt input. MAT0.2 Match output Timer0, channel CAP0.2 Capture input Timer0, channel CAP1.2 Capture input Timer1, channel SCK1 Serial Clock SPI1. clock output from master input slave. MAT1.2 Match output Timer1, channel CAP1.3 Capture input Timer1, channel MISO1 Master Slave SPI1. Data input master data output from slave. MAT1.3 Match output Timer1, channel MAT1.2 Match output Timer1, channel MOSI1 Master Slave SPI1. Data output from master data input slave. CAP1.2 Capture input Timer1, channel MAT1.3 Match output Timer1, channel SSEL1 Slave Select SPI1. Selects interface slave. EINT3 External interrupt input. PWM5 Pulse Width Modulator output CAP1.3 Capture input TIMER1, channel CAP0.0 Capture input Timer0, channel MAT0.0 Match output Timer0, channel CAN2 receiver input. CAN2 transmitter output. CAN1 receiver input. AIN0 converter, input This analog input always connected pin. CAP0.1 Capture input Timer0, channel MAT0.1 Match output Timer0, channel
P0.17
P0.18
P0.19
P0.20
P0.21 P0.22 P0.23 P0.24 P0.25 P0.27
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Preliminary data
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LPC2290
16/32-bit microcontrollers with external memory interface
Table Symbol P0.28
description.continued Type Description AIN1 converter, input This analog input always connected pin. CAP0.2 Capture input Timer0, channel MAT0.2 Match output Timer0, channel AIN2 converter, input This analog input always connected pin. CAP0.3 Capture input Timer0, Channel MAT0.3 Match output Timer0, channel AIN3 converter, input This analog input always connected pin. EINT3 External interrupt input. CAP0.0 Capture input Timer0, channel Port Port 32-bit bi-directional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins through port available.
P0.29
P0.30
P1.0 P1.31
102, 144, 140, 126, 113,
P1.0 P1.1 P1.16 P1.17 P1.18 P1.19 P1.20
Low-active Chip Select signal. (Bank addresses range 8000 0000 80FF FFFF) Low-active Output Enable signal. TRACEPKT0 Trace Packet, Standard port with internal pull-up. TRACEPKT1 Trace Packet, Standard port with internal pull-up. TRACEPKT2 Trace Packet, Standard port with internal pull-up. TRACEPKT3 Trace Packet, Standard port with internal pull-up. TRACESYNC Trace Synchronization. Standard port with internal pull-up. Note: this while RESET LOW, enables pins P1.25:16 operate Trace port after reset.
P1.21 P1.22 P1.23 P1.24 P1.25 P1.26
PIPESTAT0 Pipeline Status, Standard port with internal pull-up. PIPESTAT1 Pipeline Status, Standard port with internal pull-up. PIPESTAT2 Pipeline Status, Standard port with internal pull-up. TRACECLK Trace Clock. Standard port with internal pull-up. EXTIN0 External Trigger Input. Standard with internal pull-up. RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bi-directional with internal pull-up. Note: this while RESET LOW, enables pins P1.31:26 operate Debug port after reset.
P1.27 P1.28 P1.29 P1.30 P1.31
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Test Data JTAG interface. Test Data JTAG interface. Test Clock JTAG interface. Test Mode Select JTAG interface. TRST Test Reset JTAG interface.
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Preliminary data
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Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
Table Symbol
description.continued Type Description Port Port 32-bit bi-directional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. 105, 106, 108, 109, 114-118, 120, 124, 125, 127, 129-134, 136, 137, 10-13, 16-20
P2.0 P2.31
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 P2.16 P2.17 P2.18 P2.19 P2.20 P2.21 P2.22 P2.23 P2.24 P2.25 P2.26
External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line BOOT0 While RESET low, together with BOOT1 controls booting internal operation. Internal pull-up ensures high state left unconnected.
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Preliminary data
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Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
Table Symbol P2.27
description.continued Type Description External memory data line BOOT1 While RESET low, together with BOOT0 controls booting internal operation. Internal pull-up ensures high state left unconnected. BOOT1:0=00 selects 8-bit memory boot. BOOT1:0=01 selects 16-bit memory boot. BOOT1:0=10 selects 32-bit memory boot. BOOT1:0=11 selects 16-bit memory boot.
P2.28 P2.29 P2.30
External memory data line External memory data line External memory data line AIN4 converter, input This analog input always connected pin. External memory data line AIN5 converter, input This analog input always connected pin. Port Port 32-bit bi-directional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block.
P2.31
P3.0 P3.31
89-87, 74-71, 66-62, 48-44, 30-27,
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 P3.16 P3.17 P3.18 P3.19
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External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line
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Preliminary data
Rev. February 2004
Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
Table Symbol P3.20 P3.21 P3.22 P3.23 P3.24 P3.25 P3.26 P3.27 P3.28
description.continued Type Description External memory address line External memory address line External memory address line External memory address line XCLK Clock output. Low-active Chip Select signal. (Bank addresses range 8300 0000 83FF FFFF) Low-active Chip Select 2signal. (Bank addresses range 8200 0000 82FF FFFF) Low-active Chip Select signal. (Bank addresses range 8100 0000 81FF FFFF) Low-active Write enable signal. BLS3 Low-active Byte Lane Select signal (Bank AIN7 converter, input This analog input always connected pin. BLS2 Low-active Byte Lane Select signal (Bank AIN6 converter, input This analog input always connected pin. BLS1 Low-active Byte Lane Select signal (Bank BLS0 Low-active Byte Lane Select signal (Bank TD1: CAN1 transmitter output. External Reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Ground: reference.
P3.29
P3.30 P3.31 RESET
XTAL1 XTAL2
103, 107, 111,
VSSA VSSA_PLL V18A
Analog Ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. Analog Ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. Core Power Supply: This power supply voltage internal circuitry. Analog Core Power Supply: This power supply voltage internal circuitry. This should nominally same voltage should isolated minimize noise error. Power Supply: This power supply voltage ports.
104, 112,
Analog Power Supply: This should nominally same voltage should isolated minimize noise error.
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LPC2290
16/32-bit microcontrollers with external memory interface
Functional description
Details LPC2290 systems peripheral functions described following sections.
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known THUMB, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind THUMB that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit THUMB set.
THUMB set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because THUMB code operates same 32-bit register code. THUMB code able provide code size ARM, 160% performance equivalent processor connected 16-bit memory system.
On-Chip static
On-Chip static used code and/or data storage. SRAM accessed 8-bits, 16-bits, 32-bits. LPC2290 provides static RAM.
Memory
LPC2290 memory maps incorporate several distinct regions, shown following figures. addition, interrupt vectors re-mapped allow them reside either on-chip boot-loader, external memory BANK0 on-chip static RAM. This described Section 6.20 "System control".
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LPC2290
16/32-bit microcontrollers with external memory interface
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF RESERVED ADDRESS SPACE
EXTERNAL MEMORY BANK3 EXTERNAL MEMORY BANK2 EXTERNAL MEMORY BANK1 EXTERNAL MEMORY BANK0 BOOT BLOCK (RE-MAPPED FROM ON-CHIP MEMORY
0x8400 0000 0x83FF FFFF 0x8300 0000 0x82FF FFFF 0x8200 0000 0x81FF FFFF 0x8100 0000 0x80FF FFFF 0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4001 0000 0x4000 3FFF KBYTE ON-CHIP STATIC 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0000 0000
002aaa798
LPC2290 memory map.
Interrupt controller
Vectored Interrupt Controller (VIC) accepts interrupt request inputs categorizes them FIQ, vectored IRQ, non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. Fast Interrupt reQuest (FIQ) highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt.
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LPC2290
16/32-bit microcontrollers with external memory interface
Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active. 6.4.1 Interrupt sources Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core Timer0 Timer1 UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only Embedded ICE, DbgCommRx Embedded ICE, DbgCommTx Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) UART1 Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) PWM0 SPI0 SPI1 Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) (state change) SPIF, MODF SPIF, MODF Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) channel
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LPC2290
16/32-bit microcontrollers with external memory interface
Interrupt sources.continued Flag(s) External Interrupt (EINT1) External Interrupt (EINT2) External Interrupt (EINT3) channel 20,21 22,23 24,25 26,27
Table Block
System Control External Interrupt (EINT0)
Converter ORed Acceptance Filter CAN1 int, int) CAN2 int, int) CAN3 int, int) LPC2294 only CAN4 int, int) LPC2294 only
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. Control Module contains three registers shown Table
Table Address 0xE002C000 0xE002C004 0xE002C014 Name PINSEL0 PINSEL1 PINSEL2 Description function select register function select register function select register Access Read/Write Read/Write Read/Write
function select register (PINSEL0 0xE002C000)
PINSEL0 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions, direction controlled automatically. Settings other than those shown Table reserved, should used
Table PINSEL0 function select register (PINSEL0 0xE002C000) name P0.0 Value P0.1 Function GPIO Port (UART0) PWM1 Reserved GPIO Port (UART0) PWM3 EINT0 Value after Reset
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LPC2290
16/32-bit microcontrollers with external memory interface
function select register (PINSEL0 0xE002C000).continued name P0.2 Value Function GPIO Port (I2C) Capture (Timer0) Reserved GPIO Port (I2C) Match (Timer0) EINT1 GPIO Port (SPI0) Capture (Timer0) Reserved GPIO Port MISO (SPI0) Match (Timer0) Reserved GPIO Port MOSI (SPI0) Capture (Timer0) Reserved GPIO Port SSEL (SPI0) PWM2 EINT2 GPIO Port UART1 PWM4 Reserved GPIO Port (UART1) PWM6 EINT3 GPIO Port 0.10 (UART1) Capture (Timer1) Reserved GPIO Port 0.11 (UART1) Capture (Timer1) Reserved Value after Reset
Table PINSEL0
P0.3
P0.4
11:10
P0.5
13:12
P0.6
15:14
P0.7
17:16
P0.8
19:18
P0.9
21:20
P0.10
23:22
P0.11
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LPC2290
16/32-bit microcontrollers with external memory interface
function select register (PINSEL0 0xE002C000).continued name P0.12 Value Function GPIO Port 0.12 (UART1) Match (Timer1) Reserved GPIO Port 0.13 (UART1) Match (Timer1) Reserved GPIO Port 0.14 (UART1) EINT1 Reserved GPIO Port 0.15 (UART1) EINT2 Reserved Value after Reset
Table PINSEL0 25:24
27:26
P0.13
29:28
P0.14
31:30
P0.15
Controller available LPC2294 only. Fields table related CAN4 have Reserved value LPC2290.
function select register (PINSEL1 0xE002C004)
PINSEL1 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown table reserved, should used.
Table PINSEL1 function select register (PINSEL1 0xE002C004) Name P0.16 Value P0.17 P0.18 Function GPIO Port 0.16 EINT0 Match (Timer0) Reserved GPIO Port 0.17 Capture (Timer1) (SPI1) Match (Timer1) GPIO Port 0.18 Capture (Timer1) MISO (SPI1) Match (Timer1) Value after Reset
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LPC2290
16/32-bit microcontrollers with external memory interface
function select register (PINSEL1 0xE002C004).continued Name P0.19 Value Function GPIO Port 0.19 Match (Timer1) MOSI (SPI1) Match (Timer1) GPIO Port 0.20 Match (Timer1) SSEL (SPI1) EINT3 GPIO Port 0.21 PWM5 Reserved Capture (Timer1) GPIO Port 0.22 Reserved Capture (Timer0) Match (Timer0) GPIO Port 0.23 (CAN Controller Reserved Reserved GPIO Port 0.24 (CAN Controller Reserved Reserved GPIO Port 0.25 (CAN Controller Reserved Reserved Reserved Reserved Reserved Reserved GPIO Port 0.27 AIN0 (A/D converter) Capture (Timer0) Match (Timer0) GPIO Port 0.28 AIN1 (A/D converter) Capture (Timer0) Match (Timer0)
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Table PINSEL1
Value after Reset
P0.20
11:10
P0.21
13:12
P0.22
15:14
P0.23
17:16
P0.24
19:18
P0.25
21:20
P0.26
23:22
P0.27
25:24
P0.28
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LPC2290
16/32-bit microcontrollers with external memory interface
function select register (PINSEL1 0xE002C004).continued Name P0.29 Value Function GPIO Port 0.29 AIN2 (A/D converter) Capture (Timer0) Match (Timer0) GPIO Port 0.30 AIN3 (A/D converter) EINT3 Capture (Timer0) Reserved Reserved Reserved Reserved Value after Reset
Table PINSEL1 27:26
29:28
P0.30
31:30
P0.31
function select register (PINSEL2 0xE002C014)
PINSEL2 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown table reserved, should used.
Table function select register (PINSEL2 0xE002C014) Description Reserved. When pins P1.36:26 used GPIO pins. When P1.31:26 used Debug port. When pins P1.25:16 used GPIO pins. When P1.25:16 used Trace port. Controls data strobe pins: Pins P2.7:0 P1.0 P1.1 P3.31 Pins P2.15:8 P3.30 Pins P2.27:16 Pins P2.29:28 Pins P2.31:30 Pins P3.29:28
9397 12874
PINSEL2 bits
Reset value P1.26/RTCK P1.20/ TRACESYNC BOOT1:0 D7:0 BLS0 D15:8 BLS1 D27:16 D29:28 D31:30 BLS2:3
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P2.7:0 P1.0 P1.1 P3.31 P2.15:8 P3.30 P2.27:16 P2.29:28 reserved P2.31:30 AIN5:4 P3.29:28 AIN6:7
bits controls P3.29: enables P3.29, enables AIN6. bits controls P3.28: enables P3.28, enables AIN7. Controls P3.27: enables P3.27, enables
Preliminary data
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Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
Table 10:9 15:14 17:16 19:18
function select register (PINSEL2 0xE002C014).continued Description Reserved. Controls P3.26: enables P3.26, enables CS1. Reserved. Reset value
PINSEL2 bits
bits 25:23 111, controls P3.23/A23/XCLK: enables P3.23, enables XCLK. Controls P3.25: enables P3.25, enables CS2, reserved values. Controls P3.24: enables P3.24, enables CS3, reserved values. Reserved. bits controls P2.29:28: enables P2.29:28, reserved bits controls P2.30: enables P2.30, enables AIN4. bits controls P2.31: enables P2.31, enables AIN5. Controls whether P3.0/A0 port address line (1). BOOT1:0=00 RESET=0, otherwise BOOT1 during Reset
27:25
Controls whether P3.1/A1 port address line (1).
Controls number pins among P3.23/A23/XCLK P3.22:2/A2.22:2 that BOOT1:0=11 address lines: Reset, otherwise None A11:2 address lines. A3:2 address lines. A5:2 address lines. A7:2 address lines. A15:2 address lines. A19:2 address lines. A23:2 address lines.
31:28
Reserved.
External memory controller
external Static Memory Controller module which provides interface between system external (off-chip) memory devices. provides support four independently configurable memory banks MBytes each with byte lane enable control) simultaneously. Each memory banks capable supporting SRAM, ROM, Flash EPROM, Burst memory, some external devices. Each memory bank bits wide.
6.10 General purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins.
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LPC2290
16/32-bit microcontrollers with external memory interface
6.10.1
Features
Direction control individual bits. Separate control output clear. default inputs after reset. 6.11 10-bit converter
LPC2290 contains single 10-bit successive approximation analog digital converter with eight multiplexed channels. 6.11.1 Features
Measurement range Capable performing more than 400,000 10-bit samples second. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal.
6.12 controllers acceptance filter
LPC2290 contains controllers. Controller Area network (CAN) serial communications protocol which efficiently supports distributed real-time control with very high level security. domain application ranges from high speed networks cost multiplex wiring. 6.12.1 Features
Data rates Mbit/s each bus. 32-bit register access. Compatible with specification 2.0B, 11898-1. Global Acceptance Filter recognizes 29-bit identifiers buses. Acceptance Filter provide FullCAN-style automatic reception selected Standard identifiers.
6.13 UARTs
LPC2290 contains UARTs. UART provides full modem control handshake interface, other provides only transmit receive data lines. 6.13.1 Features
byte Receive Transmit FIFOs. Register locations conform `550 industry standard. Receiver FIFO trigger points bytes Built-in baud rate generator. Standard modem interface signals included UART1.
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LPC2290
16/32-bit microcontrollers with external memory interface
6.14 serial controller
bi-directional inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g. driver transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. multi-master bus, controlled more than master connected implemented LPC2290 supports rate kbit/s (Fast I2C). 6.14.1 Features
Standard compliant interface. Easy configure Master, Slave, Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption
serial data bus.
Serial clock synchronization allows devices with different rates communicate
serial bus.
Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
used test diagnostic purposes. 6.15 serial controller
LPC2290 contains SPIs. full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master. 6.15.1 Features
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex, Communication. Combined master slave. Maximum data rate eighth input clock rate.
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16/32-bit microcontrollers with external memory interface
6.16 General purpose timers
Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them. 6.16.1 Features
32-bit Timer/Counter with programmable 32-bit Prescaler. Four 32-bit capture channels timer that take snapshot timer value
when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
6.17 Watchdog timer
purpose Watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, Watchdog will generate system reset user program fails `feed' reload) Watchdog within predetermined amount time. 6.17.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset Watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate Watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (tpclk (tpclk multiples
tpclk
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16/32-bit microcontrollers with external memory interface
6.18 Real time clock
Real Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode). 6.18.1 Features
Measures passage time maintain calendar clock. Ultra Power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Programmable Reference Clock Divider allows adjustment match
various crystal frequencies.
6.19 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2290. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge). 6.19.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
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match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs.
Single edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive
going negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 6.20 System control
6.20.1 Crystal oscillator oscillator supports crystals range MHz. oscillator output frequency called fosc processor clock frequency referred cclk purposes rate equations, etc. fosc cclk same value unless running connected. Refer Section 6.20.2 "PLL" additional information. 6.20.2 accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle.The turned bypassed following chip Reset enabled software. program must configure activate PLL, wait Lock, then connect clock source.
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LPC2290
16/32-bit microcontrollers with external memory interface
6.20.3
Reset wake-up timer Reset sources LPC2290: RESET Watchdog Reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip Reset source starts Wake-up Timer (see Wake-up Timer description below), causing internal chip reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed, on-chip circuitry completed initialization. When internal Reset removed, processor begins executing address which Reset vector. that point, processor peripheral registers have been initialized predetermined values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes Wake-up Timer. Wake-up Timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.20.4
External interrupt inputs LPC2290 includes nine edge level sensitive External Interrupt Inputs selectable functions. When pins combined, external events processed four independent interrupt signals. External Interrupt Inputs optionally used wake processor from Power-down mode.
6.20.5
Memory Mapping Control Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x00000000. Vectors mapped bottom BANK0 external memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.20.6
Power Control LPC2290 supports reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either Reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal
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LPC2290
16/32-bit microcontrollers with external memory interface
operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings. 6.20.7 Divider determines relationship between processor clock (cclk) clock used peripheral devices (PCLK). Divider serves purposes. first that cannot operate highest speeds CPU. order compensate this, slowed down half fourth processor clock rate. default condition reset quarter clock. second purpose Divider allow power savings when application does require peripherals full processor rate. Because Divider connected output, remains active running) during Idle mode.
6.21 Emulation debugging
LPC2290 supports emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself. 6.21.1 Embedded ICEStandard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access core. core Debug Communication Channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICElogic. 6.21.2 Embedded trace Since LPC2290 significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocell provides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software
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LPC2290
16/32-bit microcontrollers with external memory interface
debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction. 6.21.3 RealMonitorRealMonitor configurable software module, developed Inc., which enables real time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using (Debug Communications Channel), which present EmbeddedICE logic. LPC2290 contains specific configuration RealMonitor software programmed into on-chip memory.
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LPC2290
16/32-bit microcontrollers with external memory interface
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol Parameter AVIN Tstg Supply voltage, internal rail Supply voltage, external rail Analog supply voltage Analog input voltage related pins input voltage, tolerant pins[3][4] input voltage, other pins[2][3] supply current supply pin[5] ground current ground Storage temperature[6] pin[5] Conditions -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 +2.5 +3.6 Unit
Power dissipation (based package heat transfer, device power consumption)
following applies Limiting values: Stresses above those listed under Limiting values cause permanent damage device. This stress rating only functional operation device these conditions other than those described Section "Static characteristics" Section "Dynamic characteristics" this specification implied. This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. exceed Including voltage outputs 3-state mode. Only valid when supply voltage present. peak current limited times corresponding maximum current. Dependent package type.
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Preliminary data
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LPC2290
16/32-bit microcontrollers with external memory interface
Static characteristics
Table Static characteristics Tamb commercial, unless otherwise specified. Symbol Parameter Supply voltage External rail supply voltage Analog supply voltage level input current, pull-up High level input current, pull down 3-state output leakage, pull-up/down latch-up current Input voltage[3][4][5] Output voltage, output active High level input voltage level input voltage Hysteresis voltage High level output level output voltage[6] voltage[6] V[8] V[8] cclk MHz, Tamb code while(1){} executed from FLASH, active peripherals Power-down Mode Tamb Tamb Tamb +105 10/25[9] 50/110[9] 200[9] -(0.5 (1.5 Vhys Conditions 1.65 Typ[1] 1.95 Unit
Standard Port pins, RESET, RTCK Ilatchup
High level output current[6] level output current[6] High level short circuit current[7] level short circuit current[7] Pull-down current Pull-up current (applies P1.16 P1.25) Active Mode
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LPC2290
16/32-bit microcontrollers with external memory interface
Table Static characteristics.continued Tamb commercial, unless otherwise specified. Symbol Parameter RPDB Pull-down boot resistor BOOT1:0 pins system configuration selection Conditions unloaded data lines and/or data lines and/or loaded with external memory and/or memory mapped I/Os leaking total additional current Ilkgt pins Vhys Ilkg High level input voltage level input voltage Hysteresis voltage level output voltage[6] Input leakage VTOL from VTOL from VTOL from Oscillator pins input Voltages output Voltages
Typ[1]
Unit
0.7V -70µA lkgt
VTOL
VTOL
VTOL
Typical ratings guaranteed. values listed room temperature (+25 °C), nominal supply voltages. capacitance characterized tested. Including voltage outputs 3-state mode. supply voltages must present. 3-state outputs into 3-state mode when grounded. Accounts voltage drop supply lines. Only allowed short time period. Minimum condition maximum condition LPC2294 only.
Table converter electrical characteristics unless otherwise specified; Tamb unless otherwise specified; converter frequency MHz. Symbol AVIN
Parameter Analog input voltage Analog input capacitance Differential Offset Gain non-linearity[1][2][3] Integral non-linearity[1][4] error[1][5] error[1][7] error[1][6]
±0.5
Unit
Absolute
Conditions: VSSA monotonic, there missing codes. differential non-linearity (DLe) difference between actual step width ideal step width. Figure integral no-linearity (ILe) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure
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Preliminary data
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Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
offset error (OSe) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (Ge) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute voltage error (Ae) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
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Preliminary data
Rev. February 2004
Philips Semiconductors
LPC2290
16/32-bit microcontrollers with external memory interface
offset error 1023
gain error
1022
1021
1020
1019
1018
Code
(ideal) 1018 1019 1020 1021 1022 1023 1024
AVIN (LSBideal) offset error
VSSA 1024
002aaa668
Example actual transfer curve. ideal transfer curve. Differential non-linearity (DLe). Integral non-linearity (ILe). Center step actual transfer curve.
conversion characteristics.
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LPC2290
16/32-bit microcontrollers with external memory interface
Dynamic characteristics
Table Characteristics Tamb commercial, industrial, V18, over specified ranges[1] Symbol External Clock fosc Oscillator frequency supplied external oscillator (signal generator) External clock frequency supplied external crystal oscillator External clock frequency on-chip used External clock frequency on-chip boot-loader used initial code download tCHCX tCLCX tCLCH tCHCL Port Pins tRISE tFALL pins Output fall time from Cb[2] Port output rise time (except P0.2, P0.3) Port output fall time (except P0.2, P0.3) External oscillator clock period Clock high time Clock time Clock rise time Clock fall time Parameter Conditions Typ[1] Unit
1000
Parameters valid over operating temperature range unless otherwise specified. capacitance from
Table Symbol tCHAVR tCHCSL tCHCSH tCHANV tCSLAV tOELAVR tCSLOEL tAVDV
External memory interface characteristics. Tamb Description XCLK HIGH Address Valid XCLK HIGH XCLK HIGH HIGH XCLK HIGH Address Invalid Address Valid Address Valid Memory Access Time (latest Address Valid, LOW, Data Valid) -5[1] -5[1] Unit
Common Read Write Cycles
Read Cycle Parameters
(tCYC*(2 WST1)) (-20)
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16/32-bit microcontrollers with external memory interface
Table Symbol tAVDV
External memory interface characteristics. Tamb °C.continued Description Burst-ROM Initial Memory Access Time (latest Address Valid, LOW, Data Valid) Unit (tCYC*(2 WST1)) (-20)
tAVDV tSTHDNV tCSHOEH tOEHANV tCHOEL tCHOEH tAVCSLW tCSLDVW tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tWELWEH tWEHANV tWEHDNV tBLSHANV tBLSHDNV tCHDV tCHWEL tCHHBLSL tAVCSL tAVCSL tAVCSL
Burst-ROM Subsequent Memory Access tCYC (-20) Time (Address Valid Data Valid) Data Hold Time (earliest HIGH, HIGH, Address Change Data Invalid) HIGH HIGH HIGH Address Invalid XCLK HIGH XCLK HIGH HIGH Address Valid Data Valid Data Valid Data Valid HIGH HIGH HIGH Address Invalid HIGH Data Invalid HIGH Address Invalid HIGH Data Invalid XCLK HIGH Data Valid XCLK HIGH XCLK HIGH XCLK HIGH HIGH XCLK HIGH HIGH XCLK HIGH Data Invalid tCYC tCYC WST2) tCYC WST2) tCYC-5 tCYC)-5 tCYC-5 tCYC)-5
tCYC*(1 WST2) tCYC*(1 WST2) tCYC tCYC) tCYC tCYC)
Write Cycle Parameters
Except initial access, which case address tCYC earlier.
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16/32-bit microcontrollers with external memory interface
Table
Standard read access specifications frequency setting round integer Memory access time requirement 20ns WRITE INIT 20ns 20ns
Access cycle
Standard read
20ns WRITE INIT 20ns 20ns
20ns WRITE INIT 20ns
Standard write
Burst read initial
Burst read subsequent
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LPC2290
16/32-bit microcontrollers with external memory interface
Timing
0.45
tCHCX
tCHCL
tCLCX
tCLCH
002aaa416
External clock timing.
XCLK CLSAV CSHOEH
Addr Data AVDV STHDNV
CSLOEL OELAVR CHOEL OEHANV CHOEH
002aaa749
External memory read access.
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XCLK
AVCSLW
CSLDVW WELWEH WEHANV BLSHANV
BLS/WE
CSLWEL
BLSLBLSH WELDV
CSLBLSL
Addr Data CSLDV WEHDNV
BLSHDNV
002aaa750
External memory write access.
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Package outline
LQFP144: plastic profile quad flat package; leads; body SOT486-1
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.75 0.45 0.08 0.08 D(1) E(1)
22.15 22.15 21.85 21.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT486-1 REFERENCES 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-14 03-02-20
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Revision history
Table Date 20040209 Revision history CPCN Description Preliminary data (9397 12874)
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16/32-bit microcontrollers with external memory interface
Data sheet status
Level Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys licence title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Licenses
Purchase Philips components Purchase Philips components conveys license under Philips' patent components system provided system conforms specification defined Philips. This specification ordered using code 9398 40011.
Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application.
Trademarks
RealMonitor trademark ARM, Inc. EmbeddedICE trademark ARM, Inc. ARM7TDMI-S trademark ARM, Inc. trademark Motorola, Inc.
Contact information
additional information, please visit sales office addresses, send e-mail
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16/32-bit microcontrollers with external memory interface
Contents
6.4.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.18 6.18.1 6.19 6.19.1 6.20 6.20.1 6.20.2 6.20.3 6.20.4 6.20.5 General description Features features Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-Chip static Memory map. Interrupt controller Interrupt sources. connect block function select register (PINSEL0 0xE002C000). function select register (PINSEL1 0xE002C004). function select register (PINSEL2 0xE002C014). External memory controller. General purpose parallel I/O. Features 10-bit converter Features controllers acceptance filter Features UARTs Features serial controller Features serial controller. Features General purpose timers Features Watchdog timer. Features Real time clock Features Pulse width modulator Features System control Crystal oscillator Reset wake-up timer External interrupt inputs Memory Mapping Control 6.20.6 6.20.7 6.21 6.21.1 6.21.2 6.21.3 Power Control. Emulation debugging. Embedded ICE. Embedded trace. RealMonitor. Limiting values Static characteristics Dynamic characteristics Timing Package outline Revision history Data sheet status. Definitions Disclaimers Licenses Trademarks
Koninklijke Philips Electronics N.V. 2004. Printed U.S.A.
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights. Date release: February 2004 Document order number: 9397 12874
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