VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR differential 3.3V LVPEC
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ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
differential 3.3V LVPECL outputs Selectable differential CLK0, nCLK0 LVCMOS/LVTTL CLK1 inputs CLK0, nCLK0 supports following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL CLK1 accepts following input levels: LVCMOS LVTTL Maximum output frequency: 350MHz range: 250MHz 700MHz External feedback "zero delay" clock regeneration with configurable frequencies Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum) CLK1, 80ps (maximum) Output skew: 150ps (maximum) Static phase offset: -150ps 150ps Industrial temperature information available upon request
GENERAL DESCRIPTION
ICS8732-01 voltage, skew, 3.3V LVPECL Clock Generator member HiPerClockSthe HiPerClockSfamily High Performance Clock Solutions from ICS. ICS8732-01 selectable clock inputs. CLK0, nCLK0 pair accept most standard differential input levels. single ended clock input accepts LVCMOS LVTTL input levels. ICS8732-01 fully integrated along with frequency configurable outputs. external feedback input outputs regenerate clocks with "zero delay".
ICS8732-01 multiple divide select pins each bank outputs along with independent feedback divide select pins allowing ICS8732-01 function both frequency multiplier divider. PLL_SEL input used bypass test system debug purposes. bypass mode, input clock routed around into internal output dividers.
BLOCK DIAGRAM
CLK_SEL CLK0 nCLK0 CLK1 FB_IN nFB_IN
ASSIGNMENT
FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 nFB_IN nQFB0 nQFB1 FB_IN QFB0 QFB1 VCCO
nQA0 nQA1 nQA2 nQA3
nQB0 nQB1 nQB2 nQB3
VCCO nQA0 nQA1 PLL_SEL VCCO nQA2 nQA3
VCCO nQB3 nQB2 VCCO nQB1 nQB0
PLL_SEL
DIV_SELA0 DIV_SELA1 DIV_SELB0 DIV_SELB1 FBDIV_SEL0 FBDIV_SEL1 FBDIV_SEL2
ICS8732-01
DIV_SELA1 DIV_SELA0 CLK1 nCLK0 CLK0 CLK_SEL VCCA DIV_SELB1 DIV_SELB0
QFB0 nQFB0 QFB1 nQFB1
52-Lead LQFP 10mm 10mm 1.4mm package body package View
8732AY-01
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
Type Description Output supply pins. Differential output pair. LVPECL interface levels.
TABLE DESCRIPTIONS
Number Name VCCO QA0, nQA0, QA1, nQA1
Power Output
Power
Negative supply pins. Selects between reference clock input dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS LVTTL interface levels. Differential output pairs. LVPECL interface levels. Determines output divider valued Table LVCMOS LVTTL interface levels. Determines output divider valued Table Pulldown LVCMOS LVTTL interface levels. Pulldown Core supply pins. Pulldown LVCMOS LVTTL reference clock input. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0. Pulldown When HIGH, selects CLK1. LVCMOS LVTTL interface levels. Analog supply pin. connect. Determines output divider valued Table Pulldown LVCMOS LVTTL interface levels. Determines output divider valued Table Pulldown LVCMOS LVTTL interface levels. Differential output pairs. LVPECL interface levels. Active High Master Reset. When logic HIGH, internal dividers reset causing true outputs inver outputs Pulldown high. When LOW, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Differential output pairs. LVPECL interface levels. Differential feedback output pairs. LVPECL interface levels. Feedback input phase detector regenerating clocks with "zero delay". Feedback input phase detector regenerating clocks Pullup with "zero delay". Selects divide value differential feedback output pairs. Pulldown LVCMOS LVTTL interface levels. Selects divide value differential feedback output pairs. Pulldown LVCMOS LVTTL interface levels. Selects divide value differential feedback output pairs. Pulldown LVCMOS LVTTL interface levels. Pulldown
PLL_SEL QA2, nQA2, QA3, nQA3 DIV_SELA1 DIV_SELA0 CLK1 nCLK0 CLK0 CLK_SEL VCCA DIV_SELB1 DIV_SELB0 QB0, nQB0, QB1, nQB1 QB2, nQB2, QB3, nQB3 QFB1, nQFB1, QFB0, nQFB0 FB_IN nFB_IN FBDIV_SEL0 FBDIV_SEL1 FBDIV_SEL2
Input Output Input Input Power Input Input Input Input Power Unused Input Input Output
Pullup
Input
Output Output Input Input Input Input Input
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
8732AY-01
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
Test Conditions Minimum Typical Maximum Units
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
TABLE CONTROL INPUT FUNCTION TABLE
Inputs PLL_SEL DIV_SELA1
QA0:QA3 OUTPUTS
Outputs QA0:QA3, nQA0:nQA3 fVCO/2 fVCO/4 fVCO/6 fVCO/8 fREF_CLK/2 fREF_CLK/4 fREF_CLK/6 fREF_CLK/8
DIV_SELA0
TABLE CONTROL INPUT FUNCTION TABLE
Inputs PLL_SEL DIV_SELB1
QB0:QB3 OUTPUTS
Outputs QB0:QB3, nQB0:nQB3 fVCO/2 fVCO/4 fVCO/8 fVCO/12 fREF_CLK/2 fREF_CLK/4 fREF_CLK/8 fREF_CLK/12
DIV_SELB0
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REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
TABLE CONTROL INPUT FUNCTION TABLE
Inputs PLL_SEL FBDIV_SEL2
QFB0, QFB1
Outputs QFB0, QFB1 nQFB0, nQFB1 fVCO/4 fVCO/6 fVCO/8 fVCO/10 fVCO/8 fVCO/12 fVCO/16 fVCO/20 fREF_CLK/4 fREF_CLK/6 fREF_CLK/8 fREF_CLK/10 fREF_CLK/8 fREF_CLK/12 fREF_CLK/16 fREF_CLK/20
FBDIV_SEL1
FBDIV_SEL0
TABLE OUTPUT FREQUENCY W/FB_IN QFB0
QFB1
fVCO CLK1 (MHz) Minimum 62.5 41.67 31.25 31.25 20.83 15.62 Maximum (NOTE 116.67 87.5 87.5 58.33 43.75
Inputs FB_IN FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 Output Divider Mode
(NOTE fREF_CLK fREF_CLK fREF_CLK fREF_CLK fREF_CLK fREF_CLK fREF_CLK fREF_CLK
12.5 NOTE frequency range 250MHz 700MHz. NOTE maximum input frequency that phase detector accept 175MHz.
8732AY-01
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V 50mA 100mA 42.3°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter VCCA VCCO ICCA Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current; NOTE Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
NOTE This parameter included Power Supply Current (IEE) value.
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage CLK1 CLK_SEL, PLL_SEL, DIV_SELAx, DIV_SELBx, FBDIV_SELx, CLK1 CLK_SEL, PLL_SEL, DIV_SELAx, DIV_SELBx, FBDIV_SELx, CLK_SEL, CLK1 DIV_SELAx, DIV_SELBx, FBDIV_SELx PLL_SEL CLK_SEL, CLK1 DIV_SELAx, DIV_SELBx, FBDIV_SELx PLL_SEL Test Conditions Minimum -0.3 -0.3 Typical Maximum VCC+ VCC+ Units
Input Voltage
Input High Current
3.465V 3.465V 3.465V, 3.465V, -150
Input Current
8732AY-01
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
Test Conditions CLK0, FB_IN nCLK0, nFB_IN CLK0, FB_IN nCLK0, nFB_IN 3.465V 3.465V 3.465V, 3.465V, -150 0.15 0.85 Minimum Typical Maximum Units
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCMR Parameter Input High Current Input Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE
NOTE single ended applications, maximum input voltage FB_IN, nFB_IN 0.3V. NOTE Common mode voltage defined VIH.
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
NOTE Outputs terminated with VCCO
TABLE INPUT REFERENCE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol fREF Parameter Input Reference Frequency Test Conditions Minimum Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol fMAX Parameter Output Frequency Static Phase Offset; NOTE Output Skew; NOTE CLK0, Cycle-to-Cycle Jitter nCLK NOTE CLK1 Test Conditions PLL_SEL 3.3V, fREF 100MHz, fVCO 400MHz Minimum Typical Maximum signal Units
tsk(o) tjit(cc)
-150
Lock Time Output Rise/Fall Time Output Duty Cycle fOUT 175MHz parameters measured fMAX unless noted otherwise. NOTE Defined time difference between input reference clock averaged feedback input when locked input reference frequency stable. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard NOTE outputs divide configuration.
8732AY-01
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCCA, VCCO
SCOPE
nCLK0, nFB_IN
LVPECL
CLK0, FB_IN
Cross Points
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQA0:nQA3, nQB0:nQB3, nQFB0, nQFB1 QA0:QA3, QB0:QB3, QFB0, QFB1
tcycle
jit(cc) tcycle -tcycle
sk(o)
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nCLK0 CLK0, CLK1 nFB_IN FB_IN
Clock Outputs
STATIC PHASE OFFSET
nQA:nQA3, nQFB0, nQFB1 QA:QA3, QFB0, QFB1
OUTPUT RISE/FALL TIME
Pulse Width
PERIOD
PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8732AY-01
tcycle
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VCC/2 generated bias resistors This bias circuit should located close possible input pin. ratio
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Single Ended Clock Input V_REF nCLK 0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
LVPECL OUTPUTS
drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
3.3V
FOUT
((VOH VOL) (VCC
FOUT
FIGURE LVPECL OUTPUT TERMINATION
8732AY-01
FIGURE LVPECL OUTPUT TERMINATION
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8732-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VCCA should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
3.3V .01µF VCCA .01µF 10µF
FIGURE POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested here examples only. Please consult with vendor
driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
3.3V 3.3V
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V
3.3V
LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
8732AY-01
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
pacitors should physically located near power pin. ICS8732-01, unused outputs left floating.
LAYOUT GUIDELINE
Figure shows schematic example ICS8732-01. this example, CLK0/nCLK0 input selected. decoupling
VCCA
10uF
DIV_SELA1 DIV_SELA0
nQA3 nQA2 VCCO PLL_SEL nQA1 nQA0 VCCO
0.1uF
ICS8732-01
LVPECL
DIV_SELB1 DIV_SELB0
DIV_SELA1 DIV_SELA0 CLK1 nCLK0 CLK0 CLK_SEL VCCA DIV_SELB1 DIV_SELB0
FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 nFB_IN FB_IN nQFB0 QFB0 nQFB1 QFB1 VCCO
FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0
nQB0 nQB1 VCCO nQB2 nQB3 VCCO
Logic Input Examples
Logic Input
Logic Input
VCC=3.3V
Spare (i.e. intstalled)
(U1-1)
Logic Input pins
Logic Input pins
(U1-8)
(U1-16)
(U1-26)
(U1-32)
(U1-39)
(U1-40)
(U1-46)
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Bypass capacitors located near power pins
FIGURE ICS8732-01 LVPECL BUFFER SCHEMATIC EXAMPLE
8732AY-01
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8732-01. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8732-01 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 165mA 572mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 302mW
Total Power_MAX (3.465V, with outputs switching) 572mW 302mW 874mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 36.4°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.874W 36.4°C/W 102°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
Table Thermal Resistance 52-pin LQFP, Forced Convection
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
8732AY-01
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
1.0V
OH_MAX
1.0V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 1V)/50] 20.0mW ))/R
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
8732AY-01
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8732-01 4916
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REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.22 0.09 MINIMUM NOMINAL -1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC -0.75 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
8732AY-01
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
TABLE ORDERING INFORMATION
Part/Order Number ICS8732AY-01 ICS8732AY-01T Marking ICS8732AY-01 ICS8732AY-01T Package Lead LQFP Lead LQFP Tape Reel Count tray Temperature 70°C 70°C
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8732AY-01
REV. OCTOBER 2004
ICS8732-01
VOLTAGE, SKEW 3.3V LVPECL CLOCK GENERATOR
REVISION HISTORY SHEET Description Change Features Section changed min. from 200MHz 250MHz. Characteristics Table changed from max. typical 4pF. Output Frequency Table changed CLK1 min. column correlate with change. Absolute Maximum Ratings changed included Continuous Current Surge Current Added Differential Clock Input Interface Application Information section. Power Supply Characteristics Table changed from 240mA max. 165mA max., ICCA from 14mA max. 15mA max. Power Considerations recalculated Power Dissipation Junction Temperatures correspond with Table Updated LVPECL Output Termination diagrams. Added Schematic Layout. Block Diagram changed REF_SEL CLK_SEL. Ordering Information Table corrected Tape Reel Count read from 1000. Output Frequency Table changed NOTE from "200MHz" "175MHz". 5/20/03 Date
Table
Page
6/23/03
9/24/03 3/3/04 4/29/04 10/19/04
8732AY-01
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