PAL22V10 Family, AmPAL22V10/A 24-Pin Versatile Device DISTIN

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PAL22V10 Family, AmPAL22V10/A 24-Pin Versatile Device DISTIN

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COM'L: -7/10/15
PAL22V10 Family, AmPAL22V10/A
24-Pin Versatile Device
DISTINCTIVE CHARACTERISTICS
fast 7.5-ns propagation delay fMAX (external) Macrocells programmable registered combinatorial, active high active match application needs Varied product term distribution allows product terms output complex functions
Advanced Micro Devices
Global asynchronous reset synchronous preset initialization Power-up reset initialization register preload testability Extensive third-party software programmer support through FusionPLD partners 24-Pin SKINNYDIP, 24-pin Flatpack 28-pin PLCC packages save space
GENERAL DESCRIPTION
PAL22V10 provides user-programmable logic replacing conventional SSI/MSI gates flip-flops reduced chip count. PAL22V10 device implements familiar Boolean logic transfer function, products. device programmable array driving fixed array. array programmed create custom product terms, while array sums selected terms outputs. product terms connected fixed array with varied distribution from across outputs (see Block Diagram). products feeds output macrocell. Each macrocell programmed registered combinatorial, active high active low. output configuration determined fuses controlling multiplexers each macrocell. AMD's FusionPLD program allows PAL22V10 designs implemented using wide variety popular industry-standard design tools. working closely with FusionPLD partners, certifies that tools provide accurate, quality support. ensuring that thirdparty tools available, costs lowered because designer does have complete tools each device. FusionPLD program also greatly reduces design time since designer tool that already installed familiar.
BLOCK DIAGRAM
CLK/I0
Programmable Array 132)
RESET OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL PRESET
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
16559C-1
Publication# 16559 Rev. Issue Date: February 1996
Amendment
2-197
CONNECTION DIAGRAMS View SKINNYDIP/FLATPACK
CLK/I0 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
16559C-2
PLCC/LCC
CLK/I0 I/O9 I/O8
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2
I/O0 I/O1
16559C-3
Note: marked orientation.
DESIGNATIONS
Clock Input Input/Output Connect Supply Voltage Ground
2-198
PAL22V10 Family
ORDERING INFORMATION Commercial Products
programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE AmPAL Programmable Array Logic NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER OUTPUTS SPEED
OPTIONAL PROCESSING Blank Standard Processing OPERATING CONDITIONS Commercial (0°C +75°C) PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028)
Valid Combinations PAL22V10-7 PAL22V10-10 PAL22V10-15 AmPAL22V10A
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
PAL22V10-7/10/15, AmPAL22V10A (Com'l)
2-199
FUNCTIONAL DESCRIPTION
PAL22V10 allows systems engineer implement design on-chip, opening fuse links configure gates within device, according desired logic function. Complex interconnections between gates, which previously required timeconsuming layout, lifted from board placed silicon, where they easily modified during prototyping production. Product terms with fuses opened assume logical HIGH state; product terms connected both true complement single input assume logical state. PAL22V10 inputs macrocells. macrocell (Figure allows four potential output configurations; registered output combinatorial I/O, active high active (see Figure configuration choice made according user's design
specification corresponding programming configuration bits Multiplexer controls initially connected ground through programmable fuse, selecting path through multiplexer. Programming fuse disconnects control line from driven high level, selecting path. device produced with fuse link each input gate array, connections selectively removed applying appropriate voltages circuit.
Variable Input/Output Ratio
PAL22V10 twelve dedicated input lines, each macrocell output pin. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Unused input pins should tied GND.
Output Configuration Registered/Active Registered/Active High Combinatorial/Active Combinatorial/Active High I/On
Unprogrammed fuse Programmed fuse
16559C-4
Figure Output Logic Macrocell Diagram
2-200
PAL22V10 Family
Registered Output Configuration
Each macrocell PAL22V10 includes D-type flipflop data storage synchronization. flip-flop loaded LOW-to-HIGH transition clock input. registered configuration array feedback from flip-flop.
Combinatorial Configuration
macrocell configured combinatorial selecting multiplexer path that bypasses flip-flop combinatorial configuration feedback from pin.
Registered/Active
Combinatorial/Active
Registered/Active High
Combinatorial/Active High
16559C-5
Figure Macrocell Configuration Options
Programmable Three-State Outputs
Each output three-state output buffer with threestate control. product term controls buffer, allowing enable disable function product device inputs output feedback. combinatorial output provides bidirectional pin, configured dedicated input buffer always disabled.
Preset/Reset
initialization, PAL22V10 Preset Reset product terms. These terms connected registered outputs. When Synchronous Preset (SP) product term asserted high, output registers will loaded with HIGH next LOW-to-HIGH clock transition. When Asynchronous Reset (AR) product term asserted high, output registers will immediately loaded with independent clock. Note that preset reset control flip-flop, output pin. output level determined output polarity selected.
Programmable Output Polarity
polarity each macrocell output active high active low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection controlled programmable output macrocell, affects both registered combinatorial outputs. Selection automatic, based design specification definitions.
Power-Up Reset
flip-flops power-up logic predictable system initialization. Outputs PAL22V10 will depend programmed output polarity. rise must monotonic reset delay time 1000 maximum.
PAL22V10 Family
2-201
Register Preload
register PAL22V10 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Quality Testability
PAL22V10 offers very high level built-in quality. Extra programmable fuses, test words test columns provide means verifying performance parameters. addition, this verifies complete programmability functionality device provide highest programming yields post-programming functional yields industry.
Technology
AmPAL22V10A fabricated with AMD's diffusionisolated bipolar process. array connections formed with highly reliable PtSi fuse. PAL22V10-15, fabricated with AMD's diffusion-isolated bipolar process. This process reduces parasitic capacitances minimum geometries provide higher performance. array connections formed with PtSi fuses -15, fuses reliable operation.
Security Fuse
After programming verification, PAL22V10 design secured programming security fuse. Once programmed, this fuse defeats readback internal programmed pattern device programmer, securing proprietary designs from competitors. When security fuse programmed, array will read every fuse programmed, preload will disabled.
Programming
PAL22V10 programmed standard logic programmers. Approved programmers listed this data book.
2-202
PAL22V10 Family
LOGIC DIAGRAM SKINNYDIP (PLCC/LCC) Pinouts
CLK/I
(28)
(27)
(26)
(25)
(24)
(23)
(21)
(20)
(19)
(10)
(18)
(11)
(17)
(12) (13)
(16)
(14)
16559C-6
PAL22V10 Family
2-203
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -1.2 Output Voltage -0.5
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Clamp Voltage Input HIGH Current Input Current Maximum Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -1.2 Input -100 -150 -100 -130 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note (Note (Note VOUT (Note VOUT (Note VOUT (Note Outputs Open (IOUT
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-204
PAL22V10-7 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tSKEWR tARW tARR tSPR Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Skew Between Registered Outputs (Note Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) (Note Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. Output delay minimums measured under best-case conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Skew measured with outputs switching same direction. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PAL22V10-7 (Com'l)
2-205
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -1.2 Output Voltage -0.5
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Clamp Voltage Input HIGH Current Input Current Maximum Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -1.2 Input -100 -150 -100 -130 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note (Note (Note VOUT (Note VOUT (Note VOUT (Note Outputs Open (IOUT
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-206
PAL22V10-10 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR Clock Width Parameter Description Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) (Note Unit
fMAX
Maximum Frequency (Note
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. Output delay minimums measured under best-case conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PAL22V10-10 (Com'l)
2-207
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Input Current Output Voltage -0.5 Static Discharge Voltage 2001
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Clamp Voltage Input HIGH Current Input Current Maximum Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -1.2 -100 -100 -130 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note (Note (Note VOUT (Note VOUT (Note VOUT (Note Outputs Open (IOUT
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-208
PAL22V10-15 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) (Note Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. Output delay minimums measured under best-case conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PAL22V10-15 (Com'l)
2-209
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 +5.5 Input Current Output Voltage -0.5
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Clamp Voltage Input HIGH Current Input Current Maximum Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -1.2 -100 -100 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note (Note (Note VOUT (Note VOUT (Note VOUT (Note Outputs Open (IOUT
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-210
AmPAL22V10A (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR fMAX Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width HIGH External Feedback 1/(tS tCO) 28.5 Unit
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected.
AmPAL22V10A (Com'l)
2-211
SWITCHING WAVEFORMS
Input Feedback Input Feedback Combinatorial Output
16559C-7
Clock
Registered Output
16559C-8
Combinatorial Output
Registered Output
Input Feedback Clock
16559C-9
0.5V 0.5V
16559C-10
Output
Clock Width
Input Output Disable/Enable
Input Asserting Asynchronous Reset
tARW
Input Asserting Synchronous Preset
tSPR
Registered Output
tARR
Clock
Clock
16559C-11
Registered Output
16559C-12
Asynchronous Reset
Synchronous Preset
Notes: Input pulse amplitude Input rise fall times typical.
2-212
PAL22V10 Family
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
16559C-13
Commercial Specification tPD, Closed Open Closed Open Closed except
Measured Output Value
PAL22V10 Family
2-213
MEASURED SWITCHING CHARACTERISTICS PAL22V10-10
4.75 75°C (Note
tPD,
Number Outputs Switching
Number Outputs Switching
16559C-14
tPD,
Load Capacitance
16559C-15
Note: These parameters 100% tested, evaluated initial characterization time design modified where affected.
2-214
PAL22V10-10
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Input
Program/Verify Circuitry
16559C-16
Typical Input
Output
Input, Pins
Program/Verify/ Test Circuitry Preload Circuitry
16559C-17
Typical Output
PAL22V10 Family
2-215
POWER-UP RESET
power-up reset feature ensures that flip-flops will reset after device been powered output state will depend programmed pattern. This feature valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset wide range ways
Parameter Symbol Parameter Description Power-up Reset Time Input Feedback Setup Time Clock Width
rise steady state, conditions required ensure valid power-up reset. These conditions are:
rise must monotonic. Following reset, clock input must driven
from HIGH until applicable input feedback setup times met.
1000
Unit Switching Characteristics
Power
Registered Active-Low Output
Clock
16559C-18
Power-Up Reset Waveform
2-216
PAL22V10 Family

PAL22V10 Family, AmPAL22V10/A 24-Pin Versatile Device DISTIN

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