CMOS Parallel FIFO M67201A/202A implement first-in first-out algo

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CMOS Parallel FIFO M67201A/202A implement first-in first-out algo

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M67201A/M67202A
CMOS Parallel FIFO
M67201A/202A implement first-in first-out algorithm, featuring asynchronous read/write operations. FULL EMPTY flags prevent data overflow underflow. Expansion logic allows unlimited expansion word size depth with timing penalties. Twin address pointers automatically generate internal read write addresses, external address information required TEMIC FIFOs. Address pointers automatically incremented with write read pin. bits wide data used data communications applications where parity error checking necessary. Retransmit reset Read pointer zero without affecting write pointer. This very useful retransmitting data when error detected system. Using array eigh transistors memory cell fabricated with state lithography named SCMOS, 67201A/202A combine extremely standby supply current (typ with fast access time over full temperature range. versions offer battery backup data retention capability with typical power consumption less than military/space applications that demand superior levels performance reliability 67201A/202A processed according methods latest revision (class and/or 9000.
Features
First-in first-out dual port memory organisation 67201A) 1024 organisation 67202A) Fast access time 20*, commercial, industrial automotive 20*, military Wide temperature range 55°C 125°C 67201AL/202AL power 67201AV/202AV very power Fully expandable word width depth
Preview. Please Consult Sales.
Asynchronous read/write operations Empty, full half flags single device mode Retransmit capability Bi-directional applications Battery back-up operation data retention compatible Single Power Supply High performance SCMOS technology
versions also available. Please consult sales.
MATRA Rev. April.
M67201A/M67202A
Interface
Block Diagram
Configuration
plastic mils(*) plastic mils ceramic mils mils (Preview) SO/DIL (top view)
INDEX
PLCC
(top view)
request only.
FL/RT XO/HF
FL/RT XO/HF
MATRA Rev. April.
M67201A/M67202A
Names
NAMES
I0-8 Q0-8 Inputs Outputs Write Enable Read Enable Reset Empty Flag
DESCRIPTION
NAMES
XO/HF FL/RT
DESCRIPTION
Full Flag Expansion Out/Half-Full Flag Expansion First Load/Retransmit Power Supply Ground
Signal Description
Data
Data inputs data pointers first location. reset required after power-up before write operation enabled. Both Read Enable Write Enable inputs must high state during period shown figure (i.e. tRSS before rising edge should change until tRSR after rising edge Half-Full flag will reset high after Reset (RS).
RESET (RS)
Reset occurs whenever Reset (RS) input taken state. Reset returns both internal read write Figure Reset.
Notes
change status during reset, flags will valid tRSC. around rising edge
Write Enable
write cycle initiated falling edge this input Full Flag (FF) set. Data set-up hold times must maintained rise time leading edge Write Enable (W). Data stored sequentially array, regardless current read operation. Once half memory filled, during falling edge next write operation, Half-Full Flag (HF) will remain this state until difference between write read pointers less than MATRA Rev. April.
equal half total available memory device. Half-Full Flag (HF) then reset rising edge read operation. prevent data overflow, Full Flag (FF) will low, inhibiting further write operations. completion valid read operation, Full Flag (FF) will high after TRFF, allowing valid write begin. When FIFO stack full, internal write pointer blocked from that external changes will have effect full FIFO stack.
M67201A/M67202A
Read Enable
read cycle initiated falling edge Read Enable provided that Empty Flag (EF) set. data accessed first in/first basis, with standing current write operations. After Read Enable goes high, Data Outputs will return high impedance state until next Read operation. When data FIFO stack been read, Empty Flag (EF) will low, allowing "final" read cycle, inhibiting further read operations whilst data outputs remain high impedance state. Once valid write operation been completed, Empty Flag (EF) will high after tWEF valid read then initiated. When FIFO stack empty, internal read pointer blocked from that external changes will have effect empty FIFO stack.
Full Flag (FF)
Full Flag (FF) will low, inhibiting further write operations when write pointer location less than read pointer, indicating that device full. read pointer moved after Reset (RS), Full Flag (FF) will after 512/1024 writes.
Empty Flag (EF)
Empty Flag (EF) will low, inhibiting further read operations when read pointer equal write pointer, indicating that device empty.
Expansion Out/Half-full Flag (XO/HF)
This dual-purpose output. single device mode, when Expansion (XI) connected ground, this output acts indication half-full memory. After half memory filled falling edge next write operation, Half-Full Flag (HF) will will remain until difference between write read pointers less than equal half total memory device. Half-Full Flag (HF) then reset rising edge read operation. Depth Expansion Mode, Expansion (XI) connected Expansion (XO) previous device. This output acts signal next device Daisy Chain providing pulse next device when previous device reaches last memory location.
First Load/Retransmit (FL/RT)
This dual-purpose input. Depth Expansion Mode, this connected ground indicate that first loaded (see Operating Modes). Single Device Mode, this acts retransmit input. Single Device Mode initiated connecting Expansion (XI) ground. 67201A/202A made retransmit data when Retransmit Enable Control (RT) input pulsed low. retransmit operation will internal read point first location will affect write pointer. Read Enable Write Enable must high state during retransmit. retransmit feature intended when number writes equals less than depth FIFO have occured since last cycle. retransmit feature compatible with Depth Expansion Mode will affect Half-Full Flag (HF), accordance with relative locations read write pointers.
Data Output
DATA output 9-bit wide data. This data high impedance condition whenever Read high state.
Expansion (XI)
This input dual-purpose pin. Expansion (XI) connected indicate operation single device mode. Expansion (XI) connected Expansion (XO) previous device Depth Expansion Daisy Chain modes.
MATRA Rev. April.
M67201A/M67202A
Functional Description
Operating Modes Single Device Mode
single 67201A/202A used when application requirements 512/1024 words less. Figure Block Diagram Single 1024
(HALF-FULL FLAG) WRITE DATAIN READ
67201A/202A Single Device Configuration when Expansion (XI) control input grounded (see Figure this mode Half-Full Flag (HF), which active output, shared with Expansion (XO).
67201A 67202A
DATAOUT
FULL FLAG (FF) RESET (RS)
(EF) EMPTY FLAG (RT) RETRANSMIT
EXPANSION (XI)
WIDTH EXPANSION MODE
Word width increased simply connecting corresponding input control signals multiple devices.
Status flags (EF, detected from device. Figure demonstrates 18-bit word width using 67201A/202A. word width attained adding additional 67201A/202A.
Figure Block Diagram 1024 FIFO Memory Used Width Expansion Mode.
DATAIN READ WRITE FULL FLAG RESET (RS) (Q)DATAOUT Note Flag detection accomplished monitoring signals either (any) device used width expansion configuration. connect output control signals together. (FF)
67201A/202A
67201A/202A
(EF) EMPTY FLAG (RT) RETRANSMIT
MATRA Rev. April.
M67201A/M67202A
Table Reset retransmit Single Device Configuration/Width Expansion Mode
INPUTS MODE
Reset Retransmit Read/Write
INTERNAL STATUS
OUTPUTS
Read Pointer
Location Zero Location Zero Increment(4)
Write Pointer
Location Zero Unchanged Increment(4)
Note Pointer will increment flag high.
Table Reset First Load Truth Table Depth Expansion/Compound Expansion Mode
INPUTS MODE
Reset First Device Reset Other Devices Read/Write
INTERNAL STATUS
OUTPUTS
Read Pointer
Location Zero Location Zero
Write Pointer
Location Zero Location Zero
Note connected previous device. fig.
Depth Expansion (Daisy Chain) Mode
67201A/202A easily adapted applications which require more than 512/1024 words. Figure demonstrates Depth Expansion using three 67201A/202A. depth achieved adding additional 67201A/202A. 67201A/202A operate Depth Expansion configuration following conditions first device must designated connecting First Load (FL) control input ground. other devices must have high state. Expansion (XO) each device must connected Expansion (XI) next device. figure External logic needed generate composite Full Flag (FF) Empty Flag (EF). This requires that EF's (i.e. must generate correct composite EF). figure Retransmit (RT) function Half-Full Flag (HF) available Depth Expansion Mode.
Compound Expansion Module
quite simple apply expansion techniques described above together create large FIFO arrays (see figure
Bidirectional Mode
Applications which require data buffering between systems (each system being capable Read Write operations) created coupling 67201A/202A shown figure Care must taken ensure that appropriate flag monitored each system (i.e. monitored device which monitored device which use). Both Depth Expansion Width Expansion used this mode.
Data Flow Through Modes
types flow-through modes permitted read flow-through write flow-through mode. read flow-through mode (figure FIFO stack allows
MATRA Rev. April.
M67201A/M67202A
single word read after word been written empty FIFO stack. data enabled (tWEF after leading edge which known first write edge remains until line raised from high, after which will into three-state mode after tRHZ line will show pulse indicating temporary reset then will set. interval which low, more words written FIFO stack (the subsequent writes after first write edge will reset Empty Flag) however, same word (written first write edge) presented output read pointer will incremented low. toggling remaining words written FIFO will appear output accordance with read cycle timings. write flow-through mode (figure 18), FIFO stack allows single word data written immediately after single word data been read from full FIFO stack. line causes reset, line, being low, causes again anticipation data word. word loaded into FIFO stack leading edge line must toggled when order write data into FIFO stack increment write pointer.
Figure Block Diagram 1536 3072 FIFO Memory (Depth expansion).
67201A 67202A
FULL
67201A 67202A
EMPTY
67201A 67202A
Figure Compound FIFO Expansion.
67201A/202A DEPTH EXPANSION BLOCK 67201A/202A DEPTH EXPANSION BLOCK Q(N-8) Q(N-8) 67201A/202A DEPTH EXPANSION BLOCK
I(N-8)
I(N-8)
Notes depth expansion block section Depth Expansion Figure Flag detection section Width Expansion Figure
MATRA Rev. April.
M67201A/M67202A
Figure Bidirectional FIFO Mode.
67201A 67202A
SYSTEM
SYSTEM
67201A 67202A
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC GND) Input Output voltage applied (GND (Vcc Storage temperature
OPERATING RANGE
Military Industrial Commercial Automotive
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
Parameters
67201A 67202A (Preview)
ICCOP Operating supply current Standby supply current Power down current
67201A 67202A
67201A 67202A
67201A 67202A
AUTO AUTO
UNIT AUTO
VALUE
ICCSB
ICCPD (10)
MATRA Rev. April.
M67201A/M67202A
Parameters (continued)
67201A 67202A Parameter
ICCOP
67201A 67202A
67201A 67202A
67201A 67202A
Description
Operating supply current Standby supply current Power down current
Version
AUTO
UNIT AUTO
VALVAL
ICCSB
ICCPD (10)
Notes
measurements made with outputs open. FL/RT VIH. input Vcc.
67201A/M67202A PARAMETER
(11) (12) (13) (13) (14) (14) (15) (15) Notes
DESCRIPTION
Input leakage current Output leakage current Input voltage Input high voltage Output voltage Output high voltage Input capacitance Output capacitance
20/- 25/-
35/- 40/- 45/- 50/-
UNIT
VALUE
Vcc. VIH, VOUT VCC. -0.3 pulse width min, This parameter sampled tested MHz.
Test Conditions
Input pulse levels Input rise/Fall times Input timing reference levels Output reference levels Output load figure
Figure Output Load.
OUTPUT
includes scope capacitance
MATRA Rev. April.
M67201A/M67202A
67201A/202A 67201A/202A 67201A/202A 67201A/202A
SYMBOL (16)
SYMBOL (17)
PARAMETER (18) (22)
COM, IND, COM, IND, MIL, AUTO MIL, AUTO
PREVIEW
ONLY
COM, IND, AUTO
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ TWLWL TWLWH TWHWL TDVWH TWHDX TRSLWL TRSLRSH TWHRSH TRSHWL TRTLWL TRTLRTH TWHRTH TRTHWL FLAGS TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset Reset HF/FF high Read Read high high Read width after high Write high high Write Write Read high high Write width after high tRPW tRLZ tWLZ tRHZ tWPW tRSC tRSS tRSR tRTC tRTS tRTR Read cycle time Access time Read recovery time Read pulse width (19) Read data (20) Write data (20, Data valid from read high Read high data high (20) Write cycle time Write pulse width (19) Write recovery time Data set-up time Data hold time Reset cycle time Reset pulse width (19) Reset set-up time Reset recovery time Retransmit cycle time Retransmit pulse width (19) Retransmit set-up time (20) Retransmit recovery time
WRITE CYCLE
PREVIEW
RESET CYCLE
PREVIEW
RETRANSMIT CYCLE
PREVIEW
PREVIEW
MATRA Rev. April.
M67201A/M67202A
67201A/202A 67201A/202A 67201A/202A 67201A/202A
SYMBOL (16)
SYMBOL (17)
ONLY PARAMETER (18) (22)
COM, IND, MIL, AUTO
ONLY
COM, IND, AUTO
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ TWLWL TWLWH TWHWL TDVWH TWHDX TRSLWL TRSLRSH TWHRSH TRSHWL TRTLWL TRTLRTH TWHRTH TRTHWL FLAGS TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset Reset HF/FF high Read Read high high Read width after high Write high high Write Write Read high high Write width after high tRPW tRLZ tWLZ tRHZ tWPW tRSC tRSS tRSR tRTC tRTS tRTR Read cycle time Access time Read recovery time Read pulse width (19) Read data (20) Write data (20, Data valid from read high Read high data high (20) Write cycle time Write pulse width (19) Write recovery time Data set-up time Data hold time Reset cycle time Reset pulse width (19) Reset set-up time Reset recovery time Retransmit cycle time Retransmit pulse width (19) Retransmit set-up time (20) Retransmit recovery time
WRITE CYCLE
RESET CYCLE
RETRANSMIT CYCLE
MATRA Rev. April.
M67201A/M67202A
67201A/202A 67201A/202A 67201A/202A 67201A/202A
SYMBOL (16)
SYMBOL (17)
PARAMETER (18) (22)
COM, IND, COM, IND, MIL, AUTO MIL, AUTO
PREVIEW
ONLY
COM, IND, AUTO
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
EXPANSION TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL tXOL tXOH tXIR tXIS Read/Write Read/Write high pulse width recovery time set-up time
67201A/202A
67201A/202A
67201A/202A
67201A/202A
SYMBOL (16)
SYMBOL (17)
ONLY PARAMETER (18) (22)
COM, IND, MIL, AUTO
ONLY
COM, IND, AUTO
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
EXPANSION TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL Notes tXOL tXOH tXIR tXIS Read/Write Read/Write high pulse width recovery time set-up time
symbol. symbol. Timings referenced test conditions. Pulse widths less than minimam value allowed. Values guaranteed design, currently tested. Only applies read data flow-through mode. parameters tested only.
Figure Asynchronous Write Read Operation.
MATRA Rev. April.
M67201A/M67202A
Figure Full Flag from Last Write First Read.
Figure Empty Flag from Last Read First Write.
Figure Retransmit.
Note
change status during Retransmit, flags will valid tRTC.
MATRA Rev. April.
M67201A/M67202A
Figure Empty Flag Timing
Figure Full Flag Timing
Figure Half-Full Flag Timing.
MATRA Rev. April.
M67201A/M67202A
Figure Expansion Out.
Figure Expansion
Figure Read Data Flow Through Mode.
MATRA Rev. April.
M67201A/M67202A
Figure Write Data Flow Through Mode.
Ordering Information
TEMPERATURE RANGE PACKAGE DEVICE 67201AL SPEED FLOW
version version ceramic mils plastic mils plastic mils plastic mils rectangular PLCC mils (Preview) Side brazed pins mils Dice form Commercial Industrial Automotive Military Space request only -40° -40° -55° -55° +70°C +85°C +125°C +125°C +125°C 67201 FIFO 67202 1024 FIFO power Very power
blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX
standards Class PIND test 9000 level Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape reel Tape reel pack pack
MATRA Rev. April.
M67201A/M67202A
Military Space Versions
following tables give package/consumption/access time/process flow available combinations
Temp. range Packages Consumption
Access Time (ns)
process 67201A
flows (including SMD5962-87531 SMD5962-89863)
process 67201F
flows Space flows
Temp. range
Packages
Consumption
Access Time (ns)
process 67202A
flows (including SMD5962-89536)
process 67202F
flows Space flows (including SCC9301032)
product production call sales office availibility
information contained herein subject change without notice. responsibility assumed TEMIC using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
MATRA Rev. April.

CMOS Parallel FIFO M67201A/202A implement first-in first-out algo

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