Quad 2-Input NAND Gate With Open-Drain Outputs MC74HC03A identica
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Quad 2-Input NAND Gate With Open-Drain Outputs
MC74HC03A identical pinout LS03. device inputs compatible with Standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs. HC03A NAND gate has, outputs, high-performance N-Channel transistor. This NAND gate can, therefore, with suitable pullup resistor, used wired-AND applications. Having output characteristic curves given this data sheet, this device used driver other application that only requires sinking current. Output Drive Capability: LSTTL Loads With Suitable Pullup Resistor Outputs Directly Interface CMOS, NMOS High Noise Immunity Characteristic CMOS Devices Operating Voltage Range: Input Current: Compliance With JEDEC Standard Requirements Chip Complexity: FETs Equivalent Gates
MC74HC03A
SUFFIX PLASTIC PACKAGE CASE 646-06
SUFFIX SOIC PACKAGE CASE 751A-03
SUFFIX TSSOP PACKAGE CASE 948G-01
ORDERING INFORMATION MC74HCXXAN MC74HCXXAD MC74HCXXADT Plastic SOIC TSSOP
DESIGN GUIDE
Criteria Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product Equivalent two-input NAND gate Value 0.0075 Unit
FUNCTION TABLE
Inputs Output
High Impedance
LOGIC DIAGRAM
OUTPUT PROTECTION DIODE
Pinout: 14-Lead Packages (Top View)
3,6,8,11
1,4,9,12 2,5,10,13
Denotes open-drain outputs
10/95
Motorola, Inc. 1995
MC74HC03A
MAXIMUM RATINGS*
Symbol Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Vout Output Voltage (Referenced GND) Input Current, Iout Output Current, Supply Current, Pins Power Dissipation Still Plastic SOIC Package TSSOP Package Tstg Storage Temperature
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Lead Temperature, from Case Seconds Plastic DIP, SOIC TSSOP Package
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. Derating Plastic DIP: mW/_C from 125_C SOIC Package: mW/_C from 125_C TSSOP Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Unit Supply Voltage (Referenced GND) Vin, Vout Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure 1000
CHARACTERISTICS (Voltages Referenced GND)
Symbol Parameter
Condition
Guaranteed Limit 25°C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 0.26 0.26 0.26 ±0.1 ±0.5 85°C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 0.33 0.33 0.33 ±1.0 ±5.0 125°C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 0.40 0.40 0.40 ±1.0 Unit
Minimum High-Level Input Voltage
Vout 0.1V -0.1V |Iout| 20µA
Maximum Low-Level Input Voltage
Vout 0.1V 0.1V |Iout| 20µA
Maximum Low-Level Output Voltage
Vout 0.1V 0.1V |Iout| 20µA |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current
Iout Output High-Impedance State Vout
NOTE: Information typical parametric values found Chapter Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129
MC74HC03A
CHARACTERISTICS 50pF, Input 6ns)
Symbol tPLZ, tPZL Parameter Maximum Propagation Delay, Input Output (Figures Guaranteed Limit 25°C 85°C 125°C Unit
tTLH, tTHL
Maximum Output Transition Time, Output (Figures
Cout
Maximum Input Capacitance Maximum Three-State Output Capacitance (Output High-Impedance State)
NOTE: propagation delays with loads other than information typical parametric values, Chapter Motorola High- Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Buffer)* Used determine no-load dynamic power consumption: VCC2f VCC. load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129
MC74HC03A
INPUT tPZL OUTPUT tTHL tPLZ HIGH IMPEDANCE *Includes probe capacitance DEVICE UNDER TEST
OUTPUT
TEST POINT
Figure Switching Waveforms
TYPICAL T=25°C SINK CURRENT (mA) T=25°C T=85°C T=125°C EXPECTED MINIMUM* VCC=5V
Figure Test Circuit
OUTPUT VOLTAGE (VOLTS)
*The expected minimum curves guarantees, design aids.
Figure Open-Drain Output Characteristics
PULLUP RESISTOR
HC03 HC03
LED1
HC03 HC03
OUTPUT
LED2 ENABLE
DESIGN EXAMPLE CONDITIONS: 10mA USING FIGURE TYPICAL CURVE, ID=10mA, 0.4V
HC03
OUTPUT A1B1 A2B2 AnBn
1.7V 0.4V 10mA 290W
Figure Wired
Figure Driver With Blanking
High-Speed CMOS Logic Data DL129
MC74HC03A
OUTLINE DIMENSIONS
SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE
NOTES: LEADS WITHIN 0.13 (0.005) RADIUS TRUE POSITION SEATING PLANE MAXIMUM MATERIAL CONDITION. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 0.052 0.095 0.008 0.015 0.115 0.135 0.300 0.015 0.039 MILLIMETERS 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 1.32 2.41 0.20 0.38 2.92 3.43 7.62 0.39 1.01
SEATING PLANE
SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION.
0.25 (0.010)
SEATING PLANE
0.25 (0.010)
MILLIMETERS 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 0.25 0.19 0.25 0.10 5.80 6.20 0.25 0.50
INCHES 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.228 0.244 0.010 0.019
High-Speed CMOS Logic Data DL129
MC74HC03A
OUTLINE DIMENSIONS
SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
0.10 (0.004) 0.15 (0.006)
0.25 (0.010)
IDENT.
DETAIL
0.15 (0.006)
SECTION
0.10 (0.004) SEATING
PLANE
DETAIL
High-Speed CMOS Logic Data DL129
MC74HC03A
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298
High-Speed CMOS Logic Data DL129
CODELINE
*MC74HC03A/D*
MC74HC03A/D
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