Winbond W9330F integrated cordless telephone controller. employs Code

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Winbond W9330F integrated cordless telephone controller. employs Code

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Preliminary W9330F CODE DIVISION SPREAD SPECTRUM TELEPHONE CHIP
Winbond W9330F integrated cordless telephone controller. employs Code Division Spread Spectrum (CD/SS) technology optimized cost, consumer applications while providing clarity, distance security digital spread spectrum communication. Targeted single chip baseband solution, W9330F incorporates digital signal processing (DSP) system control functions module, voice codec interface, thus freeing other user oriented tasks. Using 1-bit analog digital conversion (ADC) technique, signal processings performed extended time domain transformation allow cost radio modules. Linear coding schemes such FSK, BPSK supported. Advance built features include acoustic echo minimization, data encryption, diversity antenna control. proprietary noise reduction scheme implemented correct speed multipath fading found consumer cordless wireless local loop applications. W9330F implemented power CMOS process technology. contained 100pin PQFP package. complete reference design available telephone manufacturers quick turn development.
Cost Single Chip Baseband Cordless Telephone Solution Advanced CD/SS digital signal processing architecture part-15 compliant unlicensed band operation Optimized cost telephone components Acoustic Echo Support Multiple Handset Designs Separate Command Data Fields 22-bit User Selectable with Automatic Hardware Authentication Audio Noise Reduction with Automatic Digital Noise Control On-chip PLL, module Codec Interface Variable Rate Clock Generation Integrated Power Management Hardware Supported Dual Antenna Design Multi Clock Synchronization Wireless Local Loop Applications Built-in Data Encryption 3.0V Single Power Supply with 5.0V Tolerant Packaged 100-pin PQFP/TQFP
Publication Release Date: August 1998 Revision
Preliminary W9330F
CONFIGURATION
W9330F 100-QFP
CPU_CLK OSC_IN OSC_OUT CLK_IN CLK_OUT COD_SYNC COD_CLK BSYNC_OUT BSYNC_IN PLL_SW RF_PWR TX_ENV TX_DATA RX_DATA
Preliminary W9330F
BLOCK DIAGRAM
AD[7:0] COD_CLK COD_SYN CPU_CLK OSC_EN OSCI OSCO ID_DET LOCK RLOCK CHIP_EN
INTERFACE
PNA,
XMTR/ SPREADER
GENERAL
TX_DATA RX_DATA RF_PWR PLL_SW TX_ENV ANTSW
RCVR/ DE-SPREADER
TDD_CTRL
FIFO FIFO
DESCRIPTIONS
following table describes external pins W9330F. following conventions abbreviations used signal descriptions: Signal Name: active signals indicated overscore; otherwise signal active high. Signal Type: input IN_D input with built-in pull down resister IN_U input with built-in pull resister output Open-drain output Bi-directional signal
Publication Release Date: August 1998 Revision
Preliminary W9330F
Table Micro-controller Access Signals PARAMETER AD[7:0] TYPE DESCRIPTIONS Address data bus. This multiplexed address data used micro-controller interface
Address Latch Enable. Access address latched falling edge ALE. address specifies on-chip register being accessed micro-controller. Chip Select. This signal asserted during micro-controller access cycle. Interrupt Request. asserted W9330F interrupt system micro-controller certain operation points. Interrupt generated each transmit frame, each receive frame, when frame error detected. Read Control. When asserted, read data driven AD[7:0] W9330F. Write Control. When asserted, write data AD[7:0] sampled W9330F.
Table Codec Interface PARAMETER COD_CLK TYPE DESCRIPTIONS Codec transmit receive clock. used Codec chip sample received data generate transmit data. This signal generated from main operating frequency KHz. Codec Synchronization signal. This framing clock signal used Codec synchronized transmit receive data. COD_SYNC synchronous with COD_CLK generated from main operating frequency. Received Data. Voice data sampled Codec. sampled Codec chip falling edge COD_CLK beginning each frame. Transmit data. Voice data generated Codec transmission. generated Codec rising edge COD_CLK.
COD_SYNC
Preliminary W9330F
Table Module Interface PARAMETER ANTSW TYPE DESCRIPTIONS Antenna Switch. This signal used switch between available antenna system. ANTSW signal changes state only beginning time between frames. Phase Lock Loop Switch. This signal switches transceiver phase lock loop between transmit receive mode. PLL_SW high during transmission preceding time. when receiving. Power. This signal switches transmitter during full duplex operation. high when transmitting when receiving. enveloped TX_ENV ensure proper timing sequence when module switches direction. Received Data. data recovered from module. Input de-spreader circuitry. Transmit Data. Output spreader circuitry transmitted module. TX_DATA high drive output tolerant. other external pins tolerant. Transmitter Power. Switches direction module. high when transmitting when receiving. envelopes RF_PWR chip time both edges.
PLL_SW
RF_PWR
RX_DATA TX_DATA
TX_ENV
Table System Interface PARAMETER BSYNC_IN TYPE IN_D DESCRIPTIONS Burst Synchronization Input. This signal designed setup where multiple master located together. BSYNC_IN signals should connected together that masters start transmission same time. Burst Synchronization Output. This signal designed setup where multiple master located together. BSYNC_OUT master should used synchronization source connected BSYNC_IN masters, including BSYNC_IN synchronize transmission. only master issused, BSYNC_OUT should connected BSYNC_IN same device. Chip Enable. This signal controls internal clocks device. When de-asserted, internal clocks remain unchanged (time freeze). CPU_CLK signal internal timer still operational while CHIP_EN de-asserted. device operation mode only when CHIP_EN asserted.
BSYNC_OUT
CHIP_EN
Publication Release Date: August 1998 Revision
Preliminary W9330F
Table System Interface, continued
PARAMETER CLK_IN CLK_OUT CPU_CLK
TYPE
DESCRIPTIONS System clock input. should 19.2 MHz. System clock output. This signal generated oscillator circuit should connected CLK_IN input Clock. This clock input system microcontroller. After power this main operating clock divided programmed divided Check Error. This signal asserted each receive subframe indicate that least single error been detected. cleared with status register read. General Purpose Timer. This signal output programmable general purpose timer. cycle time this output programmable between usec 8.192 with duty cycle. detection. This signal during each receive frame after field been detected. clear receive frame found. Lock. Indicates that W9330F LOCK state with remote device. functional description section more detail. connect. These pins must left unconnected system.
LOCK
IN_U
Output enable port output pins. Crystal oscillator enable signal. oscillator circuit when this signal de-asserted. Crystal input. Crystal output General purpose output port.
OSC_ OSC_IN OSC_OUT PA[7:0]
PB[7:4] PB[3:0] PC[7:4] PC[3:0]
IN_U IN_D
General purpose output port.
General purpose input port.
Preliminary W9330F
Table System Interface, continued
PARAMETER PD[7:0]
TYPE
DESCRIPTIONS General purpose port
RESET RLOCK WAKEUP
System reset. This asynchronous reset signal. RESET must asserted least clock cycles after initial power Remote Lock. Indicates that W9330F RLOCK state. functional description section more detail Combinational output port input pins. WAKEUP PC0| PC1|PC2|PC3|~PC4|~PC5|~PC6|~PC7
FUNCTIONAL DESCRIPTION
W9330F integrated baseband chip designed digital cordless telephone applications. employs direct sequence spread spectrum technology secure superior voice data transmission. telephone controller functions provided including: time division duplex control, pseudo noise spreader de-spreader, direct codec interface expansion ports.
Spreader De-spreader
function spreader spread spectrum communication system. encodes (spreads) voice data into multiple (chip) pseudo-noise (PN) sequence transmission. Four sets sequences, chips each, programmable system controller. four sequences their opposite phase counterparts form eight possible combinations. Every three bits transmit data grouped together form symbol. Each eight possible symbol assigned combination. With each sequence being 32-chip long each symbol carries bits user data, spread ratio 10.667. de-spreader performs reversed function spreader. received signal (chip) sampled de-spreader compared with eight possible sequence being sent. user data recovered based best-matched sequence. received signal sampled de-spreader twice chip rate. This sampling rate chosen ensure that transmitted signal sufficiently reconstructed after environmental distortion. following diagram shows principal functions spreader de-spreader.
Publication Release Date: August 1998 Revision
Preliminary W9330F
programmable sequence
speader transmit signal de-speader receive signal (fromRF)
sequence comparator Receive symbol sequence select Transmit symbol
Time Division Duplex
W9330F emulates full duplex communication half duplex link using time division duplex (TDD). communication units, designated master other designated slave, communicate with each other using protocol. Within each time slot, only device transmitting other either idle receiving mode. Three types communication frames used master slave establish communication link transmit data. frame structures illustrated following diagram. Each frame consists bits. includes 54-bit preamble five sub-frames. Each sub-frame contains bits data bits parity. first subframe contains bits field which uniquely identifies master-slave pair. Between transmitting receiving each frame, idle time equals transmission time bits added module switching locking. chip rate 1.365333 spread 10.667, transmission time frame including idle time exactly 3.000 With bits user data transmitted frame, data bandwidth Kbps each direction. Communication initiated master sending acquisition frame. When slave acquires acquisition frame correctly matches field, responds sending another acquisition frame master. When master receives acquisition frame with correct responds sending empty frame slave. slave responds sending another empty frame communication link established. Once link established, master slave take turns sending data frame. Each data frame contains status sub-frame identify intended receiver command/status information addition user data.
Preliminary W9330F
Acquisition Frame
Preamble ID&ST IDx2 IDx2 IDx2 IDx2
Empty Frame
Preamble ID&ST
Data Frame
Preamble ID&ST Data Data Data Data
Receive frame
idle Transmit frame
idle
Receive frame
System Controller Interface
Interface system controller through on-chip registers, interrupt group auxiliary status signals. Control register access control registers W9330F accessed system controller through simple interface. registers expansion ports uniquely identified 8-bit address. following diagram illustrates read write access timing on-chip registers. Each access must enclosed assertion soon asserted, access address specified with asserted. access address latched falling edge ALE. Once address latched, access command specified asserting signals. asserted, read data driven W9330F bus. system controller must tri-state before asserting avoid data contention. asserted, data written into register specified during ALE. valid data must driven before asserted. gated write supported.
Publication Release Date: August 1998 Revision
Preliminary W9330F
Read Access
(input) (output)
Write Access
(input)
Interrupt W9330F programmed generate system interrupt each transmit receive frame subframe. command register set, interrupt generated each transmit frame. SUBE command register also set, interrupt generated each transmit subframe addition frame. command register similar function applied receive frame subframe. When interrupt, asserted, remains asserted until status register read controller. When status register read, some status bits cleared same time. status register read before next interrupt arrives, second interrupt detected since remains asserted starting from first interrupt. Auxiliary status signals W9330F provides additional status signals assist system design. LOCK signal asserted after device successfully receive acquisition frame. remains asserted until communication link broken. RLOCK signal asserted after device successfully receive empty frame. remains asserted until communication link broken. asserted when receiving device detects correct system receive frame. asserted around first subframe receive frame. Once asserted, remains asserted until frame. W9330F allows symbol errors within field. asserted less symbol error detected field.
Preliminary W9330F
asserted when parity error detected subframe. cleared when status register read system controller.
Clock Generator
W9330F operates with system crystal oscillator 19.2 MHz. CLK_IN signal system clock input pin. internal timing signals, including chip rate sampling rate, generated from this main clock. system clock supplied external source generated through on-chip oscillator circuit. on-chip oscillator circuit consists four pins, OSC_IN, OSC_OUT, OSC_ CLK_OUT. OSC_IN OSC_OUT pins connected external crystal. OSC_ should asserted (low) enable oscillator circuit. CLK_OUT buffered output oscillator which capable driving multiple external devices. on-chip oscillator used generate system clock input, CLK_OUT CLK_IN should connected together externally. system clock provided external source other than on-chip oscillator, oscillator circuit turned deasserting OSC_ external clock source should drive CLK_IN input directly. power down mode OSC_ signal de-asserted stop oscillator system clock conserve power. W9330F contains programmable clock generator generate divided-down clock system controller. clock output from W9330F programmed MHz, MHz, (CLK_IN divided off. After system reset, clock runs (divided
Codec Interface
W9330F supports ADPCM Codec chips that compatible with CCITT G.721 recommendation ANSI T1.301. Once communication established between master slave, W9330F interfaces directly with codec retrieve transmit data send received data. generates codec framing signal COD_SYNC clocking signal COD_CLK. COD_SYNC signal signal generated from system clock. COD_CLK signal KHz, equivalent COD_SYNC. rising edge COD_SYNC defines data frame codec chip. COD_SYNC signal remains high four COD_CLK cycles. codec chip samples four bits data falling edge COD_CLK while COD_SYNC high. User data recovered de-spreader W9330F stored on-chip FIFO then outputted sampled codec, synchronized with COD_SYNC COD_CLK signals. Data transmitted W9330F generated codec first four rising edge COD_CLK each data frame. transmit data, sampled W9330F falling edge COD_CLK stored on-chip FIFO. During transmission time, data read from FIFO sent module through spreader. following timing diagram illustrates timing codec interface.
Publication Release Date: August 1998 Revision
Preliminary W9330F
cod_clock
COD_SYNC COD_CLK Sampling Point
Interface
module interface consists PLL_SW, RF_PWR, TX_ENV, TX_DATA, RX_DATA ANTSW signals. PLL_SW, RF_PWR andTX_ENV signals control module receive transmit state. ANTSW signals issued only dual antenna design select available antennas. value ANTSW follows ANTSW control register. transmit frame receive frame, value stored ANTSW copied ANTSW output. During transmit receive frame, ANTSW output remains unchanged. following timing diagram illustrates control signals when switching between transmitting receiving.
Receive Frame
idle
idle
Receive Frame
Transmit Frame
RF_PWR TX_ENV PLL_SW
time
Preliminary W9330F
Reset
W9330F reset through hardware software. Hardware reset when RESET input asserted with system clock running. Software reset done writing "one" command register. Hardware reset software reset very similar except that some control registers return their default values through hardware reset while some other control registers return default value through either reset. register description section this data sheet describes conditions when each register returns default value. should noted that some register values such expansion ports affected either reset. After system power-up, RESET signal must asserted least clock cycles before system function properly. When RESET signal de-asserted, W9330F enters standby mode. During standby, control registers hold current value system controller interface expansion blocks fully functional. control registers, including command registers, should programmed controller during standby mode. Once programming completed, STRT command register start operation.
Advanced Power Management
W9330F three power down modes: sleep, freeze standby. Sleep mode lowest level power consumption. device enters sleep mode when OSC_ de-asserted. system clock, CLK_IN, supplied external source, should also stop toggling. Most function W9330F, including CPU_CLK, general purpose timer, CODEC interface, stopped sleep mode. controller interface ports still operational. control registers ports retain their values control register still accessed through controller interface. However, read status register would clear signal. order conserve power, controller activity register access should keep minimum. exit from sleep mode, device must through standby mode. device must first reset through hardware reset software reset. While reset OSC_ external clock re-asserted. hardware software reset then removed device standby mode. Freeze mode second lowest level power saving. device enters freeze mode when CHIP_EN input de-asserted. similar sleep mode except that since system clock still toggling, CPU_CLK general purpose timer functions still operational. Exit from freeze mode similar exit from sleep mode. Standby mode entered executing hardware software reset while system clock running. standby mode, device operational except that communication protocol running. When STRT command register set, device enters active mode becomes fully operational. device receives transmits data only active mode. order ensure that device enters sleep freeze mode with output pins proper setting, device must first reset through hardware software before entering either sleep freeze modes. on-chip oscillator used system clock supplied external source, OSC_ must de-asserted time avoid device switching noise minimize power consumption. Publication Release Date: August 1998 Revision
Preliminary W9330F
Active
power consumption level
reset de-assert osc_en
Standby
reset de-assert chip_en
Freeze Sleep
Noise Reduction Control
During voice communication, audible noise occur system through mechanisms: (1)data underflow/overflow communication link broken. Data underflow overflow caused frequency mis-match between master slave. rate underflow overflow proportional mis-match. shown that operating frequencies between master slave differs ppm, overflow underflow occurs every second. event data overflow, receiver receives data rate faster than sends ADPCM codec. When enough data accumulated within W9330F receiving FIFO, drops bits ADPCM aligned data each time occurs. Overflow audible because every 8-bit segment ADPCM data play time only usec occurs infrequently that virtually information lost. Data underflow occurs when receiver receives data rate slower than Kbps required ADPCM codec. When occurs, W9330F adds 8-bit quiet code into codec stream. quiet code holds audio output steady usec until next data arrives. occurrence such event audible human short duration. value quiet code programmable user that different codec devices supported. Communication link broken when receiver cannot acquire receive data frame. This event signaled controller frame error communication link must re-established. W9330F programmable handling frame error. STKY command register cleared, W9330F will immediately declare lose lock frame error. LOCK RLOCK bits will dropped will re-establish link sending receiving acquisition frame. STKY command register set, W9330F continues transmit data frame frame error times. receive correct data frame during this time, communication link remains intact. declares lose lock only when cannot receive correct data frame after several attempts. number attempts continues transmit frame error also programmable user through control registers. During time when data received, W9330F sends quiet code codec. This eliminates need audio signal muting controller during frame error.
Preliminary W9330F
Data Encryption
Data transmission using code division spread spectrum technology inherently secure code. W9330F adds another level data security allowing user encrypt transmit data frame-by-frame basis. transmit data encoded random sequence generated on-chip. Only receivers programmed with same random sequence decipher transmit frame. random sequence generated following polynomial f(X): f(X) Unique random sequence defined user initializing value through control registers.
Error Detection
Error detection built-in W9330F. Every bits transmit data accompanied parity bit. Parity generation detection automatically performed. status register output signals when parity error detected. They within each subframe when parity detected cleared when status register read.
Signal Strength Indicator
Code division spread spectrum (CD/SS) devices receive data matching received signal with expected code. signal strength indicator indicates well received signal correlates with expected code. indicator accumulative value correlation factor each received data starting from beginning each frame. subframe interrupt bit, SUBE, turned signal strength indicator read each subframe frame interrupt, value always increasing from first interrupt until last interrupt receive frame. This value provides very good indication clean communication link seen W9330F. signal strength indicator relative value. Higher value indicates stronger code correlation. Value 5F(Hex) expected frame when strong signal received. When frame error detected receive frame, signal strength indicator does carry meaningful value.
Expansion Ports
W9330F contains four expansion ports facilitate system design. Port port output ports with PA7: PB7: corresponding output pins. Port tri-stated deasserting input pin. Port divided into halves, lower half, PB3: regular output buffers always enabled. upper half, PB7: open drain outputs. Both port port address-able well byte address-able. Port input port with pins PC7:0. read through control register also feeds combinational output signal. output signal, WAKEUP, defined with following logical function: WAKEUP ~PC4 ~PC5| ~PC6 ~PC7 Port general purpose port. functions output port when control register 44(Hex) cleared. control set, output buffers pins PD7: tri-stated input value read. internal registers holding value ports static registers affected software reset power management functions. ports written read even when system clock turned off. Upon hardware reset, port becomes input port registers holding output values set. Port also hardware reset. Publication Release Date: August 1998 Revision
Preliminary W9330F
General Purpose Timer
general purpose timer included W9330F. used system designer various functions such watch timer tone generator. output signal duty cycle signal cycle time programmable between usec sec. cycle time controlled register 46(Hex) 47(Hex) with 47(Hex) being upper byte 46(Hex) being lower byte. Together they form 16-bit value which becomes multiplying factor cycle time with usec being basic time unit. When registers programmed with zero, output stops toggle.
CONTROL REGISTERS
control registers W9330F accessed through system controller interface. This section describes each control register detail. following table lists control registers. register types are: Read write-able, write only register, read only register. REGISTER
Command 1/Status Command Quiet Code Transmit field Received field System Clock divider Preamble threshold Signal strength Preamble count Scrambler Sticky count code, symbol zero code, symbol code, symbol code, symbol three expansion port, wise expansion port, wise expansion port, byte wise expansion port, byte wise expansion port, expansion port, control timer, lower byte timer, upper byte Reserved
TYPE ADDRESS
Others
HARDWARE RESET VALUE
00000000 00000000 10000000 00000011 00001000 00110111 00000000 00000011 11111111 11111111 11111111 00000000 00000000
Preliminary W9330F
Address Command Status Both Command register Status register mapped register address When this address written, input data written into Command register following format. ANTSW STRT STKY
must written zero. Receive only bit. this device operates slave mode, does transmit response frame even when valid acquisition burst frame detected. Antenna switch bit. output signal ANTSW reflects value ANTSW bit. When value ANTSW changes, output signal ANTSW will change state only when PLL_SW output change state. Soft reset bit. Setting this would have similar effect asserting RESET external input pin(hardware reset). cleared when external RESET asserted. Write this enter soft reset state write zero exit soft reset. Start bit. device starts normal operation when this set. STICKY bit. this enables sticky count register (1FH) when set. description sticky count register more detail. Reset value: cleared hardware reset affected software reset. cleared hardware reset. cleared both hardware software reset. When register location read, status register value outputted with following format. ANTSW SUBF
This register should read system controller each interrupt. interrupt request pin, cleared after each read. Lock bit. This whenever acquisition frame been received device. Once set, this remains unless communication link broken. Rlock bit. This whenever empty frame been received device. Once set, this remains unless communication link broken. same value ANTSW output pin. Sub-frame end. This whenever interrupt generated subframe. When interrupt generated complete data frame, this cleared. have valid information only when cleared. Frame Error. This when device fail detect frame preamble when system mis-match. When this set, does hold valid information. This parity error detected subframe. This cleared every time this register read. Transmit End. This transmit frame subframe. Received End. This received frame subframe.
Publication Release Date: August 1998 Revision
Preliminary W9330F
Address Command write only. default: 00000000 FLIP_TX FLIP_RX SUBE
Reserved. Must zero when writing this register. When this set, TX_DATA output reversed polarity. When this set, RX_DATA input interpreted with reversed polarity. Subframe enable. SUBE either set, interrupt generated each transmit receive subframe, depending SUBE clear while either set, interrupt generated only each full data frame. Transmit-end enable bit. Setting this would enable interrupt generated each transmit frame subframe. Receive-end enable bit. Setting this would enable interrupt generated each receive frame subframe. Master/Slave select bit. device functions master this set. functions slave this cleared. Test/Normal mode select bit. This must cleared normal operation. cleared hardware software reset. Address Quiet Code, write only. default: 10000000 Quiet Code This register controls output value receive data FIFO when data underflow occurs. value equal quiet code CODEC should written into this register. When data underflow occurs, value this register outputted CODEC. This register default value hardware reset unaffected software reset. Address transmit status, write only, default value STO[7:0] STO[15:8] STO[23:16] transmit status field sent W9330F during transmission frame. Value field defined system controller interpreted W9330F. value these registers unaffected hardware software reset. They undefined after system power Address received status, read only STI[7:0] STI[15:8] STI[23:16] received status field stores status value received from each receive frame. These registers updated beginning each receive frame after status received. Value field defined system controller interpreted W9330F.
Preliminary W9330F
Address system write only, default value ID[7:0] ID[15:8] ID[21:16] These registers contain system Address contains least significant bits contains most significant bits. first bits register hard-wired they become most significant bits when frame transmitted. Both master slave should programmed same value. value these registers unaffected hardware software reset. They undefined after system power Address CLK, write only. default: 00000011
defines clock divider. bit[1:0] CPU_CLK output equivalent OSC_IN divided bit[1:0] CPU_CLK divided bit[1:0] CPU_CLK divided bit[1:0] CPU_CLK output always low. This register default value hardware reset. affected software reset. Address Threshold, write only. default: 00001000
least significant bits this register define threshold value de-spreader recognizing preamble symbol. Each acquired symbol signal strength value between preamble symbol must have signal strength above order recognized. "1000" hardware reset affected software reset. Address Signal Strength, read only. Signal Strength This register relative strength indicator received signal. FF(Hex) indicates strongest signal 0x00 indicates weakest signal. This register should read each receive frame determine signal strength. This register used assist system software adjust signal level select antenna multi-antenna design. Address Preamble count, write only. default: 00110111 CNT1 CNT2
This register contains preamble symbol count during preamble acquisition. Preamble acquisition divided into stages. first stage completed when number preamble symbol equals CNT1 acquired. second stage completed when number preamble symbol equals CNT2 acquired. CNT2 must always larger than CNT1. This register default value during hardware reset affected software reset.
Publication Release Date: August 1998 Revision
Preliminary W9330F
Address Encryption register, write only. default: 00000000 Encryption This register contains encryption used transmit receive data. Both master slave must programmed same value order communicate. This register default value during hardware reset affected software reset. Address Sticky count, write only. default: 00000011 Sticky count
least significant bits this register determine sticky count. sticky count number error data frame device allowed before would re-establish communication link through acquisition burst frame protocol. STKY Command register cleared, sticky count register ignored communication link must re-established every data frame error. This register default value during hardware reset affected software reset. Address code, write only, default value CODEZERO[7:0] CODEZERO[15:8] CODEZERO[23:16] CODEZERO[31:24] These registers contain sequence symbol "000" "111". code registers affected hardware software reset. Address code, write only, default value CODEONE[7:0] CODEONE[15:8] CODEONE[23:16] CODEONE[31:24] These registers contain sequence symbol "001" "110". code registers affected hardware software reset. Address code, write only, default value CODETWO[7:0] CODETWO[15:8] CODETWO[23:16] CODETWO[31:24] These registers contain sequence symbol "010" "101". code registers affected hardware software reset.
Preliminary W9330F
Address code, write only, default value CODETHREE[7:0] CODETHREE[15:8] CODETHREE[23:16] CODETHREE[31:24] These registers contain sequence symbol "011" "100". code registers affected hardware software reset. Address expansion port write only Address bit-wise address expansion port data position each same addressed through byte-wise address, i.e. access through through AD0. Address expansion port write only Bit-wise address port Access method same port Address expansion port write only This byte-wise address port When address written, bits port updated same time. This port affected hardware software reset. Address expansion port write only. default: 11111111 This byte-wise address port When address written, bits port updated same time. This port hardware reset affected software reset. Address expansion port read only this register mapped input port PC[7:0]. This port affected hardware software reset. Address expansion port read write. default: 11111111 this register mapped port PD[7:0]. When this port output mode, write this register sets value pins. When this port input mode, value pins read from this location. This port hardware reset affected software reset. Address control, port write only. default: 11111111 this register control port When one, port input port. When zero, port output port pins driven device. Other bits this register reserved. This register hardware reset affected software reset. Address General purpose timer, write only. default: 00000000 Register together form 16-bit number, GPT_CNT. Register upper byte register lower byte. GPT_CNT determines cycle time output units 2400 CLK_IN cycle time. device operates 19.2 MHz, cycle time ranges from 8.192 sec. always duty cycle. When GPT_CNT zero, output does toggle. These registers cleared hardware reset affected software reset.
Publication Release Date: August 1998 Revision
Preliminary W9330F
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Storage Temperature Power Supply Voltage Voltage Tolerant Pins Voltage Non-5V Tolerant Pins RATING +125 -0.3 +4.5 -0.3 +5.5 -0.3 +0.3 UNIT
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
Characteristics
3.0V ±10%,
PARAMETER Supply Voltage Input High Voltage Input Voltage Input Current, Normal Buffer Input Current, Buffer with Pull-up Input Current, Buffer with Pulldown Tri-state Leakage Current Output High Voltage Output High Voltage Output High Voltage Output Voltage Output Voltage Output Voltage Sleep Mode Current Freeze Mode Current Standby Current Active Current
Notes: TX_DATA Tolerant
SYMBOL VOH1 VOH2 VOH3 VOL1 VOL2 VOL3 IDD1 IDD2 IDD3 IDD4
MIN.
MAX.
UNIT
TEST CONDITIONS
-200
VOL1, VOH1 BSYNC_OUT, COD_CLK, COD_SYNC, CPU_CLK, LOCK, PLL_SW, RF_PWR, RLOCK, TX_ENV, WAKEUP VOL2,VOH2 ANTSW, CLK_OUT, GPT, VOL3, VOH3 TX_DATA PB[7:4] open-drain outputs does apply.
Preliminary W9330F
TIMING WAVEFORMS
Module Timing Specifications
PARAMETER TX_ENV High Time TX_ENV High RF_PWR High PLL_SW High TX_ENV High RF_PWR High Time RF_PWR TX_ENV RF_PWR PLL_SW TX_DATA Rate SYMBOL TERH TPTH TRTL TRPL VALUE 2532 2524 1.365 UNITS Mbps NOTE
Tpth
RF_PWR TX_ENV PLL_SW Terh Trtl Trpl
TX_DATA
Note timing values linear proportional CLK_IN frequency. Value assumes CLK_IN 19.2
Publication Release Date: August 1998 Revision
Preliminary W9330F
Timing Waveforms, continued
CODEC Interface Timing Specifications
PARAMETER CLK_IN Frequency COD_SYNC High Time COD_SYNC Cycle Time COD_CLK High Time COD_CLK Cycle Time COD_CLK High COD_SYNC High COD_CLK High Valid COD_CLK Setup Time COD_CLK Hold Time SYMBOL FCLK TCSH TCDV FCDS FCDH VALUE 19.2 6.71 0.83 1.67 0.05 0.05 0.05 0.05 UNITS NOTE
COD_SYNC
COD_CLK
Tcsh Tcdv Tcdh
Tcds
Note timing values linear proportional CLK_IN frequency. Value assumes CLK_IN 19.2
Preliminary W9330F
Timing Waveforms, continued
Interface Timing Specifications
PARAMETER Address Setup Time Address Hold Time Data Setup Time Data Hold Time
Data Output Enable Data Output Disable
SYMBOL TDOE TOFF
MIN.
MAX.
UNITS
NOTE
Pulse Width
Pulse Width
Data Output Valid High
Tdoe Toff
Publication Release Date: August 1998 Revision
Preliminary W9330F
PACKAGE DIMENSIONS
100-pin
Symbol
Dimension inches
Dimension
Min. Nom. Max. Min. Nom. Max.
0.01 0.014 0.018 0.113 0.016 0.008 0.555 0.25 2.57 0.20 0.10 13.90 0.35 2.72 0.30 0.15 0.45 2.87 0.40 0.20
Notes:
0.101 0.107 0.008 0.012 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.026 0.669 0.905 0.025 0.677 0.913 0.031 0.063
14.00 14.10 20.00 20.10 0.802 17.40 23.40 0.95
0.791 19.90 0.032 0.685 0.921 0.037
0.498 0.65 17.00 23.00 0.65 17.20 23.20 0.80 1.60
0.003
0.08
Detail Seating Plane
Dimensions include interlead flash. Dimension does include dambar protrusion/intrusion. Controlling dimension: Millimeters General appearance spec. should based final visual inspection spec.
Headquarters
Winbond Electronics (H.K.) Ltd.
803, World Trade Square, Tower Creation III, Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 First Street, Jose, 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, 115, Sec. Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: data specifications subject change without notice.
Note: CD/SS technology used W9330F developed Lanwave Components, Inc.

Winbond W9330F integrated cordless telephone controller. employs Code

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