SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR Fully integrated sing
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ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
Fully integrated single ended 3.3V LVCMOS/LVTTL outputs LVCMOS/LVTTL clock inputs redundant clock applications CLK0 CLK1 accepts following input levels: LVCMOS/LVTTL Output frequency range: 8.33MHz 125MHz range: 200MHz 500MHz External feedback "zero delay" clock regeneration Cycle-to-cycle jitter: ±100ps (typical) Output skew: 350ps (maximum) 3.3V operating supply -40°C 85°C ambient operating temperature Lead-Free package available compatible with MPC974
GENERAL DESCRIPTION
ICS87974I skew, jitter 1-to-15 LVCMOS/LVTTL Clock Generator/Zero Delay HiPerClockSBuffer member HiPerClockS family high performance clock solutions from ICS. device fully integrated three banks whose divider ratios independently controlled, providing output frequency relationships 1:1, 2:1, 3:1, 3:2, 3:2:1. addition, external feedback connection provides wide selection output-to-input frequency ratios. CLK0 CLK1 pins allow redundant clocking input dynamically switching between clock sources. ICS87974I compatible with MPC974.
Guaranteed jitter output skew characteristics make ICS87974I ideal those applications demanding well defined performance repeatability.
ASSIGNMENT
VCO_SEL VDDOC VDDOC VDDOB
nMR/OE CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL CLK0 CLK1 VDDA
VDDOB VDDOB FB_IN VDDOFB
ICS87974I
FB_SEL0 VDDOA FB_SEL1 VDDOA VDDOA
52-Lead LQFP 10mm 10mm 1.4mm package body package View
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
BLOCK DIAGRAM
SELA CLK_SEL
(Internal Pulldown) (Internal Pulldown)
CLK0 (Internal Pulldown) CLK1 (Internal Pullup) FB_IN (Internal Pullup) PLL_SEL (Internal Pullup) VCO_SEL
(Internal Pulldown)
QA0:QA4
QB0:QB4
SELB (Internal Pulldown)
QC0:QC3
SELC (Internal Pulldown)
nMR/OE (Internal Pullup)
FB_SEL1
(Internal Pulldown)
FB_SEL0 (Internal Pulldown)
CLK_EN (Internal Pullup)
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
SIMPLIFIED BLOCK DIAGRAM
CLK_EN SEL_A VCO_SEL
CLK_SEL CLK0 CLK1 FB_IN PLL_SEL SEL_B
SEL_A
QA0:QA4
SEL_B
QB0:QB4
SEL_C
SEL_C
QC0:QC3
FB_0 FB_1
FB_SEL(0:1) nMR/OE
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
Type Power Description Power supply ground. Active High Master Reset. Active output enable. When logic HIGH, internal dividers reset outputs tristated (HiZ). When logic LOW, internal dividers dividers outputs enabled. LVCMOS LVTTL interface levels. Synchronizing clock enable. When HIGH, clock outputs QAx:QCx enabled. When LOW, clock outputs QAx:QCx low. LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects between reference clock input dividers. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0. LVCMOS LVTTL interface levels. Reference clock input. LVCMOS LVTTL interface levels. Reference clock input. LVCMOS LVTTL interface levels. connect. Core supply pin. Analog supply pin. Selects divide value Bank feedback output described Pulldown Table LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank clock outputs. Output supply clock output. Clock output. LVCMOS LVTTL interface levels. Feedback input phase detector generating clocks with "zero delay". Connect Pullup LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank clock outputs. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins Bank clock outputs. Selects when HIGH. Selects when LOW. Pulldown LVCMOS LVTTL interface levels.
TABLE DESCRIPTIONS
Number Name
nMR/OE
Input
Pullup
CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL CLK0 CLK1 VDDA FB_SEL0, FB_SEL1 QA4, QA3, QA2, QA1, VDDOA VDDOFB FB_IN QB4, QB3, QB2, QB1, VDDOB QC3, QC2, QC1, VDDOC VCO_SEL
Input Input Input Input Input Input Input Input Unused Power Power Input Output Power Power Output Input Output Power Output Power Input
Pullup Pulldown Pulldown Pullup Pulldown Pulldown Pulldown Pullup
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum Typical VDD, VDDA, VDDOx 3.465V Maximum Units
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); Note Output Impedance
NOTE VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB.
TABLE OUTPUT CONTROL FUNCTION TABLE
Inputs nMR/OE CLK_EN QA0:QA4 Enable QB0:QB4 Enable Outputs QC0:QC3 Enable Enable Enable
TABLE OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL Operating Mode Bypass
TABLE INPUT FUNCTION TABLE
Inputs CLK_SEL Input CLK0 CLK1
TABLE SELECT FUNCTION TABLE
SEL_A SEL_B SEL_C
TABLE SELECT FUNCTION TABLE
Inputs FB_SEL1 FB_SEL0 Outputs
TABLE SELECT FUNCTION TABLE
Inputs VCO_SEL fVCO VCO/2 VCO/4
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
4.6V -0.5V -0.5V VDDO 0.5V 73.2°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDOx IDDA
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage; NOTE Power Supply Current Analog Supply Current
Test Conditions
Minimum 3.135 2.935 3.135
Typical
Maximum 3.465 3.465 3.465
Units
Output Supply Current; NOTE IDDOx NOTE VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB. NOTE IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOFB
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol
Parameter SEL_A:SEL_C, nMR/OE, VCO_SEL, PLL_SEL, Input CLK_SEL, CLK_EN, High Voltage FB_SEL0, FB_SEL1, FB_IN CLK0, CLK1 SEL_A:SEL_C, nMR/OE, VCO_SEL, PLL_SEL, Input CLK_SEL, CLK_EN, Voltage FB_SEL0, FB_SEL1, FB_IN CLK0, CLK1 FB_SEL0, FB_SEL1, SEL_A:SEL_C, CLK0, Input VCO_SEL, CLK_SEL High Current CLK1, FB_IN, nMR/OE, PLL_SEL, CLK_EN FB_SEL0, FB_SEL1, SEL_A:SEL_C, CLK0, Input VCO_SEL, CLK_SEL Current CLK1, FB_IN, nMR/OE, PLL_SEL, CLK_EN Output High Voltage; NOTE Output Voltage; NOTE
Test Conditions
Minimum
Typical
Maximum
Units
3.465V 3.465V 3.465V 3.465V -100
NOTE Outputs terminated with VDDOx/2.
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol fMAX fVCO Parameter Output Frequency Lock Range; NOTE SYNC Feedback Propagation Delay; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter NOTE Lock Time Output Rise/Fall Time Output Pulse Width Output Enable Time 0.8V 2.0V 0.15 tPeriod/2 tPeriod/2 Test Conditions PLL_SEL 3.3V, fREF 50MHz Measured rising edge VDDO/2 -250 Minimum Typical Maximum ±100 tPeriod/2 Units
tsk(o) tjit(cc)
Output Disable Time tDIS parameters measured fMAX unless noted otherwise. NOTE Measured from VDD/2 point input theVDDOx/2 output. NOTE Defined time difference between input reference clock average feedback input signal when locked input reference frequency stable. NOTE Defined skew within bank with equal load conditions. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDOx/2. NOTE This parameter defined accordance with JEDEC Standard NOTE Measured peak-to-peak.
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
VDD, VDDA, VDDOx
SCOPE
DDOX
LVCMOS
DDOX
sk(o)
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
OUTPUT SKEW
DDOX
DDOX
DDOX
0.8V
0.8V
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
VDDOX
QAx, QBx, QCx,
PERIOD
PERIOD
OUTPUT PULSE WIDTH/PULSE WIDTH PERIOD
87974BYI
VDDOX
QAx, QBx, QCx,
tcycle
Clock Outputs
OUTPUT RISE/FALL TIME
VDDOX
CLK0, CLK1
VDDOx
SYNC
FEEDBACK PROPAGATION DELAY
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87974I provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDOx should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA pin.
3.3V .01µF VDDA .01µF
FIGURE POWER SUPPLY FILTERING
LAYOUT GUIDELINE
schematic ICS87974I layout example used this layout guideline shown Figure ICS87974I recommended board layout this example shown Figure This layout example used general guideline. layout actual system will depend selected component types, density components, density traces, stack P.C. board.
VDDO VCO_SEL Receiver
Receiver
3.3V
Reset pulse pull
CLK_EN SELB SELC PLL_SEL SELA CLK_SEL
3.3V LVCMOS Driver 0.01u
FB_SEL0 VDDOA FB_SEL1 VDDOA VDDOA
CLK_EN SELB SELC PLL_SEL SELA CLK_SEL CLK0 CLK1 VDDA
VCO_SEL VDDOC VDDOC VDDOB
VDDOB VDDOB FB_IN VDDOFB
Receiver
0.01u CLK_EN PLL_SEL SELA SELB SELC CLK_SEL
87974
Receiver
(U1-17)
VDDO
(U1-22)
0.1uF
(U1-26)
0.1uF
(U1-28)
0.1uF
(U1-33)
0.1uF
(U1-37)
0.1uF
(U1-41)
0.1uF
(U1-45)
0.1uF
(U1-49)
0.1uF
0.1uF
Space (i.e. intstalled) Example Reconfigurable Logic Control Input
FIGURE ICS87974I LVCMOS/LVTTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
87974BYI
REV. OCTOBER 2004
following component footprints used this layout example: resistors capacitors size 0603.
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. series termination resistors should located close driver pins possible.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VDDA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace
VDDO
ICS87974
VDDA
FIGURE BOARD LAYOUT ICS87974I
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87974I 4225
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.22 0.09 MINIMUM NOMINAL -1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC -0.75 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
Marking ICS87974BYI ICS87974BYI ICS87974BYILN ICS87974BYILN Package Lead LQFP Lead LQFP Tape Reel Lead "Lead-Free/Annealed" LQFP Lead "Lead-Free/Annealed" LQFP Tape Reel Count tray tray Temperature -40°C 85°C -40°C 85°C -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87974BYI ICS87974BYIT ICS87974BYILN ICS87974BYILNT
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87974BYI
REV. OCTOBER 2004
ICS87974I
SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET Description Change Added Layout Guideline Board Layout. Added simplified block diagram. Revised Package Outline drawing. Corrected Package Dimensions table correspond with Package Outline drawing. Update format throughout datasheet. Description table updated nMR/OE VDDOx descriptions. Power Supply table changed parameter "Core." from "Positive.". Changed max. limit from 105mA max. 118mA max., IDDOx from 20mA max. 22mA max. Characteristics Table changed max. typical. Select Function Table switched FB_SELx headings, FB_SEL1 heading column FB_SEL0 heading column Characteristics Table added ROUT, Output Impedance row. Revised Package Outline. Change from rev. marking throughout data sheet. Change max. temperature 70°C down from 85°C throughout data sheet. Power Supply Characteristics table adjusted: VDDA from 3.135V min. 2.9375V min., from 118mA max. 125mA max., IDDOX from 22mA max. 25mA max. Through data sheet maximum temperature changed from 70°C 85°C. Power Supply Characteristics Table changed from 125mA max. 121mA max. IDDOx changed from 25mA max. 24mA max. Swaped labels FB_SEL0 FB_SEL1 Block Diagram Simplified Block Diagram. Corrected Select Function Table. Ordering Information Table added Lead-Free number. 5/15/03 7/9/03 Date 4/2/02 4/4/02 11/15/02
Table
Page
3/20/03
7/23/03
8/4/03
2/9/04 6/9/04 10/11/04
87974BYI
REV. OCTOBER 2004
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