PM73122 PM73123 PM73124 AAL1GATOR-32 PROGRAMMER'S GUIDE PM73
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AAL1GATOR PRODUCT FAMILY AAL1GATOR-32
LINK CES/DBCES AAL1
PROGRAMMER'S GUIDE
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REVISION HISTORY Issue Issue Date January 2000 April 2001 Details Change Created document. Corrected Configuration Steps Flow Chart. Clarified tributary mapping Extract Tributary Mapping Configuration section. Corrected incorrect reference made Section 8.4.5 Line Clock Source.
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CONTENTS INTRODUCTION. SCOPE. TARGET AUDIENCE. NUMBERING CONVENTIONS DEVICE NAMING CONVENTIONS
REFERENCES. AAL1GATOR PRODUCT FAMILY OVERVIEW AAL1GATOR-32. AAL1GATOR-8. AAL1GATOR-4.
REGISTER DESCRIPTION MEMORY MAPPED REGISTERS. NORMAL MODE REGISTERS.
OPERATIONAL PROCEDURES.11 SOFTWARE RESET 5.1.1 CHIP SOFTWARE RESET.11 5.1.2 A1SP SOFTWARE RESET CONFIGURATION PROCEDURE. 5.2.1 STATE HARDWARE RESET 5.2.2 STATE CHIP A1SP SOFTWARE RESET 5.2.3 STATE A1SP SOFTWARE RESET. 5.2.4 STATE NORMAL OPERATING MODE
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DEVICE IDENTIFICATION.
CONFIGURING UTOPIA INTERFACE COMMON UTOPIA INTERFACE CONFIGURATION. UTOPIA SOURCE INTERFACE CONFIGURATION UTOPIA SINK INTERFACE CONFIGURATION BASED UTOPIA UTOPIA LOOPBACK 6.4.1 LOOPBACK SETUP EXAMPLE MULTI-ADDRESS MODE.
DATA STRUCTURES. TRANSMIT DATA STRUCTURES. 7.1.1 P_FILL_CHAR. 7.1.2 T_SEQNUM_TBL 7.1.3 T_COND_SIG. 7.1.4 T_COND_DATA. 7.1.5 RESERVED (TRANSMIT SIGNALING BUFFER). 7.1.6 T_OAM_QUEUE 7.1.7 T_QUEUE_TBL 7.1.8 RESERVED (TRANSMIT DATA BUFFER) RECEIVE DATA STRUCTURES 7.2.1 R_OAM_QUEUE_TBL 7.2.2 R_OAM_CELL_CNT 7.2.3 R_DROP_OAM_CELL. 7.2.4 R_SRTS_CONFIG. 7.2.5 R_CRC_SYNDROME.
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7.2.6 R_CH_TO_QUEUE_TBL. 7.2.7 R_COND_SIG 7.2.8 R_COND_DATA 7.2.9 RESERVED (RECEIVE SRTS QUEUE). 7.2.10 RESERVED (RECEIVE SIGNALING BUFFER) 7.2.11 R_QUEUE_TBL. 7.2.12 R_OAM_QUEUE 7.2.13 RESERVED (RECEIVE DATA BUFFER). CONFIGURING LINE INTERFACE CONVENTIONS REGISTER SUMMARY. DIRECT SPEED MODE. 8.3.1 LINE FORMAT FRAME STRUCTURE 8.3.2 LINE CLOCK SOURCE 8.3.3 SYNCHRONIZATION 8.3.4 SIGNALING. 8.3.5 OTHER PER-LINE OPTIONS MODE. 8.4.1 PROGRAMMING INTERFACE. 8.4.2 GENERAL CONFIGURATION 8.4.3 EXTRACT BLOCK CONFIGURATION .115 8.4.4 INSERT BLOCK CONFIGURATION. 8.4.5 LINE CLOCK SOURCE 8.4.6 OTHER PER-LINE OPTIONS
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H-MVIP MODE 8.5.1 LINE FORMAT FRAME STRUCTURE 8.5.2 LINE CLOCK SOURCE 8.5.3 SYNCHRONIZATION 8.5.4 SIGNALING.
HIGH SPEED MODE 8.6.1 HIGH SPEED LINE CONFIGURATION. 8.6.2 LINE CLOCK SOURCE 8.6.3 OTHER PER-LINE OPTIONS
CONFIGURING A1SP BLOCKS SENDING CELLS ADDING QUEUES A1SP CLOCK CONFIGURATION
CONFIGURING INTERFACE INTERRUPTS 11.1 11.2 11.3 11.4 11.5 MASTER INTERRUPTS UTOPIA INTERRUPTS INTERFACE INTERRUPTS LINE INTERFACE INTERRUPTS A1SP INTERRUPTS 11.5.1 A1SPN RECEIVE STATUS FIFO 11.5.2 A1SPN TRANSMIT IDLE STATE FIFO 11.5.3 RECEIVE QUEUE ERROR ENABLES.
IDLE CHANNEL DETECTION CONFIGURATION STATUS.
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12.1 12.2 12.3 12.4 12.5 12.6 12.7
RECEIVE CHANNEL ACTIVE TABLE. RECEIVE PENDING TABLE RECEIVE CHANGE POINTER TABLE TRANSMIT CHANNEL ACTIVE TABLE PATTERN MATCHING LINE CONFIGURATION IDLE DETECTION CONFIGURATION TABLE. CAS/PATTERN MATCHING CONFIGURATION 12.7.1 MATCHING FORMAT 12.7.2 PATTERN MATCHING FORMAT. 12.7.3 PROCESSOR IDLE DETECTION FORMAT
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LIST FIGURES FIGURE AAL1GATOR-32 BLOCK DIAGRAM FIGURE AAL1GATOR-8 BLOCK DIAGRAM FIGURE AAL1GATOR-4 BLOCK DIAGRAM FIGURE AAL1GATOR MEMORY MAP. FIGURE A1SP SRAM MEMORY FIGURE CONFIGURATION STEPS FLOW CHART FIGURE UTOPIA INTERFACE BLOCK DIAGRAM FIGURE CELL HEADER INTERPRETATION. FIGURE UTOPIA LEVEL MULTI-ADDRESS MODE WITH BASED LOOPBACK FIGURE TRANSMIT DATA STRUCTURES MEMORY FIGURE SDF-MF FORMAT T_SIGNALING BUFFER FIGURE RECEIVE DATA STRUCTURES FIGURE R_CRC_SYNDROME MASK TABLE LEGEND. FIGURE LINE INTERFACE BLOCK ARCHITECTURE FIGURE CAPTURE SIGNALING BITS FIGURE OUTPUT SIGNALING BITS FIGURE CAPTURE SIGNALING BITS FIGURE OUTPUT SIGNALING BITS. FIGURE BLOCK ARCHITECTURE FIGURE ADDQ_FIFO WORD STRUCTURE FIGURE INTERRUPT HIERARCHY.
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LIST TABLES FIGURE AAL1GATOR-32 BLOCK DIAGRAM FIGURE AAL1GATOR-8 BLOCK DIAGRAM FIGURE AAL1GATOR-4 BLOCK DIAGRAM FIGURE AAL1GATOR MEMORY MAP. FIGURE A1SP SRAM MEMORY FIGURE CONFIGURATION STEPS FLOW CHART FIGURE UTOPIA INTERFACE BLOCK DIAGRAM FIGURE CELL HEADER INTERPRETATION. FIGURE UTOPIA LEVEL MULTI-ADDRESS MODE WITH BASED LOOPBACK FIGURE TRANSMIT DATA STRUCTURES MEMORY FIGURE SDF-MF FORMAT T_SIGNALING BUFFER FIGURE RECEIVE DATA STRUCTURES FIGURE R_CRC_SYNDROME MASK TABLE LEGEND. FIGURE LINE INTERFACE BLOCK ARCHITECTURE FIGURE CAPTURE SIGNALING BITS FIGURE OUTPUT SIGNALING BITS FIGURE CAPTURE SIGNALING BITS FIGURE OUTPUT SIGNALING BITS. FIGURE BLOCK ARCHITECTURE FIGURE ADDQ_FIFO WORD STRUCTURE FIGURE INTERRUPT HIERARCHY.
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INTRODUCTION Scope AAL1gator-32/8/4 Programmer's Guide intended describe configurable features operation AAL1gator-32/8/4 from programmer's perspective. This document cover applications AAL1gator-32/8/4. Please contact PMC-Sierra Applications Engineer specific uses covered this document. This document supplement AAL1gator-32 [1], AAL1gator-8 [2], AAL1gator-4 Longform Datasheets. Both longform datasheet programmer's guide should studied together interface AAL1gator-32/8/4 embedded processor. case discrepancy between programmer's guide datasheet, datasheet will take precedence. This document supplement AAL1gator-32/8/4 Software Driver User's Manual engineers need detailed information register accesses programming procedures.
Target Audience This document been prepared engineers that design-in AAL1gator-32/8/4 require quick reference programming AAL1gator-32/8/4. assumed that reader familiar with ATM, AAL1, circuit emulation, line interface, UTOPIA interface technologies.
Numbering Conventions following numbering conventions used throughout this document: Binary Decimal Hexadecimal 1010b, "011", 129, 0x80120,
Device Naming Conventions From this point forward, term AAL1gator shall refer three AAL1gator-32/8/4 variants, while features functionality specific each variant shall name individual device.
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REFERENCES PMC-1981419, PMC-Sierra, Inc., "AAdaptation Layer Segmentation Reassembly Processor-32 Datasheet", September 1999, Issue PMC-2000097, PMC-Sierra, Inc., "AAdaptation Layer Segmentation Reassembly Processor-8 Datasheet", January 2000, Issue PMC-2000098, PMC-Sierra, Inc., "AAdaptation Layer Segmentation Reassembly Processor-4 Datasheet", January 2000, Issue AForum, UTOPIA, ATM-PHY Layer Specification, Level 2.01, Foster City, USA, March 1994. AForum, UTOPIA, ATM-PHY Layer Specification, Level 1.0, Foster City, USA, June 1995. PMC-1980577, PMC-Sierra, Inc., "SATURN Compatible Scaleable Bandwidth Interconnect (SBI) Specification", October 1998, Issue
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AAL1GATOR PRODUCT FAMILY OVERVIEW AAL1 Segmentation Reassembly (SAR) Processor (AAL1gator-32/8/4) highly integrated flexible monolithic single chip device that provides DS1, DS3, STS-1/STM-0 line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external SRAM storage configuration, user data, statistics. device provides microprocessor interface configuration, management, statistics gathering. PMC-Sierra also offers software device control package AAL1gator-32/8/4 device.
AAL1gator-32 AAL1gator-32 contains four AAL1 Processors (A1SP) which work parallel. A1SP blocks interface common UTOPIA interface side Line Interface block other side which configured support direct clock data, H-MVIP, mode. A1SP blocks share interface other A1SP blocks share other interface. processor Interface block which also contains external clock control interface shared blocks. AAL1gator-32 ideal applications such multi-service Aswitches, Aaccess concentrators, digital cross connects, computer telephony chassis with Ainfrastructure, wireless local loop back hauls, APassive Optical Network equipment. functional blocks AAL1gator-32 shown Figure
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Figure AAL1gator-32 Block Diagram
RAM2_ADSCB RAM2_A[17:0] RAM2_D[15:0] RAM2_PAR[1:0] RAM2_WEB[1:0] RAM2_CSB RAM2_OEB
SYSCLK NCLK TL_CLK_OE TL_CLK[15:0] RL_CLK[15:0] CRL_CLK CTL_CLK
Line Interface Clock
RSTB SCAN_ENB SCAN_MODEB TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_CLAV TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_CLAV RATM_CLK TPHY_ADD[4:0]
RAM2 Interface
A1SP
LINE_MODE[1:0] ADETECT AACTIVE REFCLK C1FP DDATA[7:0] ADATA[7:0] AJUST_REQ
A1SP
UTOPIA Interface
H-MVIP Speed High Speed
TL_DATA[15:0] TL_SYNC[15:0] TL_SIG[15:0] RL_DATA[15:0] RL_SYNC[15:0] RL_SIG[15:0]
A1SP
A1SP
JTAG
Interface
Processor Interface
External Clock Interface
RAM1_ADSCB RAM1_A[17:0] RAM1_D[15:0] RAM1_PAR[1:0] RAM1_WEB[1:0] RAM1_CSB RAM1_OEB
AAL1gator-8 AAL1gator-8 reduced link number version AAL1gator-32. AAL1gator-8 provides power, DBCES capable, eight link circuit emulation applications such Integrated Access Devices (IADs), AMultiservice Access Switches, Optical Networking Units base stations wireless networks. AAL1gator-8 provides eight DS1/E1 links single DS3/E3/STS-1/STM-0 line interface access Anetwork. line interface configured support direct clock data H-MVIP mode. functional blocks AAL1gator-8 shown Figure
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CGC_DOUT[3:0] CGC_LINE[4:0] ADAP_STB SRTS_STB CGC_VALID CGC_SER_D
A[19:0] D[15:0] ACKB INTB
TRST
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Figure AAL1gator-8 Block Diagram
SYSCLK NCLK TL_CLK_OE TL_CLK[7:0] RL_CLK[7:0] CRL_CLK CTL_CLK
Clock
RSTB SCAN_ENB SCAN_MODEB TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_CLAV TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_CLAV RATM_CLK TPHY_ADD[4:0]
Line Interface
H-MVIP
TL_DATA[7:0] TL_SYNC[7:0] TL_SIG[7:0] RL_DATA[7:0] RL_SYNC[7:0] RL_SIG[7:0]
A1SP
UTOPIA Interface
Direct
JTAG
Interface
Processor Interface
External Clock Interface
RAM1_ADSCB RAM1_A[16:0] RAM1_D[15:0] RAM1_PAR[1:0] RAM1_WEB[1:0] RAM1_CSB RAM1_OEB
AAL1gator-4 AAL1gator-4 reduced link number version AAL1gator-32/8. AAL1gator-4 provides power, DBCES capable, four link circuit emulation applications such Integrated Access Devices (IADs), AMultiservice Access Switches, Optical Networking Units base stations wireless networks. AAL1gator-4 pin-compatible version AAL1gator-8 with support four DS1/E1 links single DS3/E3/STS-1/STM-0 link. line interface configured support direct clock data H-MVIP mode. AAL1gator-
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CGC_DOUT[3:0] CGC_LINE[3:0] ADAP_STB SRTS_STB CGC_VALID CGC_SER_D
A[19:0] D[15:0] ACKB INTB
TRST
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targeted link applications such Optical Networking Units base stations wireless networks. functional blocks AAL1gator-4 shown Figure Figure AAL1gator-4 Block Diagram
RL_CLK[3:0] TL_CLK_OE TL_CLK[3:0]
CRL_CLK
RSTB SCAN_ENABLE TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_FULLB TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_EMB RATM_CLK TPHY_ADD[4:0] TL_DATA[3:0] TL_SYNC[3:0] TL_SIG[3:0] RL_DATA[3:0] RL_SYNC[3:0]
CTL_CLK
SYSCLK
NCLK
Clock
Line Interface
LINE_MODE
H-MVIP
UTOPIA Interface A1SP
Direct Mode
RL_SIG[3:0]
JTAG
Interface
Processor Interface
External Clock Interface
RAM_ADSCB
CGC_DOUT[3:0]
D[15:0]
RAM_PAR[1:0]
RAM_WEB[1:0]
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CGC_LINE[3:0]
CGC_SER_D
TRST
RAM_CSB
RAM_D[15:0]
A[19:0]
RAM_A[16:0]
CGC_VALID
ADAP_STB
SRTS_STB
ACKB
RAM_OEB
INTB
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REGISTER DESCRIPTION microprocessor interface used configure monitor AAL1gator. address signals (A[19:0]) provide address while bi-directional data signals (D[15:0]) provide data allow AAL1gator device interface external microprocessor. Both read write transactions supported. microprocessor interface block provides normal test mode registers which internal AAL1gator, well memory mapped registers which mostly contained external SRAM. normal mode registers memory mapped registers required normal operation. Please refer datasheets [1,2,3] information regarding test mode registers. Unless otherwise specified, AAL1gator registers described using convention REGISTER_NAME (20-bit hexadecimal address). Normal mode registers specified full name mnemonic while memory mapped registers have mnemonic only. general memory AAL1gator register shown Figure Figure shows memory region broken into five blocks. first four blocks, A1SP0 A1SP3, memory mapped registers which mostly contained within SRAM. fifth block, Internal (Normal Mode) Registers, composed configuration registers common entire chip that contained internally chip. A1SP1 through A1SP3 only used AAL1gator-32. However, same address space used three devices maintain software compatibility. Figure AAL1gator Memory
0x00000 0x1FFFF 0x20000 0x3FFFF 0x40000 0x5FFFF 0x60000 0x7FFFF 0x80000 0xBFFFF 0xC0000 0xFFFFF A1SP SRAM A1SP SRAM A1SP SRAM A1SP SRAM Internal Registers Test Registers AAL1gator-32 Only
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Memory Mapped Registers Memory mapped registers mostly contained within SRAM used line configuration configuration transmit receive structures each A1SP. Figure shows memory A1SP block within SRAM. AAL1gator-32, four A1SP blocks identical accessed taking 17-bit relative address shown Figure appending 2-bit A1SP identifier front select particular A1SP block. Figure A1SP SRAM Memory
0x00000 0x0001F 0x00020 0x07FFF 0x08000 0x1FFFF Control Registers Transmit Data Structures Receive Data Structures
2-bit A1SP identifier, with A[19] decoded follows: A[18:17] "00" A[18:17] "01" A[18:17] "10" A[18:17] "11" A1SP0 A1SP1 A1SP2 A1SP3
Notes Memory Mapped Register Bits: memory locations readable writable. Although once processing begun, writing some locations restricted prevent corruption structures data buffers used AAL1gator. restricted locations designated below. ports marked "Reserved" must initialized initial setup. Software modifications these locations after setup will cause incorrect operation. read/write port bits marked "Not used" must written with value maintain software compatibility with future versions.
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read-only port bits marked "Not used" driven with should masked software maintain compatibility with future versions.
Normal Mode Registers Normal mode registers used configure monitor operation AAL1gator. Normal mode registers selected when A[19] high A[18] low. Table shows normal mode register memory along with section this document that describes each block registers. Table Normal Mode Register Memory Address 0x8000X 0x8010X 0x8012X 0x80200 0x80FFF 0x81000 0x812FF 0x82000 0x82FFF Register Description Command Registers Interface Registers UTOPIA Interface Registers Line Interface Registers Interrupt Status Registers Idle Channel Configuration Status Registers Section
Notes Normal Mode Register Bits: Writing values into unused register bits effect. However, ensure software compatibility with future, feature-enhanced versions product, unused register bits must written with logic zero unless stated otherwise. Reading back unused bits produce either logic logic zero; hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling AAL1gator determine programming state block. Writable normal mode register bits cleared logic zero upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect AAL1gator operation unless otherwise noted.
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Certain register bits reserved. ensure that AAL1gator operates intended, reserved register bits must written with their default value indicated register description.
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OPERATIONAL PROCEDURES This section describes procedure reset AAL1gator software initialize AAL1gator before entering operating state.
Software Reset There types software resets AAL1gator: chip software reset A1SP software reset.
5.1.1 Chip Software Reset chip software reset applied setting SW_RESET Reset Device Register (0x80000). When set, entire device held reset including other registers. While set, external SRAM accessed. Applying chip software reset also puts A1SPs into reset state. SW_RESET Chip active. Chip reset. Function
Please State section 5.2.2 effects chip software reset steps that need taken before chip software reset removed. 5.1.2 A1SP Software Reset A1SP software reset applied A1SPn setting An_SW_RESET A1SPn Command Register (0x80010, .,13). When set, corresponding A1SP held reset. An_SW_RESET A1SPn active. A1SPn reset. Function
Please State section 5.2.3 effects A1SP software reset steps that need taken before A1SP software reset removed.
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Configuration Procedure This section describes procedure necessary initialize AAL1gator after hardware reset (i.e. initial power change configuration AAL1gator time. description each programming state that exists process provided along with steps necessary proceed next state. flow chart sequence steps shown Figure shown, three reset states automatically entered when hardware reset, chip software reset, A1SPn software reset applied. Note: configuration procedure described recommended procedure programming AAL1gator. questions relating alternative sequences programming AAL1gator, please contact PMC-Sierra Applications Engineer.
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Figure Configuration Steps Flow Chart
Entire Chip A1SP
Hardware Reset
Hardware Reset A1SPn Software Reset LINE_MODE Hardware Pins
A1SPn Software Reset
Clear A1SPn SRAM zeros
Clear Hardware Reset Initialize Transmit Receive Data Structures Chip Software Reset Chip A1SP Software Reset
Configure Internal Line A1SP Software Interface Software Reset A1SPRegisters Reset A1SP Software Reset Configure LIN_STR_MODE HS_LIN_REG
Poll DLL_STAT_REG
set?
An_CMDREG_ATTN, A1SPn reads configuration
Clear Chip Software Reset
Clear A1SPn Software Reset
Configure UTOPIA Registers
Normal Operation
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5.2.1 State Hardware Reset hardware reset state entered when RSTB input forced low. This state following characteristics: internal registers (0x80000 0xBFFFF) reset their default states. UTOPIA Interface powers with outputs tri-stated. TLCLK_OE input controls whether TL_CLK lines inputs outputs between time hardware reset reading CLK_SOURCE_TX bits step State
following steps need taken proceed next state: line mode operation needs setup. LINE_MODE input pins should tied certain level initial hardware reset changed while reset state. section encoding LINE_MODE pins. line mode cannot changed software. Take AAL1gator hardware reset forcing RSTB high. 5.2.2 State Chip A1SP Software Reset Chip Software Reset state automatically entered after hardware reset removed, asserted setting SW_RESET Reset Device Register (0x80000). A1SPs also automatically reset when this state entered. This state following characteristics: entire chip with exception microprocessor interface reset. chip inactive processing data. External memory accessed. Changes internal registers will take effect until Chip Software Reset removed.
following steps need taken proceed next state: Wait clock periods slowest clock before attempting write other register. exception this rule register port. Poll Control Status Register (0x84003) until this set. This ensures that internal SYSCLK aligned with external SYSCLK before proceeding.
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Configure UTOPIA Interface registers. section detailed description configurable features UTOPIA Interface. Remove Chip Software Reset writing SW_RESET Reset Device Register (0x80000). 5.2.3 State A1SP Software Reset A1SPs still software reset after Chip Software Reset removed. individual A1SP also enter A1SP Software Reset state setting An_SW_RESET corresponding A1SPn Command Register (0x80010, 13). This state following characteristics: External memory accessed. line interface configured mode indicated LINE_MODE pins will only driving data lines and/or queues disabled.
following steps need taken each A1SP reset before entering normal operating mode: Clear section memory allocated reset A1SP zeros. A1SPs reset, then clear entire SRAM zeros. Figure memory AAL1gator. number data structures used device reserved areas depends this initialization. section detailed description these register accesses. Initialize transmit receive data structures writing registers with address offset 0x00020 0x1FFFF each A1SP SRAM memory map. Some memory locations must only this state (such T_SEQNUM_TBL R_CRC_SYNDROME) while others also changed during normal operation. section description transmit receive data structures. Figure A1SP SRAM memory map. Configure internal line interface registers. section detailed description configurable features Line Interface. Initialize memory mapped registers (LIN_STR_MODE HS_LIN_REG) which contain line configuration. section detailed description these register accesses. An_CMDREG_ATTN A1SPn Command Register (0x80010, that configuration data written LIN_STR_MODE registers HS_LIN_REG read A1SP.
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Poll An_CMDREG_ATTN until read back ensure that configuration read operation complete. Remove A1SP Software Reset writing An_SW_RESET A1SPn Command Register (0x80010, 13). 5.2.4 State Normal Operating Mode After removing A1SP Software Reset(s), device reads data structures from memory enters correct operating mode. R_CH_TO_QUEUE_TBL will then begin SYSCLK cycle initialization, which resets each timeslot playing conditioned data. this point queues initialized needed. Queues added writing An_ADDQ_REG (0x80020, with number queue added. There queue FIFO A1SP. section details. Note: Once processing begun, writing some locations restricted prevent corruption structures data buffers used AAL1gator. Device Identification Software identify AAL1gator reading DEV_ID[3:0] DEV_TYPE[2:0] bits Reset Device Register (0x80000). DEV_ID bits read provide binary number indicating feature version AAL1gator device. These bits incremented only features added revision chip. DEV_TYPE bits read distinguish particular AAL1gator device from other members AAL1gator family devices shown Table Table DEV_TYPE Encoding Device AAL1gator-4 AAL1gator-8 AAL1gator-32 DEV_TYPE[2:0]
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CONFIGURING UTOPIA INTERFACE UTOPIA Interface (UI) manages responds control signals UTOPIA passes cells from UTOPIA four A1SP blocks. Both 8-bit 16-bit UTOPIA interfaces with optional single parity supported. 8-bit 16-bit Any-PHY slave interface also supported. Each direction configured independently configuration registers. following UTOPIA/Any-PHY modes supported. UTOPIA Level ATM, Master (8-bit only) UTOPIA Level PHY, Slave 16-bit) UTOPIA Level PHY, Slave 16-bit) Any-PHY 16-bit) Slave
UTOPIA Level UTOPIA Level defines interface between Physical Layer (PHY) upper layers such ALayer various management entities. definition allows common interface Asubsystems across wide range speeds media types OC-3c rates (155 Mbps). UTOPIA Level restriction that only device supported [4]. AAL1gator devices configured 8-bit UTOPIA Level Master 8-bit 16-bit UTOPIA Level Slave. UTOPIA Level UTOPIA Level enhances UTOPIA Level defining physical operation interface support devices with aggregate data rate Mbps [5]. With AAL1gator-32 UTOPIA Level mode, device generally responds UTOPIA single port device. However possible configure sink direction (i.e. direction from UTOPIA AAL1gator) 4-port device where each A1SP different port.
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Any-PHY Any-PHY interface bit, that support Mbps bandwidth. using very overhead cycles transmit receive packets Any-PHY interface suitable designs that need scale OC-12 (622 Mbps) bandwidths. Like POS-PHY UTOPIA interfaces, Any-PHY interface master/slave bus. Any-PHY master interface with multiple devices. Any-PHY interface extends beyond device limit UTOPIA Level through in-band addressing. extra word indicating port address, prepended front each cell that transmitted received. AAL1gator devices support Any-PHY interface. Block Diagram block consists functions: Data Source Interface (SRC_INTF), Data Sink Interface(SNK_INTF), 4-cell FIFO (FF4CELL), 3-cell FIFO (FF3CELL), UMUX, UI_REG. Figure block diagram AAL1_UI block.
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Figure UTOPIA Interface Block Diagram
UTOPIA Interface (UI) Block UMUX SRC_INTF FF4CELL
Signals to/from each A1SP block
TXUTOPIA SIGNALS
UTOPIA Interface FIFO Output Logic FF3CELL
Prioritization FIFO Input Logic
SNK_INTF FF4CELL UTOPIA Interface FIFO Input Logic
Signals to/from each A1SP block
RXUTOPIA SIGNALS
DEMUX FIFO Output Logic UI_REG
There very little setup required configure UTOPIA Interface. typical operation, UI_COMN_CFG_REG, UI_SRC_CFG_REG, UI_SNK_CFG_REG need written select mode operation UI_SRC_ADD_CFG UI_SNK_ADD_CFG need programmed predefined address device. Once registers written with proper configuration information, UI_EN UI_COMN_CFG_REG should enable normal operation. Aside from normal configurations, block also placed loopback where cells received interface transmitted back onto interface. following registers control configuration UTOPIA interface:
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Address 0x80120 0x80121 0x80122 0x80123 0x80124 0x80125
Register Description UTOPIA Common Configuration Register UTOPIA Source Configuration Register UTOPIA Sink Configuration Register UTOPIA Source Address Configuration Register UTOPIA Sink Address Configuration Register UTOPIA UTOPIA Loopback Register
Register Mnemonic UI_COMN_CFG UI_SRC_CFG UI_SNK_CFG UI_SRC_ADD_CFG UI_SNK_ADD_CFG UI_U2U_LOOP_VCI
Common UTOPIA Interface Configuration General configuration enabling UTOPIA Interface controlled Common Configuration Register (0x80120). Please note that every time UTOPIA Interface needs reprogrammed, recommended Chip Software Reset state described section 5.2.2. default configuration follows: UI_EN U2U_LOOP SHIFT_VCI Register Common Configuration Register (0x80120) Common Configuration Register (0x80120) Common Configuration Register (0x80120) Value
VCI_U2U_LOOP Common Configuration Register (0x80120) VPI_MODE_EN Common Configuration Register (0x80120)
UTOPIA Interface disabled default state. addition, remote loopback based loopback modes disabled, neither shifting mode used cell header interpretation. Enabling UTOPIA Interface UI_EN enables both source side sink side UTOPIA Interface. This resets disabled state that chip resets with UTOPIA outputs tristated. Once modes have been configured interface
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enabled, then outputs will drive their correct values. other registers affected this bit. UI_EN Function disabled. logic held reset FIFOs cleared. AAL1gator will respond UTOPIA interface. enabled both directions.
UTOPIA UTOPIA Loopback Modes AAL1gator supports forms UTOPIA UTOPIA loopback; global loopback, where cells looped, based loopback, where only specific used loopback cells. 3-cell FIFO used loopback. global loopback mode, cells received UTOPIA block sent back onto UTOPIA (regardless single multi-addressing mode). Global loopback enabled setting U2U_LOOP bit: U2U_LOOP normal mode. global loopback mode Function
based loopback mode, cell received with that matches loopback sent back onto UTOPIA bus. loopback programmable writing U2U_LOOP_VCI register (please section 6.4). based loopback enabled setting VCI_U2U_LOOP bit: VCI_U2U_LOOP Function normal mode. based loopback mode
Cell Header Interpretation UMUX blocks serves bridge between four A1SP blocks SNK_INTF SRC_INTF blocks.
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determine which A1SP forward received cell, UMUX looks bits each cell (unless UTOPIA Level multi-port mode Any-PHY mode, which case bottom address bits used). SHIFT_VCI VP_MODE_EN bits determine interpretation bits cell header, shown Figure Figure Cell Header Interpretation
SHIFT_VCI=0 VP_MODE_EN=0
Ignored Ignored A1SP Data Line
Queue
SHIFT_VCI=1 VP_MODE_EN=0
Ignored A1SP Data
Ignored
Line
Ignored
Queue
SHIFT_VCI=X VP_MODE_EN=1
Ignored
A1SP
Line
Ignored
Ignored
Ignored
three possible interpretations described below: When SHIFT_VCI VP_MODE_EN low: VCI[10:9] used select A1SP When VCI[8] set, cell data cell; when VCI[8] low, cell cell VCI[7:0] used queue number VCI[8]
When SHIFT_VCI VP_MODE_EN low: VCI[14:13] used select A1SP
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When VCI[12] set, cell data cell; when VCI[12] low, cell cell VCI[11:4] used queue number VCI[12]
When VP_MODE_EN set: VPI[4:3] used select A1SP VPI[2:0] selects line within A1SP Queue will assumed bits need used indicate queue number then interpret cell cell place buffer
Note: VP_MODE_EN only lines mode. UTOPIA Source Interface Configuration UTOPIA Source Interface (SRC_INTF) block conveys cells received from UMUX block UTOPIA interface. Configuration UTOPIA source side interface controlled Source Configuration Register (0x80121). Please note that every time UTOPIA Interface needs reprogrammed, recommended Chip Software Reset state described section 5.2.2. default configuration follows: ANY-PHY_EN EVEN_PAR 16_BIT_MODE CS_MODE_EN Register Value 0x0000
UTOP_MODE[1:0] Source Configuration Register (0x80121) Source Configuration Register (0x80121) Source Configuration Register (0x80121) Source Configuration Register (0x80121) Source Configuration Register (0x80121)
CFG_ADDR[15:0] Slave Source Address Configuration Register (0x80123)
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default state, source side interface UTOPIA Level Master mode with parity generation. Source Side Operating Mode Depending value UTOP_MODE[1:0] field, UTOPIA interface will either UTOPIA master (controls write enable signal) UTOPIA device (controls cell available signal). device SRC_INTF either UTOPIA Level device, where only device UTOPIA bus, UTOPIA Level device where other devices coexist UTOPIA bus. master device SRC_INTF only function UTOPIA Level device. ANY-PHY_EN then SRC_INTF operates single port Any-PHY slave device. Any-PHY mode in-band addressing used allow more than possible addresses available UTOPIA mode. extra word prepended front each cell that transmitted. prepended word indicates port address sending cell. SRC_INTF uses CFG_ADDR[15:0] UI_SRC_ADD_CFG register (0x80123) address prepend. operating mode source side interface configured using UTOP_MODE[1:0], ANY-PHY_EN, 16_BIT_MODE bits, summarized table below. denotes that field selectable that mode. "n/a" denotes that field ignored that mode. Mode UTOPIA Level Master UTOPIA Level Slave UTOPIA Level Single Address Slave Any-PHY Slave Notes: source side interface, UTOP_MODE[1:0] "11" Reserved should used. 16_BIT_MODE set, then bits UTOPIA data Any-PHY interface used. UTOP_MODE[1:0] ANY-PHY_EN 16_BIT_MODE
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16_BIT_MODE low, then only lower bits used.
Parity Generation EVEN_PAR determines calculated parity across data bytes/words sent source interface. EVEN_PAR parity Even parity. Function
Chip Select Enable Any-PHY Mode CS_MODE_EN used determine RPHY_ADDR(3)/RCSB input pin. This should only Any-PHY mode. CS_MODE_EN Function RPHY_ADDR(3)/RCSB input used address (RPHY_ADDR(3)) source side interface. RPHY_ADDR(3)/RCSB input used chip select (RCSB) source side interface.
Slave Source Address CFG_ADDR[15:0] bits Slave Source Address Configuration Register (0x80123) contain configured slave address used UTOPIA Level Any-PHY operation source direction. Depending mode UTOPIA/Any-PHY interface different bits this field used. following table details.
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Polling MODE UTOPIA-2 Single-Addr Any-PHY with Any-PHY without Notes: PHY_ADDR Pins [4:0]=device [2:0]=device CFG_ADDR [4:0]=device [2:0]=device
Selection PHY_ADDR Pins [4:0]=device [2:0]=device CFG_ADDR prepended CFG_ADDR [4:0]=device [15:0]=device
[3:0]=device
[3:0]=device
[3:0]=device CFG_ADDR prepended
[15:0]=device
Any-PHY mode direction, AAL1gator will prepend cell with CFG_ADDR[15:0]. 8-bit mode, cell will prepended with CFG_ADDR[7:0]. Any-PHY mode, CS_MODE_EN '0', then CFG_ADDR[4:3] "00". Any-PHY mode, CS_MODE_EN '1', then CFG_ADDR[3]="0".
UTOPIA Sink Interface Configuration UTOPIA Sink Interface (SNK_INTF) block receives cells from UTOPIA interface sends them UMUX interface. Configuration UTOPIA sink side interface controlled Sink Configuration Register (0x80122). Please note that every time UTOPIA Interface needs reprogrammed, recommended Chip Software Reset state described section 5.2.2. default configuration follows: ANY-PHY_EN EVEN_PAR Register Value
UTOP_MODE[1:0] Sink Configuration Register (0x80122) Sink Configuration Register (0x80122) Sink Configuration Register (0x80122)
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16_BIT_MODE CS_MODE_EN
Register Sink Configuration Register (0x80122) Sink Configuration Register (0x80122)
Value 0x0000
CFG_ADDR[15:0] Slave Sink Address Configuration Register (0x80124)
default state, sink side interface UTOPIA Level Master mode with parity generation. Sink Side Operating Mode Depending value UTOP_MODE[1:0] field, UTOPIA interface acts either UTOPIA master (controls read enable signal) UTOPIA device (controls cell available signal). device SNK_INTF either UTOPIA Level device, where only device UTOPIA bus, UTOPIA Level device where other devices coexist UTOPIA bus. master device SNK_INTF only function UTOPIA Level device. ANY-PHY_EN then SNK_INTF operates multi port Any-PHY slave device. Any-PHY mode in-band addressing used allow more than possible addresses available UTOPIA mode. extra word prepended front each cell that transmitted. prepended word indicates port address receive cell. SNK_INTF uses CFG_ADDR[15:2] UI_SNK_ADD_CFG register (0x80124) match with address prepend. 16_BIT_MODE then CFG_ADDR(7:2) used. operating mode sink side interface configured using UTOP_MODE[1:0], ANY-PHY_EN, 16_BIT_MODE bits, summarized table below. denotes that field selectable that mode. "n/a" denotes that field ignored that mode. Mode UTOPIA Level Master UTOPIA Level Slave UTOPIA Level Single Address Slave UTOPIA Level Multi-Address Slave UTOP_MODE[1:0] ANY-PHY_EN 16_BIT_MODE
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Mode Any-PHY Slave Notes:
UTOP_MODE[1:0] ANY-PHY_EN
16_BIT_MODE
UTOPIA Level Multi-Address Slave mode only valid AAL1gator-32; AAL1gator-8 AAL1gator-4, UTOP_MODE[1:0] "11" Reserved should used. 16_BIT_MODE set, then bits UTOPIA data Any-PHY interface used. 16_BIT_MODE low, then only lower bits used.
Parity Generation EVEN_PAR determines calculated parity across data bytes/words sent source interface. EVEN_PAR parity Even parity. Function
Chip Select Enable Any-PHY Mode CS_MODE_EN used determine TPHY_ADDR(3)/TCSB input pin. This should only Any-PHY mode. CS_MODE_EN Function TPHY_ADDR(3)/TCSB input used address (TPHY_ADDR(3)) sink side interface. TPHY_ADDR(3)/TCSB input used chip select (TCSB) sink side interface.
Slave Sink Address CFG_ADDR[15:0] bits Slave Sink Address Configuration Register (0x80124) contain configured slave address used UTOPIA Level Any-PHY operation sink direction. Depending mode
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UTOPIA/Any-PHY interface different bits this field used. following table details. Polling MODE UTOPIA-2 Single-Addr UTOPIA-2 Multi-Addr Any-PHY with PHY_ADDR Pins [4:0]=device [4:2]=device [1:0]=A1SP [2]=device [1:0]=A1SP [2]=device CFG_ADDR [4:0]=device [4:2]=device Selection PHY_ADDR Pins [4:0]=device [4:2]=device [1:0]=A1SP [2]=device [1:0]=A1SP CFG_ADDR prepended Any-PHY without [3:2]=device [1:0]=A1SP [3:2]=device [3:2]=device [1:0]=A1SP CFG_ADDR prepended [15:2]=device [15:2]=device CFG_ADDR [4:0]=device [4:2]=device
Notes: Any-PHY mode, upper bits prepended address compared with CFG_ADDR[15:2]. bottom bits compared with this field just used select target A1SP. 8-bit mode CFG_ADDR[7:2] used instead. Any-PHY mode, CS_MODE_EN='0', then CFG_ADDR[4:3] "00". Any-PHY mode, CS_MODE_EN='1', then CFG_ADDR[3]="0".
Based UTOPIA UTOPIA Loopback U2U_LOOP_VCI[15:0] bits U2U_LOOP_VCI (0x80125) register specify used based loopback. VCI_U2U_LOOP UI_COMN_CFG_REG (0x80120), then cell received from bus, with which matches this programmed VCI, will sent back bus. value this register should changed only when VCI_U2U_LOOP disabled. U2U_LOOP_VCI[15:0] defaults 0x0000.
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6.4.1 Loopback Setup Example Multi-Address mode Internal routing circuitry UTOPIA Level multi-address mode requires some special consideration values select addresses. example proper configuration based loopback while UTOPIA Level multi-address mode shown Figure Note that cells sent sink interface address TxAddr=bbb10 (where configured base address) which have VCI[15]=y VCI[12:0]=z will looped back because resulting internal will match that U2U_LOOP_VCI (0x80125) register. maintain correct functionality, cell's VCI[14:13] should match that lower bits select address TxAddr, i.e. VCI[14:13]=10, thus will appear unchanged when exiting source side. Shift_VCI= then requirements VCI[14:13] placed VCI[10:9] instead. loopback cells will appear source side interface, regardless setting source configuration address (UI_SRC_CFG_ADR), maintain symmetry source configuration address should RxAddr=bbb10 this example that looped back cells appear same source address slave) port sink address slave). alternate setting would incoming VCI[14:13] TxAddr(1:0) RxAddr(1:0) "00", thus using sink side base address loopback address.
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Figure UTOPIA Level Multi-Address Mode with Based Loopback
Cell Data VCI(15) VCI(14:13) VCI(12:0) RxAddr =BBB10 Cell Data VCI(15) VCI(14:13) VCI(12:0)
TxAddr =BBB10
select address (1:0) ends source side
TDAT_O
TADR_I
RDAT_I
RADR_I
UI_SRC_CFG_ADDR(4:2)=BBB UI_SRC_CFG_ADDR(1:0)=10 UI_SRC_INTF
UI_SNK_CFG_ADDR(4:2)=BBB UI_SNK_CFG_ADDR(1:0)= ignored UI_SNK_INTF
Shift_VCI U2U_LOOP_VCI(15)= U2U_LOOP_VCI(14:13)= U2U_LOOP_VCI(12:0)=
AAL1_UI
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DATA STRUCTURES Please note that only memory locations A1SP used AAL1gator-8, that only memory locations lines through A1SP used AAL1gator-4.
Transmit Data Structures Figure shows format Transmit Data Structures block. Figure Transmit Data Structures Memory
00020 0002F 00030 0003F 00040 003FF 00400 0047F 00480 004FF 00500 006FF 00700 007FF 00800 00FFF 01000 013FF 01400 0143F 01440 01FFF 02000 03FFF 04000 07FFF T_SEQNUM_TBL T_ADD_QUEUE Unused T_COND_SIG T_COND_DATA Unused Reserved (Frame Advance FIFO) Reserved (Transmit Calendar) Reserved (Transmit Signaling Buffer) T_OAM_QUEUE Unused T_QUEUE_TBL Reserved (Transmit Data Buffer)
Note addresses listed below offsets within each A1SP address space described section Note Addr column Table means A1SP digit: (000x=A1SP0, 011x=A1SP3)
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Table Transmit Structures Summary Name Size Addr Description
P_FILL_CHAR
word
bytes
0004H
Reserved(AQ) T_SEQNUM_TBL
words words bytes lines
bytes bytes bytes
0030H 003FH 0020H 002FH 0400H 047FH 0480H04FFH
empty bytes partially filled cell filled with P_FILL_CHAR. (Reserved (AQ)) Transmit Sequence Number Table initialized according table. This table stores signaling used when TX_COND T_QUEUE_TBL set. This table stores data used when TX_COND T_QUEUE_TBL set. Reserved (Frame Advance FIFO). Reserved (Transmit Calendar). Reserved (Transmit Signaling Buffer). Transmit Queue contains cells transmitted.
T_COND_SIG
T_COND_DATA
bytes lines
bytes
Reserved Reserved Reserved T_OAM_QUEUE
words words bytes words
bytes kBytes kBytes bytes
0700H07FFH 0800H0FFFH 1000H13FFH 1400H143FH
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Name
Size
Addr
Description
T_QUEUE_TBL
words
kBytes
2000H3FFFH
Reserved Notes:
8x2K words
kBytes
4000H7FFFH
Transmit Queue Table contains pointers variables that queue-dependent. Reserved (Transmit Data Buffer).
ports marked "Reserved" must initialized initial setup. Software modifications these locations after setup will cause incorrect operation. read/write port bits marked "Not used" must written with value maintain software compatibility with future versions. read-only port bits marked "Not used" driven with should masked software maintain compatibility with future versions. 7.1.1 P_FILL_CHAR Organization: word Base address within A1SP: Type: Read/Write Function: Contains fill character partially filled cells. Format: Refer following table.
Field (Bits) used (15:8) P_FILL_CHAR (7:0)
Description Write with maintain future software compatibility. Character used partially filled cells. Initialize desired value.
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7.1.2 T_SEQNUM_TBL Organization: words Base address within A1SP: Index: Type: Read/Write Function: Stores possible first bytes payload: CSI, SNP. This table must loaded into SRAM every power cycling. Initialization: Initialize values following table
Offset
Data Value 0000H 0017H 002DH 003AH 004EH 0059H 0063H 0074H 008BH 009CH 00A6H 00B1H 00C5H 00D2H 00E8H 00FFH
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7.1.3 T_COND_SIG Organization: bytes lines Base address within A1SP: 400H Index: Type: Read/Write Function: Stores transmit conditioned signaling. Initialization: Initialize conditioned signaling value channel. This value typically depends type channel unit that connected. example, Foreign Exchange Office (FXO) needs different conditioning value than Foreign Exchange Subscriber (FXS). Format: nibble byte, bytes word, words line. Refer following table.
Offset 00000H 00010H 00020H 00030H 00040H 00050H 00060H 00070H
Name T_COND_SIG_0 T_COND_SIG_1 T_COND_SIG_2 T_COND_SIG_3 T_COND_SIG_4 T_COND_SIG_5 T_COND_SIG_6 T_COND_SIG_7
Description Transmit conditioned signaling line Transmit conditioned signaling line Transmit conditioned signaling line Transmit conditioned signaling line Transmit conditioned signaling line Transmit conditioned signaling line Transmit conditioned signaling line Transmit conditioned signaling line
T_COND_SIG_n Word Format Field (Bits) used (15:12) T_COND_SIG_A_H (11) Description Write with maintain future software compatibility. Transmit conditioned for: Offset ((channel line
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Field (Bits) T_COND_SIG_B_H (10) T_COND_SIG_C_H T_COND_SIG_D_H used (7:4) T_COND_SIG_A_L T_COND_SIG_B_L T_COND_SIG_C_L T_COND_SIG_D_L 7.1.4 T_COND_DATA
Description Transmit conditioned for: Offset ((channel line Transmit conditioned for: Offset ((channel line Transmit conditioned for: Offset ((channel line Write with maintain future software compatibility. Transmit conditioned for: Offset (channel line Transmit conditioned for: Offset (channel line Transmit conditioned for: Offset (channel line Transmit conditioned for: Offset (channel line
Organization: bytes lines Base address within A1SP: 480H Index: Type: Read/Write Function: Stores transmit conditioned data. Initialization: Initialize conditioned data appropriate channel, which typically depends type channel connected device. example, data usually needs value voice needs small Pulse Coded Modulation (PCM) value. Format: bytes word, words line. Refer following table.
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Offset 00000H 00010H 00020H 00030H 00040H 00050H 00060H 00070H
Name T_COND_DATA_0 T_COND_DATA_1 T_COND_DATA_2 T_COND_DATA_3 T_COND_DATA_4 T_COND_DATA_5 T_COND_DATA_6 T_COND_DATA_7
Description Transmit conditioned data line Transmit conditioned data line Transmit conditioned data line Transmit conditioned data line Transmit conditioned data line Transmit conditioned data line Transmit conditioned data line Transmit conditioned data line
T_COND_DATA_n Word Format Field (Bits) T_COND_DATA_H (15:8) T_COND_DATA_L (7:0) 7.1.5 RESERVED (Transmit Signaling Buffer) This structure reserved need initialized Software modifications this structure after setup will cause incorrect operation. Organization: Eight multiframes DS0s lines. Each eight lines allocated separate signaling buffer. Each generates nibble signaling multiframe. data stored buffer order received from framer device. Different framers provide signaling information different formats, following illustration shows, multiframe worth signaling data. Base address: 01000H Index: Type: Read/Write Function: Stores outgoing signaling data. Description Transmit conditioned data offset ((channel line Transmit conditioned data offset (channel line
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Figure SDF-MF Format T_SIGNALING BUFFER
Word
upper nibble each byte
7.1.6 T_OAM_QUEUE Organization: cells words Base address within A1SP: 01400H Index: Type: Read/Write Function: Stores transmit cells. Initialization: optimization initialize body cell only header must modified before sending. Format: Refer following table.
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Offset 01400H 01420H
Name T_OAM_CELL_1 T_OAM_CELL_2
Description Transmit cell Transmit cell
T_OAM_CELL_n Format Offset Word Word Word Bits 15:8 Header Header Header (HEC) (Pre-calculated software) Bits Header Header Bits Disables CRC-10 insertion. Enables CRC-10 insertion. Word Word Payload Payload Payload Payload used.
CRC-10 enabled Word data Word Word will replaced computed CRC-10 result cell transmitted. Note: Programming (word T_OAM_CELL_n) optional this already done device that interconnected AAL1gator. 7.1.7 T_QUEUE_TBL Organization: words Base address within A1SP: 2000H Index: Type: Read/Write
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Function: Configures VCs. Format: Each queue will allocated consecutive words. Offset Name Reserved Description (Data pointer.) Initialize FFFFH each time this queue initialized. used Initialize each time this queue initialized maintain future software compatibility. T_COND_CELL_CNT 16-bit rollover count conditioned cells transmitted. T_SUPPRESS_CNT 16-bit rollover count cells sent because line resynchronization. UDF-HS mode, 16-bit rollover count cells sent because TX_ACTIVE set. This counter also counts when cells sent because SUPPRESS_TRANSMISSION set. used Initialize each time this queue initialized maintain future software compatibility. Reserved (Sequence number.) Initialize each time this queue initialized. QUEUE_CONFIG configuration current queue. Initialize proper value. T_CELL_CNT 16-bit count cells transmitted. TX_HEAD(1:2) Header byte bits 15:8, header byte bits 7:0. TX_HEAD(3:4) Header byte bits 15:8, header byte bits 7:0. TX_HEAD(5) Header byte (pre-calculated HEC) bits 15:8. QUE_CREDITS 10-bit quantity representing number byte credits accumulated queue. CSD_CONFIG Stores average number bytes each cell, carries number DS0s this queue. used Initialize each time this queue initialized maintain future software compatibility. T_CHAN_ALLOC(15: table with allocated this queue DS0s 15:0 line defined queue
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Offset
Name
Description
T_CHAN_ALLOC(31: table with allocated this queue DS0s 31:16 line defined queue T_CHAN_LEFT(15:0 Initialize same value T_CHAN_ALLOC(15:0). T_CHAN_LEFT(31:1 Initialize same value T_CHAN_ALLOC(31:16). TRANSMIT_CONFIG Controls transmission data. Reserved (T_CUR_ACT_CHAN(15:0)) Initialize each time this queue initialized. Reserved (T_CUR_ACT_CHAN(31:16)) Initialize each time this queue initialized. Reserved (T_NEW_ACT_CHAN(15:0)) Initialize each time this queue initialized. Reserved (T_NEW_ACT_CHAN(15:0)) Initialize each time this queue initialized. Reserved (CSD_BYTES_LEFT) Only used DBCES mode. When operating DBCES mode this register must initialized structure size minus portion structure that fits first cell. formula calculate this value struct_size ((46-bitmask_size) struct_size) number data bytes first cell minus structure pointer bitmask size. operation determines number bytes from structure that make into first cell. This number then subtracted from structure size determine many bytes left structure after first cell. 18H-1FH used Initialize each time this queue initialized. T_COND_CELL_CNT Word Format Initialize "0000" other times word read only. word maintained TALP.
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Field (Bits) T_COND_CELL_CNT (15:0)
Description 16-bit rollover count conditioned cells transmitted. This counter increments when cells with conditioned data sent. only signaling conditioned this counter will increment.
T_SUPPRESS_CNT Word Format Initialize "0000" other times word read only. word maintained TALP.
Field (Bits) T_SUPPRESS_CNT (15:0)
Description 16-bit rollover count cells sent because line resynchronization. UDF-HS mode, 16-bit rollover count cells sent because TX_ACTIVE set. This counter also counts when cells sent because SUPPRESS_TRANSMISSION set.
QUEUE_CONFIG Word Format This word maintained microprocessor.
Field (Bits) TX_COND (15)
Description Sends data signaling from transmit conditioned data area according conditioning mode selected TRANSMIT_CONFIG register. Initialize proper value.
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Field (Bits) TX_ACTIVE (14)
Description Enables this queue. enable connections: 1)Assert this bit.
2)Add this queue ADDQ_FIFO Register. disable connections, clear TX_ACTIVE bit. This queue then removed from calendar queue next time cell would have been sent. Once this cleared, associated queue must returned add-queue FIFO until FRAMES_PER_CELL frames have passed quick reconfiguration required size queue going change (number allocated channels), then SUPPRESS_XMT pause queue reconfigure instead clearing TX_ACTIVE bit. When reactivating previously active queue, sure reinitialize registers queue table that queue.
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Field (Bits) FRAMES_PER_CELL (13:8)
Description 6-bit integer specifying maximum number frames required have enough data construct cell (round BYTE_PER_CELL/number DS0s assigned) plus example, line SDF-FR mode with five DS0s, initialize this field SDF-MF SDF-FR modes, FRAMES_PER_CELL encoded number 24-frame multiframes required number frames bits 12:8. other modes, including unstructured mode, encode this value maximum number increments required create cell. unstructured mode with full cells, this value channels with single DS0, encode value multiframe frames. When calculating FRAMES_PER_CELL value, subtract bytes used signaling nibbles from value. example, SDF-MF, single DS0, full cell connection, value SDF-MF connections using partial cells, FRAMES_PER_CELL (round BYTE_PER_CELL/number DS0s assigned) plus This prevents scheduling more than cell frame.
T_CHAN_NO_SIG
send cells with signaling when SDF-MF mode. This same using this queue SDF-FR mode, which means structure forms frame boundaries instead multiframe boundaries. only when sending cells with single without pointer SDF-FR mode. conform standard when using single SDF-FR mode, pointer should used.
T_CHAN_UNSTRUCT
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Field (Bits) BYTES_PER_CELL (5:0)
Description 6-bit integer specifying many bytes cell required structure pointers used. UDF_HS mode, this value must This number must cell generation rate queue slower than once frame. unstructured lines, this means between structured applications, BYTES_PER_CELL number must exceed number channels allocated queue. example, channel queue have number from SDF-MF connections with more than channels allocated, BYTES_PER_CELL number must exceed number channels allocated queue two. example, channel SDF-MF queue have number from AAL0 connections this field should This fact that there sequence number byte AAL0 cells.
T_CELL_CNT Word Format Initialize "0000" other times word read only. word maintained TALP.
Field (Bits) T_CELL_CNT (15:0)
Description 16-bit count data cells transmitted. Rolls from FFFFH. Initialize After initialization, write this word.
TX_HEAD(1:2) Word Format This word maintained microprocessor.
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Field (Bits) TX_HEAD(1) (15:8) TX_HEAD(2) (7:0)
Description First header byte bits 15:8. Initialize proper value. Second header byte bits 7:0. Initialize proper value.
TX_HEAD(3:4) Word Format This word maintained microprocessor.
Field (Bits) TX_HEAD(3) (15:8) TX_HEAD(4) (7:0) TX_HEAD(5) Word Format This word maintained microprocessor.
Description Third header byte bits 15:8. Initialize proper value. Fourth header byte bits 7:0. Initialize proper value.
Field (Bits) TX_HEAD(5) (15:8) used (7:0)
Description Fifth header byte that contains precalculated word. Initialize proper value. Write with maintain compatibility with future software versions.
Note: Programming optional this already done device that interconnected AAL1gator. QUE_CREDITS Word Format After initialization this word read only. word maintained CSD.
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Field (Bits) FRAME_REMAINDER (15:14)
Description 2-bit quantity representing remainder division operation performs when converting frame differential (expressed frames) frame differential (expressed eighths multiframes). This quantity maintained CSD. Initialize 00b. Write with maintain compatibility with future software versions. 10-bit quantity representing number byte credits accumulated queue. measured eighths (three LSBs fractional bits). Initialize (178H) modes full cells, 46.875 (177H) mode full cells, partially filled cell length SDF-MF queues start with (177H) times number signaling bytes which would occur first cell. (For (E1) this (187H), DS0(T1) DS0s (E1) this (17FH). other configurations initial value should (177H).
used (13:10) QUEUE_CREDITS (9:0)
CSD_CONFIG Word Format This word maintained microprocessor.
Field (Bits) NUM_CHAN (15:10)
Description 6-bit integer specifying number channels being carried this queue. queue serves seven DS0s, initialize this field This field UDF-ML mode. used UDF-HS mode.
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Field (Bits) AVG_SUB_VALU (9:0)
Description 10-bit integer representing average number data bytes cell measured eighths. three LSBs represent bits after fixed decimal point. Initialize 46.875 (0101110.111) full cells when SDF-FR SDF-MF mode. Initialize (0101111.000) full cells when UDF-ML mode. partial cells, this value same partially filled value This field used UDF-HS mode.
T_CHANNEL_ALLOC(15:0) Word Format This word maintained microprocessor.
Field (Bits) T_CHANNEL_ALLOC (15:0)
Description table with allocated this queue DS0s line defined queue Initialize proper value SDF-MF SDF-FR modes FFFFH UDF-ML UDF-HS modes.
T_CHANNEL_ALLOC(31:16) Word Format This word maintained microprocessor.
Field (Bits) T_CHANNEL_ALLOC (31:16)
Description table with allocated this queue DS0s line defined queue Initialize proper value SDF-MF SDF-FR modes FFFFH UDF-ML UDF-HS modes.
T_CHANNEL_LEFT(15:0) Word Format After initialization this word read only. word maintained TALP.
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Field (Bits) T_CHANNEL_LEFT (15:0)
Description Initialize same value T_CHAN_ALLOC(15:0).
T_CHANNEL_LEFT(31:16) Word Format After initialization this word read only. word maintained TALP.
Field (Bits) T_CHANNEL_LEFT (31:16)
Description Initialize same value T_CHAN_ALLOC(31:16).
TRANSMIT_CONFIG Word Format This word maintained microprocessor.
Field (Bits) SUPPRESS_XMT (15) LOOPBACK_ENABLE (14) AAL0_MODE_ENABLE (13)
Description suppress generation cells this queue. Cells scheduled transmitted. loopback cell receive side. VPI/VCI corresponding receive queue number. build AAL0 cells instead AAL1.
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Field (Bits) COND_MODE (12:11)
Description Selects conditioning mode with following encoding: Both signaling data conditioned Only signaling conditioned Only data conditioned reserved chosen mode takes effect when TX_COND QUEUE_CONFIG memory register. data conditioned T_COND_CELL_CNT counter will increment. only signaling conditioned T_CELL_CNT will increment normal.
DBCES_ENABLE (10) IDLE_DET_ENABLE
enable DBCES functionality. enable idle detection non-DBCES mode. When this mode queue which idle channels will have transmission cells suppressed. suppressed cell will cause T_SUPPRESS_CNT incremented. Write with maintain future software compatibility.
used (8:0)
7.1.8 RESERVED (Transmit Data Buffer) This structure reserved must initialized initial setup. Software modifications this location after setup will cause incorrect operation. Organization: kBytes lines Each line allocated separate frame buffer memory. applications, this large enough store eight multiframes DS0s frames multiframes 4096 bytes). mode, frames four multiframes stored 2880bytes). storage uses bytes frame frames multiframe simplify address generation. Every data byte stored multiframe line buffers order which arrives. E1_with_T1_SIG set, data arranged mode. Base address within A1SP: 4000H
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Index(line): 800H Type: Read/Write Function: Stores outgoing data. Format: data bytes word, words frame. T_DATA_BUFFER Word Format Field (Bits) T_DATA_H (15:8) Transmit data for: Channel (offset offset line 2048 multiframe frame (channel offset line 2048 multiframe frame (channel T_DATA_L (7:0) Transmit data for: Channel (offset offset line 2048 multiframe frame channel offset line 2048 multiframe frame channel Receive Data Structures Figure shows format Receive Data Structures block more detail. Description
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Figure Receive Data Structures
08000 08001 08002 08003 08004 0801F 08020 0802F 08030 08037 08038 0803F 08040 0807F 08080 080FF 08100 081FF 08200 0827F 08280 083FF 08400 0847F 08480 084FF 08500 087FF 08800 08FFF 09000 09FFF 0A000 0BFFF 0C000 0DFFF 0E000 0FFFF 10000 1FFFF R_OAM_QUEUE_TBL R_OAM_CELL_CNT R_DROPPED_OAM_CELL_CNT Unused Reserved (SRTS Queue Pointers) Unused R_SRTS_CONFIG Unused R_CRC_SYNDROME Unused R_CH_TO_QUEUE_TBL Unused R_COND_SIG R_COND_DATA Unused Reserved (Receive SRTS Queue) Reserved (Receive Signaling Buffer) R_QUEUE_TBL Unused R_OAM_QUEUE Reserved (Receive Data Buffer)
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Note addresses listed below offsets within each A1SP address space described section Name R_OAM_QUEUE_TBL R_OAM_CELL_CNT R_DROP_OAM_CELL Reserved R_SRTS_CONFIG R_CRC_SYNDROME R_CH_TO_QUE_TBL R_COND_SIG R_COND_DATA Reserved Reserved R_QUEUE_TBL R_OAM_QUEUE Reserved words word word words bytes lines words words bytes bytes words words words bytes bytes Size bytes bytes bytes bytes bytes Addr 8000H- 8001H 8002H 8003H 8020H802FH 8038H803FH Description Receive head tail pointers. Count received cells. Count dropped cells. Reserved (SRTS Queue Pointers). Receive SRTS configuration. Mask bits. Initialized from table. Receive channel queue table. Receive signaling conditioning values. Receive data conditioning values. Reserved (Receive SRTS Queue). Reserved (Receive Signaling Buffer). Receive queue table. Receive queue.
bytes 8080H80FFH bytes 8200H827FH bytes 8400H847FH bytes 8480H84FFH kBytes 8800H8FFFH kBytes 9000H9FFFH kBytes kBytes kBytes A000HBFFFH E000HFFFFH
10000H- Reserved (Receive 1FFFFH Data Buffer).
This section describes structures used receive side AAL1gator.
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Notes: ports marked "Reserved" must initialized initial setup. Software modifications these locations after setup will cause incorrect operation. read/write port bits marked "Not used" must written with value maintain software compatibility with future versions. read-only port bits marked "Not used" driven with should masked software maintain compatibility with future versions.
7.2.1 R_OAM_QUEUE_TBL Organization: words Base address within A1SP: 8000H Index: Type: Read/Write Function: cells received from Aside stored FIFO queue memory. Head tail pointers used keep track read write locations cell buffers. There cell buffers receive queue. these cell buffers, usable. 256th buffer used detect full queue follows: When queue empty, OAM_HEAD OAM_TAIL When cell received, cell written into buffer index (OAM_TAIL 256, OAM_TAIL replaced with (OAM_TAIL 256. When processor receives interrupt, reads cell buffer index (OAM_HEAD 256. After completing read, sets OAM_HEAD (OAM_HEAD 256. This process continued until OAM_HEAD OAM_TAIL, which time receive queue empty. receive interrupt cleared asserting CLR_RX_OAM_LATCH CMD_REG. cell arrived between time OAM_TAIL last read CLR_RX_OAM_LATCH asserted, this cell's arrival detected within interrupt service routine re-reading OAM_TAIL after CLR_RX_OAM_LATCH asserted.
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Queue Format Offset Name OAM_HEAD OAM_TAIL Head pointer Tail pointer Description
OAM_HEAD Word Format Field(Bits) OAM_HEAD (7:0) OAM_TAIL Word Format Field(Bits) OAM_TAIL (7:0) 7.2.2 R_OAM_CELL_CNT Organization: word Base address within A1SP: 8002H Index: Type: Read/Write Function: 16-bit rollover counter that counts number cells received. software must initialize this counter during reset. R_OAM_CELL_CNT Word Format Field(Bits) R_OAM_CELL_CNT (15:0) Description 16-bit rollover counter that counts number cells received. software must initialize this counter during reset. After initialization, write this word. Description Incremented RALP after writes cell cell queue. Initialize Description microprocessor should increment next cell location when reads cell. Initialize
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7.2.3 R_DROP_OAM_CELL Organization: word Base address within A1SP: 8003H Index: Type: Read/Write Function: 16-bit rollover counter that counts number dropped cells. software should initialize this counter during reset. R_DROP_OAM_CELL Word Format Field(Bits) R_DROP_OAM_CELL (15:0) Description 16-bit rollover counter that counts number cells dropped. cells dropped when more than present receive queue. software must initialize this counter during reset. After initialization, write this word.
7.2.4 R_SRTS_CONFIG Organization: bytes lines Base address within A1SP: 8038H Index: Type: Read/Write Function: This table stores CDVT SRTS channel, expressed number queued SRTS nibbles. Initialization: Initialize number SRTS nibbles equivalent CDVT data rounding Each frame CDVT unstructured applications represent bits. Each SRTS nibble represents 3008 bits, which number data bits eight cells. Therefore, number SRTS nibbles that corresponds CDVT determined dividing CDVT number frames 3008 256, 11.75, rounding next higher integer. Format: byte line. Refer following table.
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R_SRTS_CONFIG Format Offset Name R_SRTS_CDVT_0 R_SRTS_CDVT_1 R_SRTS_CDVT_2 R_SRTS_CDVT_3 R_SRTS_CDVT_4 R_SRTS_CDVT_5 R_SRTS_CDVT_6 R_SRTS_CDVT_7 Description Receive SRTS CDVT line Receive SRTS CDVT line Receive SRTS CDVT line Receive SRTS CDVT line Receive SRTS CDVT line Receive SRTS CDVT line Receive SRTS CDVT line Receive SRTS CDVT line
R_SRTS_CDVT_n Word Format Field(Bits) used (15:5) R_SRTS_CDVT (4:0) 7.2.5 R_CRC_SYNDROME Organization: words Base address within A1SP: 8080H Index: Type: Read/Write Function: This table identifies which SN/SNP byte been corrupted, any. Load after each power cycle. Used internally perform correction. Description Write with maintain compatibility with future software versions. Receive SRTS CDVT
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R_CRC_SYNDROME Word Format Field(Bits) used (15:5) RX_CRC_SYNDROME (4:0) Figure R_CRC_SYNDROME Mask Table Legend
LEGEND errors Correct Correct Correct Correct error need correct field)
Description Write with maintain compatibility with future software versions. Mask bits change.
Table R_CRC_SYNDROME Mask Table Sequence Number Offset Data (Hex) Sequence Number Offset Data (Hex)
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Sequence Number
Offset
Data (Hex)
Sequence Number
Offset
Data (Hex)
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Sequence Number
Offset
Data (Hex)
Sequence Number
Offset
Data (Hex)
7.2.6 R_CH_TO_QUEUE_TBL Organization: words lines DS0s) Base address within A1SP: 8200H Index:
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Type: Read/Write Hardware Reset Value: 8080H Function: This table associates with queue. allows transmit line interface determine status receive queue supplying bytes DS0s being processed. This table located inside chip time slots initialized play conditioned data. AAL1gator processes bytes time values following table pairs. unstructured, speed lines, queue values receive queue number UDFHS mode, this table used. When this queue underrun, AAL1gator reads data line from first word R_COND_DATA_0 table. Format: Refer following table. R_CH_TO_QUEUE_TBL Format Offset Name R_CH_TO_QUEUE Description Queue numbers condition bits associated with this pair channels where: Line channel High channel
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R_CH_TO_QUEUE Word Format Field(Bits) RX_COND_H (15:14) Description Determines type data played out: Options "00", "01", "11" executed only when queue underrun resume state. When queue underrun, freeze signaling read data this channel from R_COND_DATA table. When queue underrun, freeze signaling play pseudorandom data, which inserted data from R_COND_DATA, with controlled pseudorandom number algorithm (not valid UDF-HS). Read signaling this channel from R_COND_SIG table data this channel from R_COND_DATA table. When queue underrun freeze signaling play contents buffer. RX_SIG_COND_H (13) Overrides normal signaling with Conditioned signaling Read signaling indicated RX_COND_H
Always read signaling this channel from R_COND_SIG table QUEUE_H (12:8) Five LSBs queue index associated with this DS0. three MSBs implicitly those line number. Offset (channel line unstructured lines, receive queue number
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Field(Bits) RX_COND_L (7:6)
Description Determines type data played out: Options "00", "01", "11" executed only when queue underrun resume state. When queue underrun, freeze signaling read data this channel from R_COND_DATA table. When queue underrun, freeze signaling play pseudorandom data, which inserted data from R_COND_DATA, with controlled pseudorandom number algorithm (not valid UDF-HS). Read signaling this channel from R_COND_SIG table data this channel from R_COND_DATA table. When queue underrun, freeze signaling play contents buffer.
RX_SIG_COND_L
Overrides normal signaling with Conditioned signaling Read signaling indicated RX_COND_L Always read signaling this channel from R_COND_SIG table
QUEUE_L (4:0)
Five LSBs queue index associated with this DS0. three MSBs implicitly those line number. Offset channel line
7.2.7 R_COND_SIG Organization: words Base address within A1SP: 8400H Index: Type: Read/Write Function: This table stores signaling used when RX_SIG_COND_H RX_SIG_COND_L equals R_CH_TO_QUEUE_TBL.
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Initialization: Initialize conditioned signaling value channel. This value typically depends type channel unit that connected. example, channel unit needs different conditioning value than channel unit. Format: nibble byte, bytes word, words line. Refer following table. R_COND_SIG Format Offset 00000H 00010H 00020H 00030H 00040H 00050H 00060H 00070H Name R_COND_SIG_0 R_COND_SIG_1 R_COND_SIG_2 R_COND_SIG_3 R_COND_SIG_4 R_COND_SIG_5 R_COND_SIG_6 R_COND_SIG_7 Description Receive conditioned signaling line Receive conditioned signaling line Receive conditioned signaling line Receive conditioned signaling line Receive conditioned signaling line Receive conditioned signaling line Receive conditioned signaling line Receive conditioned signaling line
R_COND_SIG_n Word Format Field (Bits) used (15:12) R_COND_A_H (11) R_COND_B_H (10) R_COND_C_H R_COND_D_H Description Write with maintain future software compatibility. Receive conditioned signaling for: Offset (channel line Receive conditioned signaling for: Offset (channel line Receive conditioned signaling for: Offset (channel line Receive conditioned signaling for: Offset (channel line
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Field (Bits) used (7:4) R_COND_A_L R_COND_B_L R_COND_C_L R_COND_D_L 7.2.8 R_COND_DATA Organization: words Base address within A1SP: 8480H Index: Type: Read/Write
Description Write with maintain future software compatibility. Receive conditioned signaling for: Offset (channel line Receive conditioned signaling for: Offset (channel line Receive conditioned signaling for: Offset (channel line Receive conditioned signaling for: Offset (channel line
Function: This table stores data used when RX_COND R_CH_TO_QUEUE_TBL equals 00b, 01b, 10b. Initialization: Initialize conditioned data appropriate channel. This typically depends type channel connected device. example, data usually needs value voice needs small value. Format: bytes word, words line. Refer following table. R_COND_DATA Format Offset 00000H 00010H Name R_COND_DATA_0 R_COND_DATA_1 Description Receive conditioned data line Receive conditioned data line
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Offset 00020H 00030H 00040H 00050H 00060H 00070H
Name R_COND_DATA_2 R_COND_DATA_3 R_COND_DATA_4 R_COND_DATA_5 R_COND_DATA_6 R_COND_DATA_7
Description Receive conditioned data line Receive conditioned data line Receive conditioned data line Receive conditioned data line Receive conditioned data line Receive conditioned data line
R_COND_DATA_n Word Format Field (Bits) R_COND_DATA_H (15:8) R_COND_DATA_L (7:0) Description Receive conditioned data for: Offset (channel line Receive conditioned data for: Offset channel line
7.2.9 RESERVED (Receive SRTS Queue) This structure reserved. Software modifications this structure after setup will cause incorrect operation. Organization: words lines. Each line allocated separate 64-entry queue store SRTS receive nibbles. Base address within A1SP: 8800H Index: 100H Type: Read/Write Function: receive signaling queue stores SRTS bits received from UTOPIA interface. Initialization: necessary initialize this structure. Format: SRTS nibble word.
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R_SRTS_QUEUE_n Word Format Field (Bits) used (15:8) R_SRTS_VAL (7:4) Description Write with maintain future software compatibility. Indicates each SRTS contains valid data. When error occurs which causes lost corresponding will written with `0'. Each time entry written, remaining bits which haven't been received will also written with `0'. normally this field will written with "1000" first then "1100" second bit, then "1110" third finally "1111" last bit. Receive SRTS data line offset
R_SRTS (3:0)
7.2.10 RESERVED (Receive Signaling Buffer) This structure reserved. Software modifications this structure after setup will cause incorrect operation. Organization: DS0s lines. Each line allocated separate byte memory. this allows storage signaling information multiframes, unless E1_WITH_T1_SIG set. applications only first bytes every store signaling data. addition, since transmit data buffer only multiframes size, this structure also needs store only multiframes. Successive multiframes stored every other 32-byte buffer. When signaling frozen underrun, value multiframe used. Base address within A1SP: 9000H Index (line): 200H Type: Read/Write Function: receive signaling queue stores signaling that received from UTOPIA interface. Initialization: signaling buffer should initialized "0". Also, R_CHAN_NO_SIG some queues specific signaling value desired driven these queues, then DS0s those queues must initialized desired value multiframes.
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Format: signaling nibbles word. R_SIG_BUFFER_n Word Format Field (Bits) used (15:13) R_SIG_INVALID (12) R_SIG_H (11:8) Description Write with maintain future software compatibility. Indicates that stored signaling invalid. signaling valid lost cells, signaling will freeze. Receive signaling data for: Channel (offset Multiframe (offset 512) Line offset 512. Offset line multiframe (channel used (7:5) R_SIG_INVALID R_SIG_L (3:0) Write with maintain future software compatibility. Indicates that stored signaling invalid. signaling valid lost cells, signaling will freeze. Receive signaling data for: Channel (offset Multiframe (offset 512) Line offset 512. Offset line multiframe channel 7.2.11 R_QUEUE_TBL Organization: words Base address within A1SP: A000H Index: Type: Read/Write
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Function: Receive Queue Table contains structures pointers specific queue. RALP RFTC blocks both R_QUEUE_TBL. Some words read both blocks written only blocks. Format: Each queue allocated consecutive words. Each word 16-bits wide. organization words follows. Table R_QUEUE_TBL Format Offset Name R_STATE_0 R_MP_CONFIG R_STATE_1 R_LINE_STATE R_MAX_BUF R_SEQUENCE_ERR R_INCORRECT_SNP R_CELL_CNT R_ERROR_STKY R_TOT_SIZE R_DATA_LAST R_TOT_LEFT used R_SN_CONFIG R_CHAN_ALLOC (15:0) R_CHAN_ALLOC (31:16) Reserved (CHNLEFTL) Reserved (CHNLEFTH) R_DROPPED_CELLS R_UNDERRUNS Description Cell receiver state Bytes cell CDVT constant. Cell receiver state Line state. Receive maximum buffer size. 16-bit rollover count errors. 16-bit rollover count cells with incorrect SNP. 16-bit rollover count played cells. Receive sticky bits. Total bytes structure. Number signaling bytes structure. Number bytes remaining structure. Initialize each time this queue initialized. Initialize each time this queue initialized. Configures sequence number processing algorithm. table with allocated this queue DS0s line defined queue table with allocated this queue DS0s line defined queue Initialize each time this queue initialized. Initialize each time this queue initialized. 16-bit rollover count cells that were received dropped. Initialize 16-bit rollover count occurrences underrun this queue. Initialize
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Offset
Name R_LOST_CELLS
Description
16-bit rollover count number lost cells this queue. Initialize R_OVERRUNS 16-bit rollover count occurrences overrun this queue. Initialize R_PTR_REFRAMES 16-bit rollover count occurrences pointer reframes. Initialize R_PTR_PAR_ERR 16-bit rollover count occurrences pointer parity errors. Initialize R_MISINSERTED 16-bit rollover count occurrences misinserted cells. Initialize R_ROBUST_SN Write pointer robust processing Reserved (CHNACTL) Initialize each time this queue initialized. Reserved (CHNACTH) Initialize each time this queue initialized. R_RD_PTR_LAST Read pointer integrity through underrun 1DHNot used Initialize each time this queue initialized. these locations must initialized whenever queue initialized.
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R_STATE_0 Word Format This word read-only maintained RALP
Field (Bits) R_DBCES_BM_IN_NXT (15) R_STRUCT_FOUND (14)
Description Indicates that Mask will present next structure. Used when found that locates structure next cell. Indicates that receiver structure found. Initialize
Reservd(OLDUNDRN_N) Initialize maintain future software compatibility. (13) Reservd(UNDRN_2AGO) Initialize maintain future software compatibility. (12) Reserved(ACTSN) (11:9) SN_STATE (8:6) 2ND_LAST_SN (5:3) LAST_SN (2:0) Initialize maintain future software compatibility. Specifies state state machine. Initialize Specifies that received cells ago. Initialize Specifies last that received. Initialize
R_MP_CONFIG Word Format This word maintained microprocessor.
Field (Bits) R_CHK_PARITY (15)
Description set, check parity incoming structure pointer.
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Field (Bits) R_BYTES_CELL (14:9)
Description 6-bit integer specifying many bytes cell required structure pointers used. UDF-HS mode, this must other modes, this partially filled length. cells partially filled, this set, treats this queue AAL0 queue will write bytes payload into allocated time slots. Receive Cell Delay Variation Tolerance (R_CDVT) constant programmed microprocessor during initialization. used RFTC after receipt first cell after underrun. SDF-MF, E1_WITH_T1_SIG, SDF-FR mode, R_CDVT expressed number multiframes bits number frames bits 4:0. other modes, R_CDVT number frames. unstructured applications, number frames refers number 256-bit increments. unstructured modes, this equivalent number 165.8 periods. Robust Processing, this field represents CDVT desired plus number frames stored cell that conditionally stored
R_AAL0_MODE R_CDVT (7:0)
R_STATE_1 Word Format This word read-only maintained RALP. This register located inside chip reset "0000".
Field (Bits)
Description
Reserved (FRC_UNDRN) Initialize maintain future software compatibility. (15) Reserved (SNCRCST) (14) Reserved (PTRMMST) (13) Initialize maintain future software compatibility. Initialize maintain future software compatibility.
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Field (Bits) Reserved (FNDPTR) (12) Reserved (FNDFRSTPTR) (11) Reserved (DBCES_EN) (10) used R_WRITE_PTR (8:0)
Description Initialize maintain future software compatibility. Initialize maintain future software compatibility. Initialize maintain future software compatibility. Driven with Mask reads maintain future software compatibility. Pointer frame which cell receiver writing last accepted cell.
R_LINE_STATE Word Format This word read-only after initialization maintained RALP RFTC. This register located inside chip reset 9000H.
Field (Bits) R_UNDERRUN (15) R_RESUME (14) R_SIG_RESUME (13) R_LONG_UNDERRUN (12) Reserved (11:9) R_END_UNDERRUN_P (8:0)
Description Indicates that this queue currently underrun. Initialize Indicates that this queue currently resume state. Initialize Indicates that this queue currently signal resume state. Initialize Indicates that rd_ptr wrapped while queue underrun Initialize maintain future software compatibility. Location read pointer needs reach after underrun begin playing data. Initialize maintain future software compatibility.
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R_MAX_BUF Word Format This word maintained microprocessor
Field (Bits) R_CHAN_UNSTRUCT (15)
Description only when receiving cells with single without pointer SDF-FR mode. This valid only SDF-FR mode. conform standard when using single SDF-FR mode, pointer should used. receive cells without signaling when line SDF-MF mode. This same using this queue SDF-FR mode, which means that structure forms frame boundaries instead multiframe boundaries. R_SIG_BUFFER will never updated this queue. However, TL_SIG output will drive value that initialized into this timeslot T_SIG_BUFFER. drop cells this queue. normal operation. Cells dropped because this recorded ALLOC_TBL_BLANK sticky bit. maintain integrity through underrun. normal operation. Size bytes-1 DBCES mask field. enable DBCES. This only valid SDF_FR mode.
R_CHAN_NO_SIG (14)
R_CHAN_DISABLE (13) BITI_UNDERRUN (12) DBCES_BIT_MASK (11:10) DBCES_EN
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Field (Bits) R_MAX_BUF (8:0)
Description Receiver maximum buffer size. R_MAX_BUF coded number frames. structured modes, this number frames. unstructured modes, this number 256-bit increments. amount data receive buffer exceeds R_MAX_BUF, more data will written, overflow will reported, queue will forced into underrun. maximum value R_MAX_BUF 1FEH most cases. structured mode with signaling, maximum value 17EH because frames used.
R_SEQUENCE ERROR Word Format This word read-only maintained RALP Field (Bits) R_SEQUENCE_ERR (15:0) Description 16-bit rollover count errors. This counter counts transitions from SYNC state OUT_OF_SEQUENCE state. This atmfCESAal1SeqErrors count from specification. Note that processing disabled, this counter will count out-of-sequence cells. Initialize Once initialized, write this word. R_INCORRECT_SNP Word Format This word read-only maintained RALP Field (Bits) R_INCORRECT_SNP (15:0) Description 16-bit rollover count cells with errors. This atmfCESHdrErrors counter from specification. Initialize Once initialized, write this word.
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R_CELL_CNT Word Format This word read-only maintained RALP Field (Bits) R_CELL_CNT (15:0) Description 16-bit rollover count received cells. This atmfCESReassCells counter from specification. Initialize Once initialized, write this word.
R_ERROR_STKY Word Format Receive sticky bits should used statistics gathering purposes only there means clearing them without possibility missing occurrence. Initialize
Field (Bits) TRANSFER (15)
Description This read then written with same value each time AAL1gator receives cell. This feature allows processor determine AAL1gator middle read then write cycle when processor cleared other sticky bits. accomplish this each time processor wants clear sticky bits, should complement this bit. Then, additional read this showed wrong value, then AAL1gator sticky word update interrupted. cell received. There parity error DBCES Mask.
CELL_RECEIVED (14) DBCES_BIT_MASK_ER (13)
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Field (Bits) PTR_RULE_ERROR (12)
Description There violation pointer generation rule. sequence begins with cell with SN=0 ends with cell with SN=7. This condition will pointer received, more than pointer received `out bounds' pointer received sequence. This condition will only checked modes where pointer expected sequence number error underrun occurred. cell dropped because blank allocation table because R_CHAN_DISABLE (refer "R_MAX_BUF Word Format" page144) asserted. cell dropped because valid pointer been found. cell dropped because forced underrun condition exists. forced underrun condition caused overruns pointer mismatches. cell dropped accordance with Algorithm specified ITU-T Recommendation I.363.1). Fast processing used this will always first cell NO_DROP_IN_STAT pointer received. cell received with pointer parity error. SRTS resume occurred. valid SRTS value received stored SRTS FIFO. cell received while SRTS queue underrun. resume occurred: valid cell received stored into buffer. This cell will played after CDVT. cell dropped because pointer mismatch. This event causes forced underrun condition.
ALLOC_TBL_BLANK (11) POINTER_SEARCH (10) FORCED_UNDERRUN SN_CELL_DROP
POINTER_RECEIVED PTR_PARITY_ERR SRTS_RESUME SRTS_UNDERRUN RESUME PTR_MISMATCH
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Field (Bits) OVERRUN UNDERRUN R_TOT_SIZE Word Format This word maintained microprocessor
Description cell dropped overrun. receive buffer exceeded maximum allowed depth. This event causes forced underrun condition. cell received while queue underrun.
Field (Bits) FRAMES_PER_CELL (15:10) R_TOT_SIZE (9:0)
Description Average number frames contained within single cell. This field used UDF-ML UDF-HS mode. Total bytes minus structure (for example, with DS0s, R_TOT_SIZE 32). This field used UDF-ML UDFHS mode. Three formulas R_TOT_SIZE are: T1/E1 SDF-FR: R_TOT_SIZE DS0s SDF-MF: R_TOT_SIZE
(no. DS0s DS0s
SDF-MF: R_TOT_SIZE R_DATA_LAST Word Format This word maintained microprocessor
DS0s (no.-of DS0s
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Field (Bits) used (15:13) LAST_CHAN (12:8)
Description Write with maintain future software compatibility. Channel number last with R_CHAN_ALLOC table (refer "R_CHAN_ALLOC(15:0) Word Format" "R_CHAN_ALLOC(31:16) Word Format" page153). Write with maintain future software compatibility. Write with maintain future software compatibility. Number signaling bytes minus structure (for example, SDF-MF with DS0s, R_DATA_LAST E1-SDFMF with seven DS0s signaling nibble unused. used UDF-ML UDF-HS mode.
R_DATA_LAST no.- of-DS0s
used (7:6) Reserved (5:4) R_DATA_LAST (3:0)
R_TOT_LEFT Word Format This word read-only maintained RALP Field (Bits) used (15:13) R_DBCES_BM_LEFT (12:11) R_DBCES_BM_ACT (10) R_TOT_LEFT (9:0) Description Driven with Mask reads maintain future software compatibility. Total unprocessed bytes remaining mask structure. Activity detected Mask. Used indicated whether channels DBCES structure active not. Total bytes minus remaining structure. used UDF-ML UDF-HS mode.
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R_SN_CONFIG Word Format This word maintained microprocessor
Field (Bits) R_CONDQ_DATA (15:8) ROBUST_SN_EN INSERT_DATA (6:5)
Description Value conditioned data inserted into lost cells depending value INSERT_DATA. enable "Robust algorithm". "Fast Algorithm". Controls format data inserted lost cells: Insert Insert data from R_CONDQ_DATA. Insert data from receive buffer.
Insert data from R_CONDQ_DATA with controlled pseudorandom number algorithm (not valid UDF-HS). DISABLE_SN NODROP_IN_START set, sequence number processing disabled. Statistics will still kept cells will dropped errors. "Fast Algorithm" processing, first cell received will always dropped because sequence been established yet. This disables automatic dropping cells while START state When SN_STATE equals 000b received cell will dropped. When SN_STATE equals 000b received cell with valid will accepted. MAX_INSERT (2:0) maximum number cells that will inserted when cells lost. number cells lost exceeds MAX_INSERT, then queue will forced into underrun. this value 000b, interpreted same 111b, which means that seven cells will inserted.
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R_CHAN_ALLOC(15:0) Word Format This word maintained microprocessor Field (Bits) R_CHAN_ALLOC (15:0) Description table with allocated this queue DS0s line defined queue /32. UDF-ML UDF-HS modes, initialize FFFFH. (DS0 15).
R_CHAN_ALLOC(31:16) Word Format This word maintained microprocessor Field (Bits) R_CHAN_ALLOC (31:16) Description table with allocated this queue DS0s line defined queue /32. UDF-ML UDF-HS modes, initialize FFFFH. (DS0 15).
R_DROPPED_CELLS Word Format This word read-only maintained RALP R_DROPPED_CELLS 16-bit rollover count Descriptionnon-OAM cells. dropped Field (Bits) Initialize Once initialized, write this (15:0) word. Cells dropped Pointer mismatch. Overrun. Blank allocation table processing. Structured cell received while underrun structure start been found yet.
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R_UNDERRUNS Word Format This word read-only maintained RALP Field (Bits) R_UNDERRUNS (15:0) Description 16-bit rollover count occurrences underrun this queue. This atmfCESBufUnderflows counter. Initialize Once initialized, write this word. Underruns counted RALP, which does know underrun occurred until cell received while underrun. ensure underrun count correct, counter incremented until queue exits underrun state enters resume state underrun condition. determine queue underrun, check level R_UNDERRUN R_LINE_STATE register. this set, then increment underrun count current count.
R_LOST_CELLS Word Format This word read-only maintained RALP Field (Bits) R_LOST_CELLS (15:0) Description 16-bit rollover count cells that were detected lost. This atmfCESLostCells counter specification. Initialize Once initialized, write this word.
R_OVERRUNS Word Format This word read-only maintained RALP Field (Bits) R_OVERRUNS (15:0) Description 16-bit rollover count occurrences overrun this queue. This atmfCESBufOverflows counter specification. Initialize Once initialized, write this word.
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R_POINTER_REFRAMES Word Format This word read-only maintained RALP Field (Bits) R_POINTER_REFRAME (15:0) Description 16-bit rollover count occurrences pointer reframes this queue. This atmfCESPointerReframes counter specification. Initialize Once initialized, write this word.
R_PTR_PAR_ERR Word Format This word read-only maintained RALP Field (Bits) R_PTR_PAR_ERR (15:0) Description 16-bit rollover count occurrences pointer parity errors this queue. This atmfCESPointerParityErrors counter specification. Initialize Once initialized, write this word.
R_MISINSERTED Word Format This word read-only maintained RALP Field (Bits) R_MISINSERTED (15:0) Description 16-bit rollover count occurrences misinserted cells this queue. This atmfCESMisinsertedCells counter specification. Initialize Once initialized, write this word.
R_ROBUST_SN Word Format This word read-only maintained RALP Field (Bits) Reserved (15) Description Used indicate when first cell received connection.
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Field (Bits) R_RSN_RESUME (14) R_RSN_CHAN_PTR (13:9) R_RSN_WRT_PTR (8:0)
Description Indication that stored cell first cell after underrun. Pointer channel number which start dropping previously stored cell. Pointer frame which cell receiver writing Robust processing.
R_RD_PTR_LAST Word Format This word read-only maintained RALP Field (Bits) used (15:9) R_RD_PTR_LAST (8:0) Description Driven with Mask reads maintain future software compatibility. Pointer frame that last read when last cell received. This used determine whether more than cells have been lost when error occurs help maintain integrity through underrun.
7.2.12 R_OAM_QUEUE Organization: cells bytes Base address within A1SP: E000H Index: Type: Read/Write Function: receive signaling queue stores signaling received from UTOPIA interface. Initialization: necessary initialize this structure. Format: data bytes word
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R_OAM_QUEUE Format Offset 00000H 00010H 01FFFH Name R_OAM_CELL_0 R_OAM_CELL_1 R_OAM_CELL_255 Description Receive cell Receive cell Receive cell
R_OAM_CELL_n Format Offset Word Word Word Word Word Word CRC_10_PASS Word Format Field (Bits) CRC_10_PASS (15) used (14:0) Description CRC_10_PASS cell passes CRC-10 check. Write with maintain future software compatibility. Bits (15:8) Header Header Header (HEC) Payload Payload CRC_10_PASS Bits (7:0) Header Header Blank Payload Payload
7.2.13 RESERVED (Receive Data Buffer) This structure reserved must initialized initial setup. RX_COND some channels "11" (insert data during underrun),
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then those channels need initialized some other value data unacceptable, since queues will reset underrun state. Software modifications this location after setup will cause incorrect operation. Organization:Each line separate receive data buffer consisting frame buffers. Each frame buffer store bytes. structured data applications, this allows storage 512frames multiframes data. Structured applications only first bytes each frame buffer data storage. Also, only first frame buffers every used store structured data frames. This provides frames storage, multiframes. Unstructured applications store bits data every frame buffer. with signaling, structure with channels. Base address within A1SP: 10000H Index (line): 2000H Type: Read/Write Function: data buffers store receive data information. data stored buffers order that they will played lines. Initialization: Initial startup. RX_COND some channels "11" (insert data during underrun), then those channels need initialized some other value data unacceptable. Format: data bytes word.
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R_DATA_BUFFER_n Word Format Field (Bits) R_DATA_H (15:8) Receive data for: Channel (offset frame (offset 256) frame (offset 512) multiframe (offset 8192) 256. multiframe (offset 8192) 512. Line offset 8192. offset line 8192 multiframe(E1) frame(E1) (chan-1) offset line 8192 multiframe(T1) frame(T1) (chan-1) R_DATA_L (7:0) Receive data for: Channel (offset frame (offset 256) frame (offset 512) multiframe (offset 8192) 256. multiframe (offset 8192) 512. Line offset 8192. offset line 8192 multiframe(E1) frame(E1) channel offset line 8192 multiframe(T1) frame(T1) channel Description
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CONFIGURING LINE INTERFACE line interface block responsible passing data between A1SP blocks converting appropriate protocol used external lines. mode module determined value LINE_MODE pins during hardware reset. This mode read software LINE_MODE bits LINE_MODE_REG (0x80210). following encoding used: LINE_MODE [1:0] "00" "01" Line Interface Mode Direct Speed AAL1gator-32 Supports T1/E1 links. Supports T1/E1 links links. Supports T1/E1 links. Supports T3/E3/STS1/STM-0 links. AAL1gator-8 Supports T1/E1 links. Supported Supports T1/E1 links. Supports T3/E3/STS1/STM-0 link. AAL1gator-4 Supports T1/E1 links. Supported Supports T1/E1 links. Supports T3/E3/STS1/STM-0 link.
"10" "11"
H-MVIP High Speed
Note: mode supported AAL1gator-8 AAL1gator-4. Figure shows block diagram Line Interface Block AAL1gator-32. block consists Block, H-MVIP Block mux/demux logic.
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Figure Line Interface Block Architecture
A1SP
DROP
A1SP
BLOCK
A1SP
MVIP
Lines(0:7) Lines(8:15)
A1SP
mux/demux logic selects between links non-SBI links. mux/demux logic selects between H-MVIP data external direct links. upper lines only used H-MVIP, mode. high speed mode, external lines used, they mapped internal links Conventions following conventions used this section: 32/8/4 lines, which connect AAL1_LI A1SP blocks, called local links. lines external interface called external lines. direction from local links external line interface call transmit direction. direction from external line interface local links called receive direction. individual data streams within interface known tributaries. Once inside AAL1_LI, these data streams known links. mode links tributary numbe
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