PM73122 AAL1GATOR-32 PRELIMINARY INFORMATION ISSUE OCTOBER 2
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RELEASED REFERENCE DESIGN PMC-1990887 ISSUE AAL1GATOR-32
PM73122
AAL1GATOR-32
PRELIMINARY INFORMATION ISSUE OCTOBER 2001
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1990887 ISSUE AAL1GATOR-32
PUBLIC REVISION HISTORY Issue Issue Date Details Change January 2000 November 2000 January 2001 October 2001 Document created. AAL1gator SRAMs changed schematics part availability. Pull-downs added signals UTOPIA buses. Clarifications made document. Byte Write Enable lines corrected (swapped) AAL1gator-32 SRAMs schematics. Added appendix Adaptive Clock Recovery VHDL source code, changed document status from preliminary released, match production release AAL1gator-32 device.
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CONTENTS INTRODUCTION PURPOSE SCOPE APPLICATIONS
FEATURES.2 GENERAL DESCRIPTION BLOCK DESCRIPTIONS.5 SPECTRA-155.5 TEMUX AAL1GATOR-32.6 S/UNI-APEX.12 S/UNI-ATLAS MICROPROCESSOR INTERFACE CPLD POWER SUPPLY
TESTABILITY IMPLEMENTATION DESCRIPTION.20 GLOSSARY REFERENCES DISCLAIMER.24 APPENDIX AAL1GATOR-32 REFERENCE DESIGN SCHEMATICS APPENDIX MICROPROCESSOR CPLD VHDL CODE.26 APPENDIX EXTERNAL SRTS VHDL CODE
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APPENDIX EXTERNAL ADAPTIVE CLOCK RECOVERY VHDL CODE
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LIST FIGURES FIGURE AAL1GATOR-32 REFERENCE DESIGN FIGURE SPECTRA-155 STS-3 CONFIGURATION.6 FIGURE AAL1GATOR-32 CONFIGURATIONS FIGURE TEMUX- AAL1GATOR-32 INTERFACE FIGURE SRTS-BASED DS3/E3 CLOCK RECOVERY CIRCUIT.12 FIGURE MICROPROCESSOR INTERFACE BLOCK.16 FIGURE SIMPLE SYSTEM TEST BENCH BLOCK DIAGRAM FIGURE COMPLEX SYSTEM TEST BENCH BLOCK DIAGRAM
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INTRODUCTION AAL1gator-32 Circuit Emulation Service (CES) Reference Design provides SONET/SDH network with access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. AAL1gator-32 Reference Design based compact standard. However, this reference design paper reference design only been built tested.
Purpose This document provides detailed hardware specification AAL1gator-32 Reference Design. This specification detailed enough allow design implementation verification.
Scope purpose this reference design assist engineers designing their products using PMC-Sierra's PM73122 AAL1gator-32 PM8315 TEMUX devices. block diagram shown design. description then given functional blocks design. detailed implementation description then follows.
Applications DACS with Ainterface. Service, Port Application. AAccess Multiplexers. Part Digital Access Cross-connect Systems (DACS) Replacement. High density T1/E1 interfaces multiplexers, multi-service switches, routers digital modems. SONET/SDH Drop Multiplexers. SONET/SDH Terminal Multiplexers.
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FEATURES Supports OC-3 capacity, scaleable OC-12. Supports rates channelized unchannelized mode. Supports Aand services. Telecom Add/Drop connects VT/TU channelized SONET/SDH processor (SPECTRA-155) high density framer (TEMUX) support T1/E1 mapped payloads. Microprocessor interface utilized bridge connector.
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GENERAL DESCRIPTION block diagram design shown Figure consisting several blocks. design single Compact card using PM5342 SPECTRA-155, three PM8315 TEMUXes, three PM73122 AAL1gator-32s, PM7324 ATLAS, PM7326 APEX, PLX9054 bridge, CPLDs HFCT-5205 optical transceiver. Figure AAL1gator-32 Reference Design
Connector CPLDs Bridge
Data &Address
Telecom
ANY-PHY
UTOPIA
PM8315 TEMUX
PM73122 AAL1gator
Connector
UTOPIA LEVEL
PM5342 SPECTRA
PM8315 TEMUX
PM73122 AAL1gator
PM7326 APEX
UTOPIA LEVEL
PM7324 ATLAS
PM8315 TEMUX
PM73122 AAL1gator
Hewlett Packard HFCT-5205 optical transceiver provides SONET/SDH compliant link serial signal rate 155.52 Mbit/s. transceiver performs optical-to-electrical conversion, converting OC-3 optical signal into STS3/STM-1 stream vice versa. This transceiver communicates with
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PM5342 SPECTRA PECL interface. SPECTRA extracts/aligns SONET/SDH payload acts Telecom interface. TEMUX devices receive/transmit data through Telecom data then passed through T1/E1 framers. then formatted transmission AAL1gator-32 devices CBR/VBR servicing. APEX ATLAS perform routing, switching, traffic policing shaping cells. APEX ATLAS connected AAL1gator-32 UTOPIA connector such that cells first pass through ATLAS that policing functions performed first. microprocessor interface, utilized connector bridge, configures, controls monitors above devices. CPLD design used generate frame pulse signal SPECTRA-155, TEMUX, AAL1gator-32 devices generate chip select signals PMC-Sierra devices board. Power requirements board +5V, +3.3V 2.5V. SPECTRA-155 requires while TEMUX, AAL1gator-32, APEX devices require +2.5V power supply. ATLAS requires +3.3V. SPECTRA-155, TEMUX, AAL1gator-32, S/UNI-ATLAS devices require demultiplexed address data microprocessor interfaces while S/UNIAPEX requires 32-bit multiplexed microprocessor bus. order provide maximum system implementation flexibility, bridge chip been used. 80-pin female UTOPIA connectors carry receive transmit UTOPIA signals between S/UNI-ATLAS external board Parallel Cell Traffic Generator Analyzer such E1401B UTOPIA Tester. design also includes several circuits device alarms power indications.
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BLOCK DESCRIPTIONS SPECTRA-155 SPECTRA-155 SONET/SDH payload extractor/aligner STS-1, STS-3 STS-3c interface applications, operating serial interface speeds Mb/s. receive direction, SPECTRA-155 receives SONET/SDH frames serial interface, recovers clock data, terminates SONET/SDH regenerator section, multiplexer section path overhead. performs framing, descrambling, detects alarm conditions, monitors section line interleaved parity. addition, SPECTRA-155 interprets received payload pointers extracts Synchronous Payload Envelope (SPE). extracted SPECTRA-155 placed Telecom DROP bus. SPECTRA-155 maps three DS3s from STS-3 provides serialized streams with derived clocks. transmit direction, SPECTRA-155 transmits SONET/SDH frames, serial interface, formats section, line path overheads. performs framing pattern insertion, scrambling, alarm signal insertion, creates section line interleaved parity. addition, SPECTRA155 generates transmit payload pointers. inserted either sourced from Telecom stream, from serial streams, from data streams. Telecom applications, SPECTRA-155 maps from Telecom into transmit stream. Figure shows direct interface SPECTRA-155 Telecom bus. SPECTRA-155 uses analog power pins QAVD, RAVD, TAVD, which must applied after VDD. simple filtering network placed each analog pins delay voltage rise until digital pins proper voltage. more information about SPECTRA-155, please refer [1].
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Figure
SPECTRA-155 STS-3 Configuration
SMODE[2:0]="000"
AC1J1V1 AD[7:0]
Telecombus Interface
PM5342 SPECTRA-155
DC1J1V1 DD[7:0]
Telecombus Drop Interface
TEMUX TEMUX integrated circuit which integrates framers, framers, SONET/SDH VT1.5/V2/TU-11/TU-12 asynchronous mapper full featured multiplexer with framer. also contains SONET/SDH mapper terminating multiplexed streams, SONET/SDH mapped streams SONET/SDH mapped streams. Virtual Tributary VT1.5 carries enough bandwidth transport signal DS0s Kb/s. Analogously, carries enough bandwidth transport (2.048 Mb/s) signal. multiplexing process involves combination (1.544 Mb/s) signals into single signal (44.736 Mb/s). asynchronously mapped into STS-1 SPE. Three STS-1 signals form STS-3. device supports byte serial Scalable Bandwidth Interconnect (SBI) interface high density system side device interconnection streams, streams, streams streams. line side TEMUX supports SONET/SDH Telecom provides 8-bit microprocessor interface configuration, control, status monitoring. more information about TEMUX, please refer references.
AAL1gator-32 purpose AAL1gator-32 provide high density T1/E1, DS3/E3/J2 line interfaces access AAL1 Anetwork. AAL1gator-32 support links PMC-Sierra's eight 8Mb/s H-MVIP links.
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AAL1gator-32 capable supporting 1024 VCs. Figure indicates ways which AAL1gator-32 used connect T1/E1 DS3/E3/J2 line interfaces. Figure AAL1gator-32 Configurations
UTOPIA
AAL1gator-32
Structured unstructured T1/E1 with support MVIP Switch Framers Mapper (TEMUX) Unstructured DS3/E3/J2
T1/E1 Framer (TQUAD/EQUAD) T1/E1 Framer+LIU (COMET)
DS3/E3/J2 Framer (S/UNI-QJET)
T1/E1 (QDSX)
(D3MX)
(TUPP-PLUS)
(SPECTRA-155)
DS3/E3/J2
this design each AAL1gator-32 interfaces with PM8315 TEMUX support: structured/unstructured only TEMUX used, more than TEMUX used structured/unstructured only TEMUX used, more than TEMUX used
When used with TEMUX, AAL1gator-32 part multiservice switch application which provide circuit emulation services pipes being carried over OC-3 link. also provide circuit emulation services unstructured link. This system scalable OC-12 system, using SPECTRA-622 instead SPECTRA-155 more TEMUX AAL1gator-32 devices.
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AAL1 Segmentation Reassembly (SAR) Processor (AAL1gator-32) monolithic single chip device that provides DS1, line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external SRAM storage configuration, user data, statistics. Some device's important functionality follows: Compliant with AForum's Circuit Emulation Services (CES) specification (AF-VTOA-0078), ITU-T I.363.1 Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with AForum's DBCES specification (AF-VTOA-0085). Supports idle channel detection processor intervention, signaling, data pattern detection. Provides idle channel indication channel basis. Provides AAL1 segmentation reassembly individual lines direct speed mode, H-MVIP lines Mb/s H-MVIP mode, lines high speed mode. Using Scalable Bandwidth Interconnect (SBI) Interface, provides AAL1 segmentation reassembly VT1.5, links, links. Provides standard UTOPIA level Interface which optionally supports parity runs MHz. following modes supported: 16-bit Level Multi-Phy Mode (MPHY) 8-bit Level MPHY 8-bit Level AMaster
Supports 1024 Virtual Channels (VC). Supports (consecutive channels) (non-consecutive channels) structured data format.
Each AAL1gator-32 interfaces with TEMUX through PMC-Sierra's bus. high level design this interface shown Figure
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Figure
19.44
TEMUX- AAL1gator-32 Interface
DROP
SREFCLK SC1FP Interface
REFCLK C1FP C1FP Interfcae Interface
TEMUX
AAL1gator-32
SBIACT SBIDET0 SBIDET1
AACTIVE ADETECT
SREFCLK SC1FP
TEMUX Interfcae
SBIACT SBIDET0 SBIDET1
REFCLK REFCLK C1FP C1FP Interface
AAL1gator-32
AACTIVE ADETECT
SREFCLK SC1FP Interface
REFCLK C1FP Interface
TEMUX
AAL1gator-32
SBIACT SBIDET0 SBIDET1
AACTIVE ADETECT
This reference design uses zero turnaround (ZBT) synchronous SRAM AAL1gator-32 that highest degree performance available. SSRAM should used situations where AAL1gator-32 configured large number partial cell large number being used over channels. normal operation, pipelined single-cycle deselect SSRAM (nonZBT) will suffice. Note that connections between AAL1gator-32 non-ZBT SSRAM slightly different. Refer AAL1gator-32 datasheet datasheet SSRAM being used details.
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PMC-Sierra does recommend specific manufacturer's SSRAM. list possible solutions provided below; however, this list should considered exhaustive. Pipelined Single-Cycle Deselect SSRAM (non-ZBT) Motorola MCM69P819-4 (TQ4) Galvantech (Cypress) GVT71256G18-6 Micron MT58L25618P-10 Technology GS84018T/B-100 Zero Turnaround (ZBT) SSRAM Cypress CY71352 Micron MT55L256L18P-10 Motorola MCM63Z818-100 (TQ133) AAL1gator-32 capable internally synthesizing E1/T1 clock each line using both synchronous residual timestamp (SRTS) adaptive clock recovery methods unstructured data format (UDF-ML) mode. AAL1gator32 able internally synthesize DS3/E3 line rate clock; however, AAL1gator-32 does output both SRTS adaptive clock recovery information Clock Generation Control (CGC) port support external DS3/E3 clock synthesis DS3/E3 signals. port AAL1gator-32 connected CPLD that different functions implement externally. These possible functions are: External control AAL1gator-32 internal T1/E1 clock synthesizers implement custom SRTS algorithm. Generation external TL_CLK sources AAL1gator-32 when mode. Read nibbles implementation external adaptive clocking algorithm. Read nibbles implementation external DS3/E3 SRTS clock recovery algorithm. Read nibbles implementation external DS3/E3 adaptive clock recovery algorithm.
last points suggest, high speed SRTS information from AAL1gator-32's SRTS port used synthesize control clock externally. circuitry external DS3/E3 SRTS shown Figure
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Some external algorithms digital analog filtering between certain stages circuitry; however, PMC-Sierra found circuitry Figure synthesize track appropriate clock well therefore PMC-Sierra does recommend other filtering. External SRTS implemented within this reference design. However, Analog Devices AD7302 8-bit VCXO MVA3025HACY (DS3: 44.736 MHz, 34.368 MHz) have been used with success. Similar devices also available from other manufactures. VHDL code CPLD given Appendix
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Figure
SRTS-based DS3/E3 Clock Recovery Circuit
Network-Derived 77.76
NCLK
CGC_DOUT CGC_LINE SRTS_STRB
D0-D7
PM73122 AAL1gator-32
CPLD
8-bit (AD7302)
TL_CLK(0)
VOUT
VCXO
This circuit functions follows: AAL1gator-32 asserts SRTS_STRB indicating SRTS nibble available CGC_DOUT line indicated CGC_LINE. lookup table within CPLD then used convert CGC_DOUT nibble into 8-bit code drive digital-to-analog converter (DAC). output voltage then controls voltage-controlled oscillator VCXO, which center frequency. resulting clock then AAL1gator-32 TL_CLK(0) input LIU. Note that NCLK must network derived, SYSCLK asynchronous network. circuit shown Figure above also used DS3/E3 adaptive clock recovery with following changes: network-derived 77.76 clock used, output ADAP_STBH should connected CPLD. Adaptive Clock Recovery CPLD implementation given Appendix more detailed description AAL1gator-32, please refer references. S/UNI-APEX PM7326 S/UNI-APEX full duplex Atraffic management device, providing cell switching, queuing, traffic shaping, congestion
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management, hierarchical scheduling 2048 loop ports ports. S/UNI APEX provides per-VC queuing VCs. per-VC queue allocated Class Service (COS), within port, either direction (ingress egress path). Per-VC queuing enables per-VC shaping ports greater fairness bandwidth allocation between within COS. APEX supports 8/16-bit Any-PHY compliant loop side master/slave interface supporting 2048 ports. Egress cell transfers across interface identified inband port identifier prepended cell. slave devices must match inband port identifier with their port port range order accept cell. port egress flow control effected 12bit address polling which appropriate slave device responds with band port flow control status. Ingress cell transfers across interface effected combination UTOPIA flow control polling device selection slave devices. Any-PHY loop side interface reconfigured standard single port 16-bit Any-PHY UTOPIA compliant slave interface. 16-bit prepends optionally supported both ingress egress cell flow identification enabling with external address resolution devices, switch fabric interfaces, other layer devices. S/UNI APEX provides 8/16-bit Any-PHY UTOPIA compliant side master interface supporting ports. 16-bit prepends optionally supported both ingress egress cell flow identification enabling with external address resolution devices, switch fabric interfaces, other layer devices. S/UNI APEX provides 36-bit SSRAM interface context storage supporting context 64kVCs 256k cell buffer pointer storage. Context Memory protection provided bits parity over each 34-bit word. S/UNI-APEX should used functions such VC-based switching traffic management required within design. Traffic management includes congestion management, class service aware scheduling, shaping. more information about S/UNI-APEX, please refer references. S/UNI-ATLAS PM7324 S/UNI-ALayer Solution (S/UNI-ATLAS, simply ATLAS) PMC-Sierra standard product that implements following ALayer functions:
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processing according ITU-T I.610 1995 1998 living list. Header Translation full VPI/VCI address range. Prepend/Postpend tagging. Cell rate policing according ITU-T I.371 using Generic Cell Rate Algorithm. Policing according AForum's Traffic Management 1998 living list. Per-PHY queuing prevent head-of-line blocking.
ATLAS performs both ingress egress functionality. ingress side SCI-PHY level interface input, SCI-PHY level interface output. Cells coming into ATLAS from identified according VPI, VCI. cells processed according information stored context particular connection. Cells also copied microprocessor cell interface external processing. egress SCIPHY level interface both input output interface. connection identified according VPI, VCI, processed according information external particular connection. with ingress, cells copied microprocessor cell interface external processing. ATLAS configured controlled through generic asynchronous microprocessor bus. S/UNI-ATLAS should used applications where policing I.610 compliance required, when traffic destined AWAN switch. Policing ingress traffic performed ensure that actual traffic pattern fits within contract (possibly DBCES applications). counters also available within S/UNI-ATLAS monitoring bandwidth. S/UNI-ATLAS utilized such that ingress cells pass first through S/UNI-ATLAS, then through S/UNI-APEX, then back through S/UNI-ATLAS again. This setup allows ingress packets policed ingress network, cells looped back I.610 compliance. more detail traffic management switching, please refer references. more detailed description S/UNI-ATLAS, please refer references.
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Microprocessor Interface CPLD illustrated Figure microprocessor interface card implemented using CompactPCI standards with cPCI connector, 9054 chip CPLD. This interface provides external host connection perform following functions AAL1gator-32 Reference Design: Configuration SPECTRA-155, TEMUX, AAL1gator-32, S/UNI-APEX, S/UNI-ATLAS devices Setting connections AAL1gator-32, S/UNI-APEX, S/UNI-ATLAS context RAMs Monitoring alarms interrupts SPECTRA-155, TEMUX, AAL1gator-32, S/UNI-APEX, S/UNI-ATLAS devices Background Debug mode board's feature tests.
Note that second CPLD included design clocking; however, VHDL code included this CPLD external clocking options because AAL1gator-32 capable performing these functions internally. Only users wishing implement their algorithm externally need implement this CPLD. essential characteristic concept strict decoupling external processor's main memory subsystems standard expansion means bridge. PLX's 9054 bridge v2.2 compliant 32bit, master interface controller which enables burst transfers Mbytes second. Since S/UNI-APEX requires multiplexed address/data bus, 9054 configured multiplexed mode mode) local side. shown Figure 32-bit multiplexed AD[31:0] Address/Data from 9054 directly connected APEX address/data pins. remaining devices, means their Address Latch Enable (ALE) pins, have microprocessor interface option work with multiplexed address/data bus. latches address signals during address phase transaction. Therefore, except APEX, AD[31:0] connected data port other devices. proper resistive termination along line necessary help with signal integrity. additional A[28:2] address connected other devices which need separate address lines through CPLD. Also, CPLD used generate chip select other microprocessor control signals devices.
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Figure
Microprocessor Interface Block
Serial EEPROM
AD[31:0] Serial EEPROM Interface AD[31:0] Control AD[27:0] CS_0
APEX
PCI_AD [31:0] A[28:2] A[28:2]
[8:0] A[11:0] D[15:0] A[19:0] Control CS_1 Control
cPCI
9054 CPLD
_Control Control Signals Control
ATLAS
A[19:0]
D[15:0]
AAL1gator32
Control CS_2
TEMUX TEMUX
A[13:0] D[7:0]
TEMUX
Control CS_5
TEMUX TEMUX
A[9:0] D[7:0]
SPECTRA-155
Control CS_8
Power Supply Power provided AAL1gator-32 Reference Design through Compact interface. PMC-Sierra's devices require that +3.3V power rail higher voltage than +2.5V power rail times. This achieved regulating lower voltage from higher voltage, shown page schematics appendix. +5.0V +3.3V taken from Compact interface. +2.5V then regulated using LT1580 regulator. This regulator designed have dropout voltage, therefore requires +5.0V well. However, most current drawn from +3.3V rail. zener diode added +5.0V rail
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dampen voltage spikes LEDs connected across each supply rails indicate presence voltage.
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TESTABILITY Figure illustrates simple test bench connection AAL1gator-32 Reference Design Card. required tester/analyzer testing reference design card must capable embedding Acells inside frames, inside stream, inside Synchronous Payload Envelope (SPE). 37717C communications performance analyzer equipped with optical interfaces, optical adaptor, SONET/SDH test interfaces, PDH/DSn Atest interfaces, Aservices layer test options used this purpose. analyzer sources STS-3 data receiver receives returned data from transmitter part optical data link module reference design card. Figure Simple System Test Bench Block Diagram
Development/Debug
Interface
37717C Analyzer
AAL1gator-32 Reference Design Card
UTOPIA Interface
Figure illustrates complex test bench connection AAL1gator-32 Reference Design Card. optical transceiver attached external SONET test equipment which sources data into receiver receives returned data from transmitter part optical data link module card. Cell Traffic Generator Analyzer such E14011B receives/transmits monitors Acell traffic from/to reference design card through UTOPIA connector board.
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Figure
Complex System Test Bench Block Diagram
Development/Debug
Interface
SONET Tester
AAL1gator-32 Reference Design Card
UTOPIA Interface
Cell Traffic Generator Analyzer E1401B)
UTOPIA Port
diagnostic loopback mode devices used loopback transmit data receive path. cPCI port Reference Design Card allows microprocessor interface with host (the development/debug monitor status SPECTRA-155, TEMUX, AAL1gator-32, S/UNI-APEX, S/UNI-ATLAS devices. This port also used program registers initialization, software load reset, diagnostics.
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IMPLEMENTATION DESCRIPTION schematic contains pages follows: Sheet Root Drawing This sheet provides block view interface signals between each block AAL1gator-32 Reference Design. Sheet Optical Interface This sheet shows connections needed HFCT5205 optical transceiver. Sheet SPECTRA-155 This sheet contains PM5342 SPECTRA-155, alarm LEDs, other supporting circuitry. Sheet 4-9: Temuxes Block These sheets contain PM8315 TEMUXes their connections. Sheet 10-18: AAL1gator-32 Block These sheets contain PM73122 AAL1gator-32s including their synchronous SRAMs. Sheet 19-21: Apex Block These sheets contain PM7326 APEX requied synchronous DRAM SRAM. Sheet 22-23: Atlas Block These sheets contain PM7324 ATLAS required synchronous SRAM. Sheet UTOPIA Connector This sheet contains transmit receive UTOPIA Level connector. Sheet Oscillator Block This sheet contains crystal oscillator UTOPIA buses.
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Sheet 26-28: CPLD Block These sheets contain CPLDs that used generate frame pulses distribute clock signals. Sheet Power Reset Block This sheet contains voltage regulators powering devices.
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GLOSSARY AAL1 ASAP ACBR SCI-PHY SRTS UTOPIA AAdaptation Layer Service-Any Port Asynchronous Transfer Mode Constant Rate Circuit Emulation Services Class Service Peripheral Component Interconnect Segmentation Re-assembly PMC-Sierra enhanced UTOPIA Scalable Bandwidth Interconnect Synchronous Residual Time Stamp Universal Test Operations Interface AVariable Rate Virtual Circuit Virtual Channel Connection Virtual Circuit Identifier Virtual Path Virtual Path Connection Virtual Path Identifier Wide Area Network Zero Turnaround
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REFERENCES PMC-Sierra Inc., PMC-970133, "SONET/SDH Payload Extractor/Aligner Mbits/s Telecom Standard Product Data Sheet", August 1998, Issue PMC-Sierra Inc., PMC-981125, "High Density T1/E1 Framer With Integrated VT/TU Mapper Multiplexer Telecom Standard Product Data Sheet", June 1998, Issue PMC-Sierra Inc., PMC-981419, "AAdaptation Layer Segmentation Reassembly Processor-32 (AAL1gator-32) Telecom Standard Product Data Sheet", December 1998, Issue PMC-Sierra Inc., PMC-981224, "ATM/Packet Traffic Manager Switch (S/UNI-APEX) Data Sheet", Issue PMC-Sierra, Inc., PMC-1981024, "Traffic Management Switching Using Vortex Chipset: S/UNI-APEX Technical Overview", August 1999, Issue 1.0. PMC-Sierra Inc., PMC-971154, "S/UNI-ALayer Solution Data Sheet", January 1999, Issue
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DISCLAIMER This document paper reference design and, such, been built tested.
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APPENDIX AAL1GATOR-32 REFERENCE DESIGN SCHEMATICS
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REVISIONS
ZONE DESCRIPTION DATE APPR
PAGE 25MHZ_OSCILLATOR_BLOCK PAGES 10-18 AAL1GATOR_32_BLOCK RPHY_CLK PAGE SPECTRA_155_BLOCK TELECOM_AC1J1V1 TELECOM_AD<7.0> TELECOM_ADP TELECOM_APL PAGE OPTICAL_INTERFACE RXDP RXDN TXDP TXDN TELECOM_DC1J1V1 TELECOM_DD<7.0> TELECOM_DDP TELECOM_DPL RXDP RXDN TXDP TXDN RXDP RXDN XCLK TXDP TXDN SS1_DFP SS0_DCK RRCLK TRCLK SS13_ACK CICLK<2.0> SPECTRA_UP_CONTROL<4.0> CECLK<2.0> CTCLK<1.0> RECVCLK1 L_AD<31.0> TEMUX_UP_CONTROL<10.0> CHIP_ADDRESS<19.0> CHIP_ADDRESS<19.0> JTAG<2.0> TDO13 TDO1 JTAG<2.0> TDO1 TDO4 L_AD<31.0> SREFCLK SREFCLK TELECOM_AC1J1V1 TELECOM_AD<7.0> TELECOM_ADP TELECOM_APL TELECOM_DC1J1V1 TELECOM_DD<7.0> TELECOM_DDP TELECOM_DPL PAGES TEMUXES_BLOCK TELECOM_AC1J1V1 TELECOM_AD<7.0> SBI_AV5 SBI_AD<7.0> TELECOM_ADP SBI_ADP TELECOM_APL TELECOM_DC1J1V1 TELECOM_DD<7.0> TELECOM_DDP TELECOM_DPL LAC1 CLK52M LREFCLK XCLK ADJUST SBI_APL SBI_DV5 SBI_DD<7.0> SBI_DDP SBI_DPL C1FP ADJUST SBI_AV5 SBI_AD<7.0> SBI_ADP SBI_APL SBI_DV5 SBI_DD<7.0> SBI_DDP SBI_DPL SBI_AV5 SBI_AD<7.0> SBI_ADP SBI_APL SBI_DV5 SBI_DD<7.0> SBI_DDP SBI_DPL C1FP ADJUST ANYPHY_TDAT<15.0> ANYPHY_TADR<3.0> ANYPHY_TENB SREFCLK ANYPHY_TPA ANYPHY_TPAR AAL_UP_CONTROL<13.0> ANYPHY_TSX L_AD<31.0> FASTCLK AACTIVE<3.1> ADETECT<3.1> TL_CLK<95.0> RL_CLK<5.0> CHIP_ADDRESS<19.0> CGC_VALID<2.0> CGC_SER_D<2.0> CGC_DOUT<11.0> CGC_LINES<14.0> SRTS_STRB<2.0> ADAP_STRB<2.0> RSTB TDAT<15.0> TDAT<15.0> TADR<4.0> TADR<4.0> TPRTY TWRENB TSOC BCLK LTCLK LRCLK WRDAT<15.0> WRPRTY WRENB WRPA WRSOP WRDAT<15.0> RDAT<15.0> WRPRTY RADR<4.0> WRENB RPRTY WRPA RRDENB WRSOP RSOC OFCLK RFCLK WTDAT<15.0> WTADR<2.0> WTPRTY WTENB TDAT<15.0> WTPA TADR<4.0> WTSOP TPRTY TWRENB TSOC ATLAS_UP_CONTROL<5.0> L_AD<31.0> CHIP_ADDRESS<19.0> JTAG<2.0> TDO10 TDO12 JTAG<2.0> TDO12 TDO13 TPHY_CLK RPHY_CLK TPHY_CLK LRCLK LTCLK BCLK RDAT<15.0> RADR<4.0> RFCLK OFCLK LCLK_CPLD LCLK WRCLK
RDAT<15.0> RADR<4.0> RPRTY RDENB RSOC
PAGES 19-21 APEX_BLOCK
PAGES 22-23 ATLAS_BLOCK
ANYPHY_TDAT<15.0> ANYPHY_TDAT<15.0> WRCLK ANYPHY_TADR<3.0> ANYPHY_TADR<3.0> ANYPHY_TENB WTDAT<15.0> ANYPHY_TPA WTADR<2.0> ANYPHY_TPAR WTPRTY ANYPHY_TSX WTENB WTPA WTSOP APEX_UP_CONTROL<10.0>
NCLK<2.0>
AAL_SYSCLK
JTAG<2.0> TDO4 TDO10 RSTB
L_AD<31.0>
RSTB
RSTB
JTAG<2.0>
CHIP_ADDRESS<19.0> L_AD<31.0> PAGES 26-27 CPLD_BLOCK AAL_UP_CONTROL<13.0> TEMUX_UP_CONTROL<10.0> SREFCLK RECVCLK1 C1FP CTCLK<1.0> CTCLK<1.0> FASTCLK CECLK<2.0> CECLK<2.0> CICLK<2.0> CICLK<2.0> AACTIVE<3.1> ADETECT<3.1>
RSTB
PAGE UTOPIA_CONNECTOR TDAT<15.0> TADR<4.0> TPRTY TWRENB TSOC PAGE CPCI_PCI9054_BLOCK LCLK PAGE POWER RSTB PCI_VCC PCI_3_3V RDAT<15.0> RADR<4.0> RPRTY RRDENB RSOC
TL_CLK<95.0> RL_CLK<5.0> CGC_VALID<2.0> CGC_SER<2.0> CGC_SER_D<2.0> CGC_DOUT<11.0> CGC_DOUT<11.0> CGC_LINES<14.0> CGC_LINES<14.0> SRTS_STRB<2.0> ADAP_STRB<2.0> NCLK<2.0> AAL_SYSCLK SRTS_STRB<2.0> ADAP_STRB<2.0> NCLK<2.0>
APEX_UP_CONTROL<10.0> XCLK ATLAS_UP_CONTROL<5.0> LREFCLK CLK52M LA<28.2> LAC1 SS1_DFP SS0_DCK RRCLK TRCLK SS13_ACK SPECTRA_UP_CONTROL<4.0> CHIP_ADDRESS<19.0> LBE<1.0> UP_CONTROL<8.0> L_INTB L_BTERMB L_AD<31.0>
APEX_UP_CONTROL<10.0> PCI_VCC ATLAS_UP_CONTROL<5.0> PCI_3_3V LA<28.2> LBE<1.0> UP_CONTROL<8.0> LA<28.2> LBE<1.0> UP_CONTROL<8.0> L_INTB L_BTERMB L_AD<31.0>
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: DRAWING TITLE=ASAP_CES_ROOT ABBREV=ASAP_CES_ROOT LAST_MODIFIED=Thu 14:26:10 2001 TITLE: AAL1GATOR-32 DESIGN ROOT DRAWING ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:1 TRUE
SPECTRA_UP_CONTROL<4.0> CHIP_ADDRESS<19.0> RSTB LCLK_CPLD
REVISIONS
ZONE DESCRIPTION DATE APPR
NOTE:
0.01UF 0.1UF 22UF
RN166 RN166 RN166 RN166
RES_ARRAY_4
0.1UF 0.01UF 22UF
TX_VCC
RX_VCC
RXDP RXDN
SD\I RXDP\I RXDN\I
3D1< 3D1< 3D1<
LINES
HFCT5205 VEET VEER
TXDP TXDN
TXDP\I TXDN\I
3C1> 3C1>
LINES
49.9
49.9
0.01UF
DRAWING: OPTICAL_BLOCK OPTICAL_BLOCK 15:06:04 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN OPTICAL INTERFACE ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:2
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
0.01UF 0.01UF 0.01UF
REVISIONS
ZONE
SALM LAIS LRDI RALM1 RALM2 RALM3
DESCRIPTION
DATE
APPR
RES_ARRAY_4
4.7UF 0.1UF 0.1UF 0.01UF 4.7UF 0.01UF
0.01UF 4.7UF 0.1UF
RN28 RN28 RN28 RN28 RN29 RN29 RN29 RN29
SPECTRA-155 ALARMS LEDS
4.7UF 4.7UF 0.1UF 0.1UF 0.01UF 0.01UF
0.01UF 4.7UF 0.1UF
HCT540
0.1UF 0.01UF 0.01UF 4.7UF 0.1UF 4.7UF
TAVD<3.1>
RALM<3.1> RAVD<4.1>
0.01UF
4.7UF
0.1UF
4.7UF 0.1UF 0.01UF
QAVD<3.1> NC/POWER<2.1> QAVD<3.1> RAVD<4.1> VDD<29.0> TAVD<3.1> JTAG PORT
LOS/RRCPFP LAIS/RRCPDAT LRDI/RRCPCLK RALM<3.1>
SALM
TRSTB
RLOW RSUC RSOW ROWCLK
RCLK
B3E<3.1> RSLDCLK RSLD RLDCLK ROHCLK
TRIS_OHB
23E10> 5E9< 17E6< 14D5< 11E5< 9E9< 7E9< 5E9< 23B2< 21D6< 20H4< 20E4<
TDO13\I TDO1\I JTAG<2.0>\I
BYTE TELECOM MODE SS0_DCK\I SS1_DFP\I TELECOM_DD<7.0>\I RN126 RN126 RN126 RN126 RN126 RN126 RN126 RN126 RN127 RN127 RN127 RN127 RN127 RN127 RN127 RN127 RN128 RN128 RN128 RN128 RN128 RN128 RN128 RN128
SMODE0 SMODE1 SMODE2 SS10 SS11 SS12 SS13 SS14 SS15 SS16 SS17 SS18 SS19 SS20 SS21 SS22 SS23 SS24 SS25 SS26 SS27 SS28 SS29 SS30 SS31 SS32 SS33 SS34
RTOHCLK RTOH RTOHFP RPOHCLK<3.1> RPOH<3.1> RPOHFP<3.1> RTCEN<3.1> RTCOH<3.1> RRCLK+ RRCLK-
28E3> 28F3> 9F9<7F9< 5F9<
9F9< 7F9<5F9< 9F9< 7F9< 5F9< 9F9< 7F9<5F9< 28E3> 8F9> 6F9> 4F9>
TELECOM_DPL\I TELECOM_DC1J1V1\I TELECOM_DDP\I SS13_ACK\I TELECOM_AD<7.0>\I
8F9> 6E9> 4F9> 4F9> 8F9> 6E9> 4F9>
TELECOM_APL\I TELECOM_AC1J1V1\I TELECOM_ADP\I
4.7K
RN33 RN33 RN33 RN33 RN34 RN34
RTCEN<3.1> RTCOH<3.1>
0.1UF
R4375 0.01UF
RRCLK\I RXDP\I
28D9> 2F4>
PM5342
RXD+ RXD-
SPECTRA
ALOS+ ALOS-
0.01UF 0.01UF
RXDN\I SD\I
2F4> 2F4>
TRCLK+ TRCLK-
C610.01UF R40237 R39237
TRCLK\I TXDP\I TXDN\I
28D9> 2F4< 2F4<
TXD+ TXDG2 <7.0>
C620.01UF
22B8<> 21E6<> 17E6<> 14E5<> 11E5<> 4D9<> 8D9< 6C9< 29B5<> 28B3<> 26C5> 28E9<>
RSTB\I SPECTRA_UP_CONTROL<4.0>\I
MBEB WRB/RWB RDB/E RSTB INTB A<7.0> VSS<28.0> NC_GNDA<4.1> TLRDI/TRCPFP TLAIS/TRCPDAT RLAIS/TRCPCLK D<7.0> QAVS<2.1> RAVS<4.1> TAVS<3.1> NCP<5.1>
TPOHCLK<3.1> TPOH<3.1> TPOHFP<3.1> TPOHEN<3.1> TTOHCLK TTOH TTOHFP TTOHEN TOHCLK TLDCLK TSLDCLK TSLD TCLK TACK TAFP
TPOH<3.1> TPOHEN<3.1>
28F3> 17F5<> 14F5<> 11F5<> 8D9<> 6D9<> 4D9<> 28C3<> 25G3<> 22C4<> 21D10<>
CHIP_ADDRESS<19.0>\I L_AD<31.0>\I
<7.0>
RN27 RN27 RN27 RN27
RES_ARRAY_4
TLOW TSUC TSOW TOWCLK
SCPI0 SCPI1 SCPO0 SCPO1
DRAWING: SPECTRA_BLOCK SPECTRA_155 15:05:21 2001
TATP RATP
4.7K 4.7K 4.7K 4.7K
RBYP TBYP
RN23 RN23 RN30 RN30 RN30 RN30 RN31 RN31 RN31 RN31 RN32 RN32 RN32 RN32
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN SPECTRA-155 ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:3
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
REVISIONS
ZONE DESCRIPTION DATE APPR
0.01UF 0.01UF 0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
RN34 RN34 RN38 RN38
AA12 AA15
RN48 RN48 RN48 RN48 RN49 RN49 RN49 RN49
CICLK<0>\I CECLK<0>\I SBI_AD<7.0>\I
AB22 AA21
29C4>
28F3>
LREFCLK\I
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDD2V5<8>
VDD2V5<7>
VDD2V5<6>
VDD2V5<5>
VDD2V5<4>
VDD2V5<3>
VDD2V5<2>
VDD2V5<1>
CSSED CICLK CIFP CTCLK CECLK CEFP ED<28> ED<27> ED<26> ED<25> ED<24> ED<23> ED<22> ED<21> ED<20> ED<19> ED<18> ED<17> ED<16> ED<15> ED<14> ED<13> ED<12> ED<11> ED<10> ED<9> ED<8> ED<7> ED<6> ED<5> ED<4> ED<3> ED<2> ED<1> ECLK<28> ECLK<27> ECLK<26> ECLK<25> ECLK<24> ECLK<23> ECLK<22> ECLK<21> ECLK<20> ECLK<19> ECLK<18> ECLK<17> ECLK<16> ECLK<15> ECLK<14> ECLK<13> ECLK<12> ECLK<11> ECLK<10> ECLK<9> ECLK<8> ECLK<7> ECLK<6> ECLK<5> ECLK<4> ECLK<3> ECLK<2> ECLK<1>
3D10< 8F9>
6F9>
TELECOM_AD<7.0>\I
RN35 RN35 RN35 RN35 RN36 RN36 RN36 RN36 RN37 RN37 RN37
28F3> 3D10< 3D10<8F9> 6E9> 3D10<8F9> 6E9>
LAC1\I TELECOM_AC1J1V1\I TELECOM_ADP\I TELECOM_APL\I
4.7K
AB10 AA10 AA11 AB11
LREFCLK LADATA<7> LADATA<6> LADATA<5> LADATA<4> LADATA<3> LADATA<2> LADATA<1> LADATA<0> LAC1 LAC1J1V1 LADP LAPL LAOE TPOS_TDAT TNEG_TMFP TICLK TCLK INTB D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> RSTB
29C4> 10G9> 13G9> 16G9>
RN50 RN50
RN50 RN50
RN51 RN51 RN38 RN38 RN39 RN39 RN39 RN39 RN40 RN40 RN40 RN40 RN41 RN41 RN41 RN41 RN42 RN42 RN42 RN42 RN43 RN43 RN43 RN43 RN44 RN44 RN44 RN44 RN45 RN45 RN45 RN45 RN46 RN46 RN46 RN46 RN47 RN47 RN47 RN47
TE1_INTB TE1_CSB TE_RDB TE_WRB TE1_ALE
28D3<> 8E9<> 6E9<>
SBI_APL\I SBI_AV5\I SBI_ADP\I TEMUX3_SBIACT
10E9> 13E9> 16E9> 10F9> 13F9> 16F9> 10F9> 13F9> 16F9> 9F3>
TEMUX_UP_CONTROL<10.0>\I
22C4<> 21D10<> 17F5<> 14F5<> 11F5<> 8D9<> 6D9<> 3B10<> 28C3<> 25G3<>
L_AD<31.0>\I
TEMUX PM8315
UNUSED INPUTS
28F3> 29B5<> 28B3<> 26C5> 22B8<> 21E6<> 17E6<> 14E5<> 11E5<> 3C10<> 8D9< 6C9<
CHIP_ADDRESS<19.0>\I RSTB\I
VSS2V5<8> VSS2V5<7> VSS2V5<6> VSS2V5<5> VSS2V5<4> VSS2V5<3> VSS2V5<2> VSS2V5<1>
VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1>
DRAWING: TEMUX_1.1 TMX1 15:05:25 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN TEMUX-1.1 ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:4
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
REVISIONS
0.01UF 0.01UF 0.01UF
ZONE
DESCRIPTION
DATE
APPR
AA14
PBGA
28E3>
VDD3V3<9>
VDD3V3<8>
VDD3V3<7>
VDD3V3<6>
VDD3V3<5>
VDD3V3<4>
VDD3V3<3>
VDD3V3<2>
VDD3V3<13>
VDD3V3<12>
VDD3V3<11>
3E10>
TELECOM_DD<7.0>\I
AB15 AB14 AA13 AB16 AA16 AB17 AB12 AB13 AA17 AB18 AA18 AB19
VDD3V3<10>
VDD3V3<1>
CLK52M\I
CLK52M LDDATA<7> LDDATA<6> LDDATA<5> LDDATA<4> LDDATA<3> LDDATA<2> LDDATA<1> LDDATA<0> LDC1J1 LDDP LDPL LDV5 LDAIS LDTPL RADEASTCLK RADEASTFP RADEAST RADWESTCLK RADWESTFP RADWEST RCLK RPOS/RDAT RNEG/RLCV XCLK TRSTB
CCSID SREFCLK SC1FP SAJUST_REQ SBIACT SBIDET0 ID<28> ID<27> ID<26> ID<25> ID<24> ID<23> ID<22> ID<21> ID<20> ID<19> ID<18> ID<17> ID<16> ID<15> ID<14> ID<13> ID<12> ID<11> ID<10> ID<9> ID<8> ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ICLK<28> ICLK<27> ICLK<26> ICLK<25> ICLK<24> ICLK<23> ICLK<22> ICLK<21> ICLK<20> ICLK<19> ICLK<18> ICLK<17> ICLK<16> ICLK<15> ICLK<14> ICLK<13> ICLK<12> ICLK<11> ICLK<10> ICLK<9> ICLK<8> ICLK<7> ICLK<6> ICLK<5> ICLK<4> ICLK<3> ICLK<2> ICLK<1>
AA20 AB21 AB20
RN57 RN57 RN58 RN58 RN58 RN58 RN59 RN59 RN59 RN59
RES_ARRAY_4
SREFCLK\I C1FP\I ADJUST\I TEMUX1_SBIACT TEMUX2_SBIACT SBI_DD<7.0>\I
28F3> 28F3> 7F3<> 9F3> 10F3< 13F4< 16F4< 6E2< 8E2< 7F3> 7F3> 9F3> 10F3<13F4<16F4<
3D10> 3D10> 3E10>
TELECOM_DC1J1V1\I TELECOM_DDP\I TELECOM_DPL\I RN51 RN51 RN52 RN52 RN52 RN52 RN53 RN53 RN53
RN53 RN56 RN56
RN63 RN63 RN63 RN63 RN64 RN64 RN64 RN64
RES_ARRAY_4
28G9> 3E10> 7E9< 3E10>
XCLK\I TDO1\I TDO2 JTAG<2.0>\I
TEMUX PM8315
16F4<13F4<10F3<9D9> 7D9> 16E4<13E4<10E4<9D9> 7D9>
SBI_DV5\I SBI_DPL\I
RN37 RN57
16E4<13E4<10E4<9D9> 7D9>
SBI_DDP\I
RN57
AA22
IFP<28> IFP<27> IFP<26> IFP<25> IFP<24> IFP<23> IFP<22> IFP<21> IFP<20> IFP<19> IFP<18> IFP<17> IFP<16> IFP<15> IFP<14> IFP<13> IFP<12> IFP<11> IFP<10> IFP<9> IFP<8> IFP<7> IFP<6> IFP<5> IFP<4> IFP<3> IFP<2> IFP<1> RECVCLK2 RECVCLK1
TEMUXSELB
29D9<
RECVCLK1\I
VSS3V3<18> VSS3V3<17> VSS3V3<16> VSS3V3<15> VSS3V3<14> VSS3V3<13> VSS3V3<12> VSS3V3<11> VSS3V3<10> VSS3V3<9> VSS3V3<8> VSS3V3<7> VSS3V3<6> VSS3V3<5> VSS3V3<4> VSS3V3<3> VSS3V3<2> VSS3V3<1>
AA19
VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21>
DRAWING: TEMUX_1.2 TMX1 15:05:29 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN TEMUX-1.2 ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:5
REVISIONS
0.01UF C110 0.01UF C106 0.01UF C104 0.01UF
ZONE
C100 0.01UF
DESCRIPTION
DATE
APPR
C109 0.01UF
C108 0.01UF
C107 0.01UF
C105 0.01UF
0.01UF
C102 0.01UF
C101 0.01UF
C103
RN56 RN56 RN69
AA12 AA15
PBGA
28F3>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDDQ<1>
VDD2V5<8>
VDD2V5<7>
VDD2V5<6>
VDD2V5<5>
VDD2V5<4>
VDD2V5<3>
VDD2V5<2>
VDD2V5<1>
LREFCLK\I TELECOM_AD<7.0>\I
CSSED CICLK CIFP CTCLK CECLK CEFP ED<28> ED<27> ED<26> ED<25> ED<24> ED<23> ED<22> ED<21> ED<20> ED<19> ED<18> ED<17> ED<16> ED<15> ED<14> ED<13> ED<12> ED<11> ED<10> ED<9> ED<8> ED<7> ED<6> ED<5> ED<4> ED<3> ED<2> ED<1> ECLK<28> ECLK<27> ECLK<26> ECLK<25> ECLK<24> ECLK<23> ECLK<22> ECLK<21> ECLK<20> ECLK<19> ECLK<18> ECLK<17> ECLK<16> ECLK<15> ECLK<14> ECLK<13> ECLK<12> ECLK<11> ECLK<10> ECLK<9> ECLK<8> ECLK<7> ECLK<6> ECLK<5> ECLK<4> ECLK<3> ECLK<2> ECLK<1>
AB22 AA21
3D10< 8F9>
4F9>
RN65 RN65 RN65 RN65 RN66 RN66 RN66 RN66 RN67 RN67
28F3> 3D10<8F9> 4F9> 3D10<8F9> 4F9>
LAC1\I TELECOM_ADP\I TELECOM_APL\I
4.7K
AB10 AA10 AA11 AB11
LREFCLK LADATA<7> LADATA<6> LADATA<5> LADATA<4> LADATA<3> LADATA<2> LADATA<1> LADATA<0> LAC1 LAC1J1V1 LADP LAPL LAOE TPOS_TDAT TNEG_TMFP TICLK TCLK INTB D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> RSTB
CICLK<1>\I CTCLK<0>\I CECLK<1>\I SBI_AD<7.0>\I RN78 RN81
29C4> 29C4> 29C4> 10G9> 13G9> 16G9>
RN81 RN81
RN81 RN82
TE2_INTB TE2_CSB TE_RDB TE_WRB TE2_ALE
RN69 RN69 RN69 RN70 RN70 RN70 RN70 RN71 RN71 RN71 RN71 RN72 RN72 RN72 RN72 RN73 RN73 RN73 RN73 RN74 RN74 RN74 RN74 RN75 RN75 RN75 RN75 RN76 RN76 RN76 RN76 RN77 RN77 RN77 RN77 RN78 RN78 RN78
SBI_APL\I SBI_AV5\I SBI_ADP\I TEMUX1_SBIACT
10E9> 13E9> 16E9> 10F9> 13F9> 16F9> 10F9> 13F9> 16F9> 5F3>
28D3<> 8E9<> 4E9<>
TEMUX_UP_CONTROL<10.0>\I
TEMUX PM8315
17F5<> 14F5<> 11F5<> 8D9<> 4D9<> 3B10<> 22C4<> 21D10<> 28C3<> 25G3<>
L_AD<31.0>\I
UNUSED INPUTS
28F3>
CHIP_ADDRESS<19.0>\I RSTB\I
29B5<> 28B3<> 26C5> 22B8<> 21E6<> 17E6<> 14E5<> 11E5<> 4D9<> 3C10<>
VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1>
VSS2V5<8> VSS2V5<7> VSS2V5<6> VSS2V5<5> VSS2V5<4> VSS2V5<3> VSS2V5<2> VSS2V5<1>
DRAWING: TEMUX_2.1 TMX2 15:05:32 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN TEMUX-2.1 ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:6
0.01UF C123 0.01UF C122 0.01UF C121 0.01UF C120 0.01UF C119 0.01UF C118 0.01UF C117 0.01UF C116 0.01UF C115 0.01UF
REVISIONS
C114 0.01UF C113 0.01UF C112 0.01UF
ZONE
C111
DESCRIPTION
DATE
APPR
AA14
PBGA
28E3>
VDD3V3<9>
VDD3V3<8>
VDD3V3<7>
VDD3V3<6>
VDD3V3<5>
VDD3V3<4>
VDD3V3<3>
VDD3V3<2>
VDD3V3<13>
VDD3V3<12>
VDD3V3<11>
CLK52M\I
VDD3V3<10>
VDD3V3<1>
3E10>
TELECOM_DD<7.0>\I
AB15 AB14 AA13 AB16 AA16 AB17 AB12 AB13 AA17 AB18 AA18 AB19
CLK52M LDDATA<7> LDDATA<6> LDDATA<5> LDDATA<4> LDDATA<3> LDDATA<2> LDDATA<1> LDDATA<0> LDC1J1 LDDP LDPL LDV5 LDAIS LDTPL RADEASTCLK RADEASTFP RADEAST RADWESTCLK RADWESTFP RADWEST RCLK RPOS/RDAT RNEG/RLCV XCLK TRSTB
CCSID SREFCLK SC1FP SAJUST_REQ SBIACT SBIDET0 ID<28> ID<27> ID<26> ID<25> ID<24> ID<23> ID<22> ID<21> ID<20> ID<19> ID<18> ID<17> ID<16> ID<15> ID<14> ID<13> ID<12> ID<11> ID<10> ID<9> ID<8> ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ICLK<28> ICLK<27> ICLK<26> ICLK<25> ICLK<24> ICLK<23> ICLK<22> ICLK<21> ICLK<20> ICLK<19> ICLK<18> ICLK<17> ICLK<16> ICLK<15> ICLK<14> ICLK<13> ICLK<12> ICLK<11> ICLK<10> ICLK<9> ICLK<8> ICLK<7> ICLK<6> ICLK<5> ICLK<4> ICLK<3> ICLK<2> ICLK<1>
AA20 AB21 AB20
RN88 RN88 RN88 RN90 RN90 RN90 RN90 RN93 RN93 RN93
RES_ARRAY_4
SREFCLK\I C1FP\I ADJUST\I TEMUX2_SBIACT TEMUX3_SBIACT SBI_DD<7.0>\I
28F3> 28F3> 5F3> 9F3> 10F3<13F4<16F4< 5F3< 9F3< 9F3> 5F3> 9F3> 10F3<13F4<16F4<
3D10> 3D10> 3E10>
TELECOM_DC1J1V1\I TELECOM_DDP\I TELECOM_DPL\I RN82 RN82 RN82 RN83 RN83 RN83 RN83 RN84 RN84
RN84 RN84 RN87
28G9> 5E9> 9E9< 3E10>
XCLK\I TDO2 TDO3 JTAG<2.0>\I
TEMUX PM8315
16F4<13F4<10F3<9D9> 5D9> 16E4<13E4<10E4<9D9> 5D9>
SBI_DV5\I SBI_DPL\I
RN67 RN67
16E4<13E4<10E4<9D9> 5D9>
SBI_DDP\I
RN88
AA22
IFP<28> IFP<27> IFP<26> IFP<25> IFP<24> IFP<23> IFP<22> IFP<21> IFP<20> IFP<19> IFP<18> IFP<17> IFP<16> IFP<15> IFP<14> IFP<13> IFP<12> IFP<11> IFP<10> IFP<9> IFP<8> IFP<7> IFP<6> IFP<5> IFP<4> IFP<3> IFP<2> IFP<1> RECVCLK2 RECVCLK1
TEMUXSELB
AA19
VSS3V3<18> VSS3V3<17> VSS3V3<16> VSS3V3<15> VSS3V3<14> VSS3V3<13> VSS3V3<12> VSS3V3<11> VSS3V3<10> VSS3V3<9> VSS3V3<8> VSS3V3<7> VSS3V3<6> VSS3V3<5> VSS3V3<4> VSS3V3<3> VSS3V3<2> VSS3V3<1>
VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21>
DRAWING: TEMUX_2.2 TMX2 15:05:34 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN TEMUX-2.2 ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:7
0.01UF C135 0.01UF C134 0.01UF C133 0.01UF C132 0.01UF C131 0.01UF
REVISIONS
ZONE DESCRIPTION DATE APPR
C127 0.01UF C126 0.01UF C125 0.01UF C124
C130 0.01UF
C129 0.01UF
C128
0.01UF
RN87 RN87 RN87
AA12 AA15
PBGA
28F3> 3D10< 6F9> 4F9>
VDDQ<4>
VDDQ<3>
VDDQ<2>
VDD2V5<8>
VDD2V5<7>
VDD2V5<6>
VDD2V5<5>
VDD2V5<4>
VDD2V5<3>
VDD2V5<2>
VDD2V5<1>
LREFCLK\I TELECOM_AD<7.0>\I
VDDQ<1>
CSSED CICLK CIFP CTCLK CECLK CEFP ED<28> ED<27> ED<26> ED<25> ED<24> ED<23> ED<22> ED<21> ED<20> ED<19> ED<18> ED<17> ED<16> ED<15> ED<14> ED<13> ED<12> ED<11> ED<10> ED<9> ED<8> ED<7> ED<6> ED<5> ED<4> ED<3> ED<2> ED<1> ECLK<28> ECLK<27> ECLK<26> ECLK<25> ECLK<24> ECLK<23> ECLK<22> ECLK<21> ECLK<20> ECLK<19> ECLK<18> ECLK<17> ECLK<16> ECLK<15> ECLK<14> ECLK<13> ECLK<12> ECLK<11> ECLK<10> ECLK<9> ECLK<8> ECLK<7> ECLK<6> ECLK<5> ECLK<4> ECLK<3> ECLK<2> ECLK<1>
AB22 AA21
RN93 RN96 RN96 RN96 RN96 RN97 RN97 RN97 RN97 RN98
28F3> 3D10<6E9> 4F9> 3D10<6E9> 4F9>
LAC1\I TELECOM_ADP\I TELECOM_APL\I
4.7K
AB10 AA10 AA11 AB11
LREFCLK LADATA<7> LADATA<6> LADATA<5> LADATA<4> LADATA<3> LADATA<2> LADATA<1> LADATA<0> LAC1 LAC1J1V1 LADP LAPL LAOE TPOS_TDAT TNEG_TMFP TICLK TCLK INTB D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> RSTB
CICLK<2>\I
29C4>
CTCLK<1>\I 29C4> CECLK<2>\I 29C4> SBI_AD<7.0>\I 10G9> 13G9> 16G9> RN122 RN122
RN130 RN130
RN130 RN130
TE3_INTB TE3_CSB TE_RDB TE_WRB TE3_ALE
28D3<> 6E9<> 4E9<>
RN113 RN113 RN113 RN113 RN114 RN114 RN114 RN114 RN115 RN115 RN115 RN115 RN116 RN116 RN116 RN116 RN117 RN117 RN117 RN117 RN118 RN118 RN118 RN118 RN119 RN119 RN119 RN119 RN120 RN120 RN120 RN120 RN121 RN121 RN121 RN121 RN122 RN122
SBI_APL\I SBI_AV5\I SBI_ADP\I TEMUX1_SBIACT
10E9> 13E9> 16E9> 10F9> 13F9> 16F9> 10F9> 13F9> 16F9> 5F3>
TEMUX_UP_CONTROL<10.0>\I
25G3<> 22C4<> 21D10<> 17F5<> 14F5<> 11F5<> 6D9<> 4D9<> 3B10<> 28C3<>
L_AD<31.0>\I
TEMUX PM8315
UNUSED INPUTS
28F3> 29B5<> 28B3<> 26C5> 22B8<> 21E6<> 17E6<> 14E5<> 11E5<> 4D9<> 3C10<>
CHIP_ADDRESS<19.0>\I RSTB\I
VSS2V5<8> VSS2V5<7> VSS2V5<6> VSS2V5<5> VSS2V5<4> VSS2V5<3> VSS2V5<2> VSS2V5<1>
VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1>
DRAWING: TEMUX_1.3 TMX3 15:05:37 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN TEMUX-3.1 ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:8
0.01UF C148 0.01UF C147 0.01UF C146 0.01UF C145 0.01UF C144 0.01UF C143 0.01UF C142 0.01UF C141 0.01UF C140 0.01UF
REVISIONS
C139 0.01UF C138 0.01UF C137 0.01UF
ZONE
C136
DESCRIPTION
DATE
APPR
AA14
PBGA
VDD3V3<9>
VDD3V3<8>
VDD3V3<7>
VDD3V3<6>
VDD3V3<5>
VDD3V3<4>
VDD3V3<3>
VDD3V3<2>
VDD3V3<13>
VDD3V3<12>
VDD3V3<11>
28E3> 3E10>
CLK52M\I
VDD3V3<10>
VDD3V3<1>
TELECOM_DD<7.0>\I
AB15 AB14 AA13 AB16 AA16 AB17 AB12 AB13 AA17 AB18 AA18 AB19
CLK52M LDDATA<7> LDDATA<6> LDDATA<5> LDDATA<4> LDDATA<3> LDDATA<2> LDDATA<1> LDDATA<0> LDC1J1 LDDP LDPL LDV5 LDAIS LDTPL RADEASTCLK RADEASTFP RADEAST RADWESTCLK RADWESTFP RADWEST RCLK RPOS/RDAT RNEG/RLCV XCLK TRSTB
CCSID SREFCLK SC1FP SAJUST_REQ SBIACT SBIDET0 ID<28> ID<27> ID<26> ID<25> ID<24> ID<23> ID<22> ID<21> ID<20> ID<19> ID<18> ID<17> ID<16> ID<15> ID<14> ID<13> ID<12> ID<11> ID<10> ID<9> ID<8> ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ICLK<28> ICLK<27> ICLK<26> ICLK<25> ICLK<24> ICLK<23> ICLK<22> ICLK<21> ICLK<20> ICLK<19> ICLK<18> ICLK<17> ICLK<16> ICLK<15> ICLK<14> ICLK<13> ICLK<12> ICLK<11> ICLK<10> ICLK<9> ICLK<8> ICLK<7> ICLK<6> ICLK<5> ICLK<4> ICLK<3> ICLK<2> ICLK<1>
SREFCLK\I C1FP\I RN134 RN134
RES_ARRAY_4
28F3> 28F3> 5F3> 7F3<> 10F3< 13F4< 16F4< 4E3< 7F3< 7F3> 5F3>7F3> 10F3<13F4<16F4<
3D10> 3D10> 3E10>
TELECOM_DC1J1V1\I TELECOM_DDP\I TELECOM_DPL\I RN131 RN131 RN131 RN131 RN132 RN132 RN132 RN132 RN133
RN133 RN133 RN133
28G9> 7E9> 11E5< 3E10>
XCLK\I TDO3 TDO4\I JTAG<2.0>\I
TEMUX PM8315
RN134 RN134 RN135 RN135 RN135 RN135 RN136 RN136 AA20 AB21 AB20
ADJUST\I TEMUX3_SBIACT TEMUX2_SBIACT SBI_DD<7.0>\I
16F4<13F4<10F3<7D9> 5D9> 16E4<13E4<10E4<7D9> 5D9>
SBI_DV5\I SBI_DPL\I
RN98 RN98
16E4<13E4<10E4<7D9> 5D9>
SBI_DDP\I
RN98
AA22
IFP<28> IFP<27> IFP<26> IFP<25> IFP<24> IFP<23> IFP<22> IFP<21> IFP<20> IFP<19> IFP<18> IFP<17> IFP<16> IFP<15> IFP<14> IFP<13> IFP<12> IFP<11> IFP<10> IFP<9> IFP<8> IFP<7> IFP<6> IFP<5> IFP<4> IFP<3> IFP<2> IFP<1> RECVCLK2 RECVCLK1
TEMUXSELB
AA19
VSS3V3<18> VSS3V3<17> VSS3V3<16> VSS3V3<15> VSS3V3<14> VSS3V3<13> VSS3V3<12> VSS3V3<11> VSS3V3<10> VSS3V3<9> VSS3V3<8> VSS3V3<7> VSS3V3<6> VSS3V3<5> VSS3V3<4> VSS3V3<3> VSS3V3<2> VSS3V3<1>
VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21>
DRAWING: TEMUX_3.2 TMX3 15:05:40 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN TEMUX-3.2 ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:9
REVISIONS
ZONE DESCRIPTION DATE APPR
12D2<>
AAL1_RAM2_D<15.0> AAL1GATOR-32 PM73122 TL_SYNC15 TL_SYNC14 TL_SYNC13 TL_SYNC12 TL_SYNC11 TL_SYNC10 TL_SYNC9 TL_SYNC8 TL_SYNC7 TL_SYNC6 TL_SYNC5 TL_SYNC4 TL_SYNC3 TL_SYNC2 TL_SYNC1 TL_SYNC0 TL_DATA15 TL_DATA14 TL_DATA13 TL_DATA12 TL_DATA11 TL_DATA10 TL_DATA9 TL_DATA8 TL_DATA7 TL_DATA6 TL_DATA5 TL_DATA4 TL_DATA3 TL_DATA2 TL_DATA1 TL_DATA0 TL_SIG15 TL_SIG14 TL_SIG13 TL_SIG12 TL_SIG11 TL_SIG10 TL_SIG9 TL_SIG8 TL_SIG7 TL_SIG6 TL_SIG5 TL_SIG4 TL_SIG3 TL_SIG2 TL_SIG1 TL_SIG0 TL_CLK15 TL_CLK14 TL_CLK13 TL_CLK12 TL_CLK11 TL_CLK10 TL_CLK9 TL_CLK8 TL_CLK7 TL_CLK6 TL_CLK5 TL_CLK4 TL_CLK3 TL_CLK2 TL_CLK1 TL_CLK0 CTL_CLK LINE_MODE1 LINE_MODE0 LINE INTERFACE
RN139
12D7<
AAL1_RAM2_A<17.0>
12B7< 12C7< 6F2< 4F3< 16G9> 13G9> 8F3<
AAL1_RAM2_OEB AAL1_RAM2_CSB RN141 RN141 SBI_AD<7.0>\I
12C7<
AAL1_RAM2_WE0B RN139 RN139
6E2<
8E2< 6E2< 4E3< 4E3< 16F9> 13F9> 8E2<
13F9> 16F9> 28E9<
SBI_ADP\I SBI_AV5\I AACTIVE<1>\I
12C7< 12B7<
AAL1_RAM2_WE1B AAL1_RAM2_R/WB RN139 RN140 RN140
8E2<
6E2<
4E3<
13E9> 16E9>
SBI_APL\I RN140
RN140
29C4> 28E3>
RL_CLK<5.0>\I FASTCLK\I
RN141
AE15 AD16 AD15 AE16 AF15 AC10
RL_SYNC15 RL_SYNC14 RL_SYNC13 RL_SYNC12 RL_SYNC11 RL_SYNC10 RL_SYNC9 RL_SYNC8 RL_SYNC7 RL_SYNC6 RL_SYNC5 RL_SYNC4 RL_SYNC3 RL_SYNC2 RL_SYNC1 RL_SYNC0 RL_DATA15 RL_DATA14 RL_DATA13 RL_DATA12 RL_DATA11 RL_DATA10 RL_DATA9 RL_DATA8 RL_DATA7 RL_DATA6 RL_DATA5 RL_DATA4 RL_DATA3 RL_DATA2 RL_DATA1 RL_DATA0 RL_SIG15 RL_SIG14 RL_SIG13 RL_SIG12 RL_SIG11 RL_SIG10 RL_SIG9 RL_SIG8 RL_SIG7 RL_SIG6 RL_SIG5 RL_SIG4 RL_SIG3 RL_SIG2 RL_SIG1 RL_SIG0 RL_CLK15 RL_CLK14 RL_CLK13 RL_CLK12 RL_CLK11 RL_CLK10 RL_CLK9 RL_CLK8 RL_CLK7 RL_CLK6 RL_CLK5 RL_CLK4 RL_CLK3 RL_CLK2 RL_CLK1 RL_CLK0 CRL_CLK
AC15 AC11 AF16 AC14 AD10
RN143 RN144
RN141 RN142 RN142 RN142 RN142 RN143 RN143 RN143
SBI_DD<7.0>\I
5F3> 7F3> 9F3>
SBI_DV5\I ADJUST\I C1FP\I
5D9> 7D9> 9D9> 5F3> 7F3<> 9F3> 28F3>
AAL1_RAM2_PAR<1.0>
12D2<>
SBI_DDP\I SBI_DPL\I ADETECT<1>\I TL_CLK<95.0>\I
5D9> 7D9> 9D9> 5D9> 7D9> 9D9> 28E9> 29D4>
SREFCLK\I
28F3>
19G9>
ANYPHY_TDAT<15.0>\I
19E9> 19F9>
ANYPHY_TSX\I ANYPHY_TADR<3.0>\I
19E9> 19E9> 19E9< 16B9> 13B8>
ANYPHY_TPAR\I ANYPHY_TENB\I ANYPHY_TPA\I
AB24 AA23 AC26 AB25 AB26 AA25 AA24
RATM_D15 RATM_D14 RATM_D13 RATM_D12 RATM_D11 RATM_D10 RATM_D9 RATM_D8 RATM_D7 RATM_D6 RATM_D5 RATM_D4 RATM_D3 RATM_D2 RATM_D1 RATM_D0 TPHY_ADD4 TPHY_ADD3 TPHY_ADD2 TPHY_ADD1 TPHY_ADD0 RATM_PAR RATM_ENB RATM_CLAV
AAL1GATOR-32 PM73122
TATM_D15 TATM_D14 TATM_D13 TATM_D12 TATM_D11 TATM_D10 TATM_D9 TATM_D8 TATM_D7 TATM_D6 TATM_D5 TATM_D4 TATM_D3 TATM_D2 TATM_D1 TATM_D0 RPHY_ADD_RSX RPHY_ADD3 RPHY_ADD2 RPHY_ADD1 RPHY_ADD0 RATM_CLK RATM_SOC TATM_PAR TATM_ENB TATM_CLAV TATM_CLK TATM_SOC
RDAT<15.0>\I
13C3> 16C3> 27D7> 22G3<
4.7K
4.7K
RADR<4.0>\I
22F3>
TPHY_CLK\I RSOC\I RPRTY\I RDENB\I RCA\I RPHY_CLK\I
24D4> 27C7> 13B3> 16B3> 27C7> 22F3< 13B3> 16B3> 27B7> 22F3< 24D4>
UTOPIA INTERFACE
DRAWING: AAL1GATOR_32_1.1 AAL1 15:05:43 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN AAL1GATOR-32_1 LINE-UTOPIA INTER. ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:10
REVISIONS
ZONE DESCRIPTION DATE APPR
28F3>
CHIP_ADDRESS<19.0>\I
29D9< 14E9> 17E9> 29D9< 14E9> 17E9>
29C9< 29C9< 29B9>
29C4> 29C4>
AC25 AD26 AB23 AD23 AC21 AF23 AE22 AD21 AC19 AE20 AD19 AF20 AE18 AD17 AF18 AC16 AE13 AD13 AF12 AE12 CGC_DOUT<11.0>\I AF10 CGC_LINES<14.0>\I SRTS_STRB<0>\I ADAP_STRB<0>\I NCLK<0>\I RN145 4.7K CGC_SER_D<0>\I CGC_VALID<0>\I
AAL1GATOR-32 PM73122 CGC_DOUT3 CGC_DOUT2 CGC_DOUT1 CGC_DOUT0 CGC_LINE4 ACKB CGC_LINE3 INTB CGC_LINE2 TRSTB CGC_LINE1 RSTB CGC_LINE0 SYSCLK SCAN_MODEB SRTS_STBH TCLK ADAP_STBH NCLK TL_CLK_OE CGC_SER_D CGC_VALID MICRO/JTAG
25G3<> 28C3<> 14F5<> 17F5<> 3B10<> 4D9<> 6D9<> 8D9<> 21D10<> 22C4<>
AE25 AD24 AC23 AC18 AC13 AF17 AA26
AAL1GATOR-32 PM73122 VDD23 VSS27 VSS26 VDD22 VSS25 VDD21 VSS24 VDD20 VSS23 VDD19 VSS22 VDD18 VSS21 VDD17 VSS20 VDD16 VSS19 VDD15 VSS18 VDD14 VSS17 VDD13 VSS16 VDD12 VSS15 VDD11 VSS14 VDD10 VSS13 VDD9 VSS12 VDD8 VSS11 VDD7 VSS10 VDD6 VSS9 VDD5 VSS8 VDD4 VSS7 VDD3 VSS6 VDD2 VSS5 VDD1 VSS4 VDD0 VSS3 PCH_9 VSS2 PCH_8 VSS1 PCH_7 VSS0 PCH_6 PCH_5 PCH_4 PCH_3 PCH_2 PCH_1 POWER SUPPLY
AF26 AF25 AF14 AF13 AE26 AE24 AD25
AC22 AF24 AE23 AD22 AC20 AF22 AE21 AD20 AE19 AD18 AC17 AF19 AE17 AF21 AD14 AE14 AD12 AF11 AC12 AE11 AD11 AE10 AC24
L_AD<31.0>\I
RN145 RN145 RN145
4.7K 4.7K 4.7K
28E3<> 17E6<> 14E5<>
AAL1_ALE AAL_WRB AAL_RDB AAL1_CSB AAL1_ACKB AAL1_INTB
AAL_UP_CONTROL<13.0>\I
RSTB\I
8D9< 22B8<> 26C5> 3C10<> 4D9<> 14E5<> 17E6<> 21E6<> 28B3<> 29B5<> 6C9< 3E10> 9E9>
JTAG<2.0>\I TDO4\I TDO5
50PPM 3.3V 38.880MHZ HCMOS
ACT125
AAL_SYSCLK\I
14E5<17E6<29B9<
0.01UF
0.1UF
C149
C150
NC/TS
ACT125
RAM1_CLK
12E7<15E8< 18E7<
ACT125
RAM2_CLK
12B7<15B8<18B7<
0.01UF
C167 0.01UF
C166 0.01UF
C165 0.01UF
C164 0.01UF
C163 0.01UF
C162 0.01UF
C161 0.01UF
C160 0.01UF
C159 0.01UF
C158 0.01UF
C157 0.01UF
0.01UF
0.01UF
0.01UF
C153 0.01UF
C152 0.01UF
C156
C155
C154
DECOUPLING CAPS POWER PINS
C151
DRAWING: AAL1GATOR_32_1.2 AAL1 15:05:45 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN AAL1GATOR-32_1 POWER ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:11
0.01UF C173 0.01UF C172 0.01UF 0.01UF C170 0.01UF C169 0.01UF
REVISIONS
C171 C168
ZONE
DESCRIPTION
DATE
APPR
AAL1_RAM1_D<15.0>
80MHZ AAL1_RAM1_A<17.0>
VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1>
VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
AAL1GATOR-32 PM73122
17A18 16C17 15B18 14A19 13D17 12C18 11B19 10A20
RAM1_A17 RAM1_A16 RAM1_A15 RAM1_A14 RAM1_A13 RAM1_A12 RAM1_A11 RAM1_A10 RAM1_A9 RAM1_A8 RAM1_A7 RAM1_A6 RAM1_A5 RAM1_A4 RAM1_A3 RAM1_A2 RAM1_A1 RAM1_A0
11D5>
RAM1_CLK
INTERFACE RN146
VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
RAM1_D15 RAM1_D14 RAM1_D13 RAM1_D12 RAM1_D11 RAM1_D10 RAM1_D9 RAM1_D8 RAM1_D7 RAM1_D6 RAM1_D5 RAM1_D4 RAM1_D3 RAM1_D2 RAM1_D1 RAM1_D0 RAM1_OEB RAM1_WEB1 RAM1_WEB0 RAM1_CSB RAM1_ADSCB RAM1_PAR1 RAM1_PAR0 SCAN_ENB
A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0>
NOTE: RAMS USED THIS DESIGN. NON-ZBT RAMS USED LOWER PERFORMANCE APPLICATIONS. REFER DOCUMENT PMC-1990887.
CY71352 (256K
AAL1_RAM1_WE1B AAL1_RAM1_WE0B RN146 AAL1_RAM1_OEB AAL1_RAM1_CSB AAL1_RAM1_R/WB
4.7K
RN146
4.7K
BWS1 BWS0 ADV/LD MODE
4.7K
AAL1_RAM1_PAR<1.0>
80MHZ
10H9>
VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1>
AAL1_RAM2_A<17.0>
VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0>
AAL1_RAM2_PAR<1.0> AAL1_RAM2_D<15.0>
10F3<> 10H9<>
CY71352 (256K
10F9> 10F9> 10G9> 10G9> 10F9> 11D5>
AAL1_RAM2_WE1B AAL1_RAM2_WE0B AAL1_RAM2_CSB RN147 AAL1_RAM2_OEB AAL1_RAM2_R/WB RAM2_CLK RN147
4.7K
4.7K
VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
BWS1 BWS0 ADV/LD MODE
DRAWING: AAL1GATOR_32_1.3 AAL1 15:05:48 2001
PMC-Sierra, Inc.
0.01UF C179 0.01UF C178 0.01UF 0.01UF C176 0.01UF C175 0.01UF C177 C174
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN AAL1GATOR-32_1 SRAM INTERFACE ENGINEER:
ISSUE DATE: 2001 REVISION NUMBER: PAGE:12
REVISIONS
ZONE DESCRIPTION DATE APPR
15D2<>
AAL2_RAM2_D<15.0> AAL1GATOR-32 PM73122 TL_SYNC15 TL_SYNC14 TL_SYNC13 TL_SYNC12 TL_SYNC11 TL_SYNC10 TL_SYNC9 TL_SYNC8 TL_SYNC7 TL_SYNC6 TL_SYNC5 TL_SYNC4 TL_SYNC3 TL_SYNC2 TL_SYNC1 TL_SYNC0 TL_DATA15 TL_DATA14 TL_DATA13 TL_DATA12 TL_DATA11 TL_DATA10 TL_DATA9 TL_DATA8 TL_DATA7 TL_DATA6 TL_DATA5 TL_DATA4 TL_DATA3 TL_DATA2 TL_DATA1 TL_DATA0 TL_SIG15 TL_SIG14 TL_SIG13 TL_SIG12 TL_SIG11 TL_SIG10 TL_SIG9 TL_SIG8 TL_SIG7 TL_SIG6 TL_SIG5 TL_SIG4 TL_SIG3 TL_SIG2 TL_SIG1 TL_SIG0 TL_CLK15 TL_CLK14 TL_CLK13 TL_CLK12 TL_CLK11 TL_CLK10 TL_CLK9 TL_CLK8 TL_CLK7 TL_CLK6 TL_CLK5 TL_CLK4 TL_CLK3 TL_CLK2 TL_CLK1 TL_CLK0 CTL_CLK LINE_MODE1 LINE_MODE0 LINE INTERFACE
RN144
15D8<
AAL2_RAM2_A<17.0>
15B8< 15B8< 6F2< 4F3< 16G9> 10G9> 8F3<
AAL2_RAM2_OEB AAL2_RAM2_CSB RN150 RN150 SBI_AD<7.0>\I
15C8<
AAL2_RAM2_WE0B RN144 RN144
8E2< 6E2< 4E3< 6E2< 4E3< 16F9> 10F9> 8E2<
10F9> 16F9> 28E9<
SBI_ADP\I SBI_AV5\I AACTIVE<2>\I
15C8< 15B8<
AAL2_RAM2_WE1B AAL2_RAM2_R/WB RN149 RN149 RN149
8E2<
6E2< 4E3<
10E9> 16E9>
SBI_APL\I RN149
RN150
29C4> 28E3>
RL_CLK<5.0>\I FASTCLK\I
RN150
AE15 AD16 AD15 AE16 AF15 AC10
RL_SYNC15 RL_SYNC14 RL_SYNC13 RL_SYNC12 RL_SYNC11 RL_SYNC10 RL_SYNC9 RL_SYNC8 RL_SYNC7 RL_SYNC6 RL_SYNC5 RL_SYNC4 RL_SYNC3 RL_SYNC2 RL_SYNC1 RL_SYNC0 RL_DATA15 RL_DATA14 RL_DATA13 RL_DATA12 RL_DATA11 RL_DATA10 RL_DATA9 RL_DATA8 RL_DATA7 RL_DATA6 RL_DATA5 RL_DATA4 RL_DATA3 RL_DATA2 RL_DATA1 RL_DATA0 RL_SIG15 RL_SIG14 RL_SIG13 RL_SIG12 RL_SIG11 RL_SIG10 RL_SIG9 RL_SIG8 RL_SIG7 RL_SIG6 RL_SIG5 RL_SIG4 RL_SIG3 RL_SIG2 RL_SIG1 RL_SIG0 RL_CLK15 RL_CLK14 RL_CLK13 RL_CLK12 RL_CLK11 RL_CLK10 RL_CLK9 RL_CLK8 RL_CLK7 RL_CLK6 RL_CLK5 RL_CLK4 RL_CLK3 RL_CLK2 RL_CLK1 RL_CLK0 CRL_CLK
AC15 AC11 AF16 AC14 AD10
RN153 RN153
RN151 RN151 RN151 RN151 RN152 RN152 RN152 RN152
SBI_DD<7.0>\I
5F3> 7F3> 9F3>
SBI_DV5\I ADJUST\I C1FP\I
5D9> 7D9> 9D9> 5F3> 7F3<> 9F3> 28F3>
AAL2_RAM2_PAR<1.0>
15D2<>
SBI_DDP\I SBI_DPL\I ADETECT<2>\I TL_CLK<95.0>\I
5D9> 7D9> 9D9> 5D9> 7D9> 9D9> 28E9> 29D4>
SREFCLK\I
28F3>
19G9>
ANYPHY_TDAT<15.0>\I
19E9> 19F9>
ANYPHY_TSX\I ANYPHY_TADR<3.0>\I
19E9> 19E9> 19E9< 16B9> 10B8>
ANYPHY_TPAR\I ANYPHY_TENB\I ANYPHY_TPA\I
AB24 AA23 AC26 AB25 AB26 AA25 AA24
RATM_D15 RATM_D14 RATM_D13 RATM_D12 RATM_D11 RATM_D10 RATM_D9 RATM_D8 RATM_D7 RATM_D6 RATM_D5 RATM_D4 RATM_D3 RATM_D2 RATM_D1 RATM_D0 TPHY_ADD4 TPHY_ADD3 TPHY_ADD2 TPHY_ADD1 TPHY_ADD0 RATM_PAR RATM_ENB RATM_CLAV
AAL1GATOR-32 PM73122
TATM_D15 TATM_D14 TATM_D13 TATM_D12 TATM_D11 TATM_D10 TATM_D9 TATM_D8 TATM_D7 TATM_D6 TATM_D5 TATM_D4 TATM_D3 TATM_D2 TATM_D1 TATM_D0 RPHY_ADD_RSX RPHY_ADD3 RPHY_ADD2 RPHY_ADD1 RPHY_ADD0 RATM_CLK RATM_SOC TATM_PAR TATM_ENB TATM_CLAV TATM_CLK TATM_SOC
RDAT<15.0>\I
10D3> 16C3> 27D7> 22G3<
RADR<4.0>\I
22F3>
TPHY_CLK\I RSOC\I RPRTY\I RDENB\I RCA\I RPHY_CLK\I
24D4> 27C7> 10B3> 16B3> 27C7> 22F3< 10B3> 16B3> 27B7> 22F3< 24D4>
UTOPIA INTERFACE DRAWING: AAL1GATOR_32_2.1 AAL2 15:05:50 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN AAL1GATOR-32_2 LINE-UTOPIA INTER. ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:13
REVISIONS
ZONE DESCRIPTION DATE APPR
28F3>
AAL1GATOR-32 PM73122
AC22 AF24 AE23 AD22 AC20 AF22 AE21 AD20 AE19 AD18 AC17 AF19 AE17 AF21 AD14 AE14 AD12 AF11 AC12 AE11 AD11 AE10 AC24 AE25 AD24 AC23 AC18 AC13 AF17 AA26
AAL1GATOR-32 PM73122 VDD23 VSS27 VSS26 VDD22 VSS25 VDD21 VSS24 VDD20 VSS23 VDD19 VSS22 VDD18 VSS21 VDD17 VSS20 VDD16 VSS19 VDD15 VSS18 VDD14 VSS17 VDD13 VSS16 VDD12 VSS15 VDD11 VSS14 VDD10 VSS13 VDD9 VSS12 VDD8 VSS11 VDD7 VSS10 VDD6 VSS9 VDD5 VSS8 VDD4 VSS7 VDD3 VSS6 VDD2 VSS5 VDD1 VSS4 VDD0 VSS3 PCH_9 VSS2 PCH_8 VSS1 PCH_7 VSS0 PCH_6 PCH_5 PCH_4 PCH_3 PCH_2 PCH_1 POWER SUPPLY
AF26 AF25 AF14 AF13 AE26 AE24 AD25
CHIP_ADDRESS<19.0>\I
17E9> 11F9> 29D9< 17E9> 11E9> 29D9<
29C9< 29C9< 29B9> 29C4> 29C4>
AC25 AD26 AB23 AD23 AC21 AF23 AE22 AD21 AC19 AE20 AD19 AF20 AE18 AD17 AF18 AC16 AE13 AD13 AF12 AE12 CGC_DOUT<11.0>\I AF10 CGC_LINES<14.0>\I SRTS_STRB<1>\I ADAP_STRB<1>\I NCLK<1>\I RN148 CGC_SER_D<1>\I 4.7K CGC_VALID<1>\I
CGC_DOUT3 CGC_DOUT2 CGC_DOUT1 CGC_DOUT0 CGC_LINE4 CGC_LINE3 CGC_LINE2 CGC_LINE1 CGC_LINE0 SRTS_STBH ADAP_STBH NCLK TL_CLK_OE CGC_SER_D CGC_VALID
ACKB INTB TRSTB RSTB SYSCLK SCAN_MODEB TCLK MICRO/JTAG
L_AD<31.0>\I
22C4<> 25G3<> 21D10<> 3B10<> 4D9<> 6D9<> 8D9<> 11F5<> 17F5<> 28C3<>
RN154 RN154 RN154
4.7K 4.7K 4.7K
28E3<> 11F5<> 17E6<>
AAL2_ALE AAL_WRB AAL_RDB AAL2_CSB AAL2_ACKB AAL2_INTB
AAL_UP_CONTROL<13.0>\I
RSTB\I AAL_SYSCLK\I
3C10<> 4D9<> 11E5<> 17E6<> 21E6<> 22B8<> 26C5> 8D9< 11D5> 28B3<> 29B5<> 6C9< 3E10>
JTAG<2.0>\I TDO6 TDO7
0.01UF
0.01UF
C195 0.01UF
C194 0.01UF
C193 0.01UF
C192 0.01UF
C191 0.01UF
C190 0.01UF
C189 0.01UF
C188 0.01UF
C187 0.01UF
C186 0.01UF
0.01UF
0.01UF
0.01UF
C182 0.01UF
C181 0.01UF
C196
C185
C184
C183
DECOUPLING CAPS POWER PINS
C180
DRAWING: AAL1GATOR_32_2.2 AAL2 15:05:52 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN AAL1GATOR-32_2 POWER ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:14
REVISIONS
ZONE
0.01UF C198 0.01UF C200 0.01UF 0.01UF C204 0.01UF C206 0.01UF C202 C207
DESCRIPTION
DATE
APPR
AAL2_RAM1_D<15.0> 80MHZ AAL2_RAM1_A<17.0>
VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1>
VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
AAL1GATOR-32 PM73122
RAM1_A17 RAM1_A16 RAM1_A15 RAM1_A14 RAM1_A13 RAM1_A12 RAM1_A11 RAM1_A10 RAM1_A9 RAM1_A8 RAM1_A7 RAM1_A6 RAM1_A5 RAM1_A4 RAM1_A3 RAM1_A2 RAM1_A1 RAM1_A0
INTERFACE
11D5>
RAM1_CLK
VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
RAM1_D15 RAM1_D14 RAM1_D13 RAM1_D12 RAM1_D11 RAM1_D10 RAM1_D9 RAM1_D8 RAM1_D7 RAM1_D6 RAM1_D5 RAM1_D4 RAM1_D3 RAM1_D2 RAM1_D1 RAM1_D0 RAM1_OEB RAM1_WEB1 RAM1_WEB0 RAM1_CSB RAM1_ADSCB RAM1_PAR1 RAM1_PAR0 SCAN_ENB
A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0>
CY71352 (256K
AAL2_RAM1_WE1B AAL2_RAM1_WE0B RN155 AAL2_RAM1_OEB AAL2_RAM1_CSB AAL2_RAM1_R/WB
4.7K
RN155
4.7K
BWS1 BWS0 ADV/LD MODE
RN154
4.7K
AAL1_RAM1_PAR<1.0>
80MHZ
13H9>
VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1>
AAL2_RAM2_A<17.0>
VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0>
AAL2_RAM2_PAR<1.0> AAL2_RAM2_D<15.0>
13F4<> 13H9<>
CY71352 (256K
13F9> 13F9> 13G9> 13G9> 13F9> 11D5>
AAL2_RAM2_WE1B AAL2_RAM2_WE0B AAL2_RAM2_CSB RN156 AAL2_RAM2_OEB AAL2_RAM2_R/WB RAM2_CLK RN156
4.7K
VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
4.7K
BWS1 BWS0 ADV/LD MODE
DRAWING: AAL1GATOR_32_2.3 AAL2 15:05:55 2001
PMC-Sierra, Inc.
C199 0.01UF 0.01UF C203 0.01UF C205 0.01UF C201 C208
0.01UF
C197 0.01UF
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN AAL1GATOR-32_2 SRAM INTERFACE ENGINEER:
ISSUE DATE: 2001 REVISION NUMBER: PAGE:15
REVISIONS
ZONE DESCRIPTION DATE APPR
18D2<>
AAL3_RAM2_D<15.0> AAL1GATOR-32 PM73122 TL_SYNC15 TL_SYNC14 TL_SYNC13 TL_SYNC12 TL_SYNC11 TL_SYNC10 TL_SYNC9 TL_SYNC8 TL_SYNC7 TL_SYNC6 TL_SYNC5 TL_SYNC4 TL_SYNC3 TL_SYNC2 TL_SYNC1 TL_SYNC0 TL_DATA15 TL_DATA14 TL_DATA13 TL_DATA12 TL_DATA11 TL_DATA10 TL_DATA9 TL_DATA8 TL_DATA7 TL_DATA6 TL_DATA5 TL_DATA4 TL_DATA3 TL_DATA2 TL_DATA1 TL_DATA0 TL_SIG15 TL_SIG14 TL_SIG13 TL_SIG12 TL_SIG11 TL_SIG10 TL_SIG9 TL_SIG8 TL_SIG7 TL_SIG6 TL_SIG5 TL_SIG4 TL_SIG3 TL_SIG2 TL_SIG1 TL_SIG0 TL_CLK15 TL_CLK14 TL_CLK13 TL_CLK12 TL_CLK11 TL_CLK10 TL_CLK9 TL_CLK8 TL_CLK7 TL_CLK6 TL_CLK5 TL_CLK4 TL_CLK3 TL_CLK2 TL_CLK1 TL_CLK0 CTL_CLK LINE_MODE1 LINE_MODE0 LINE INTERFACE
RN153
18D7<
AAL3_RAM2_A<17.0>
18B7< 18C7< 6F2< 4F3< 13G9> 10G9> 8F3<
AAL3_RAM2_OEB AAL3_RAM2_CSB RN159 RN160 SBI_AD<7.0>\I
18C7<
AAL3_RAM2_WE0B RN153 RN158
6E2<
8E2< 6E2< 4E3< 4E3< 13F9> 10F9> 8E2<
10F9> 13F9> 28E9<
SBI_ADP\I SBI_AV5\I AACTIVE<3>\I
18C7< 18B7<
AAL3_RAM2_WE1B AAL3_RAM2_R/WB RN158 RN158 RN158
8E2<
6E2<
4E3<
10E9> 13E9>
SBI_APL\I RN159
RN159
29C4> 28E3>
RL_CLK<5.0>\I FASTCLK\I
RN159
AE15 AD16 AD15 AE16 AF15 AC10
RL_SYNC15 RL_SYNC14 RL_SYNC13 RL_SYNC12 RL_SYNC11 RL_SYNC10 RL_SYNC9 RL_SYNC8 RL_SYNC7 RL_SYNC6 RL_SYNC5 RL_SYNC4 RL_SYNC3 RL_SYNC2 RL_SYNC1 RL_SYNC0 RL_DATA15 RL_DATA14 RL_DATA13 RL_DATA12 RL_DATA11 RL_DATA10 RL_DATA9 RL_DATA8 RL_DATA7 RL_DATA6 RL_DATA5 RL_DATA4 RL_DATA3 RL_DATA2 RL_DATA1 RL_DATA0 RL_SIG15 RL_SIG14 RL_SIG13 RL_SIG12 RL_SIG11 RL_SIG10 RL_SIG9 RL_SIG8 RL_SIG7 RL_SIG6 RL_SIG5 RL_SIG4 RL_SIG3 RL_SIG2 RL_SIG1 RL_SIG0 RL_CLK15 RL_CLK14 RL_CLK13 RL_CLK12 RL_CLK11 RL_CLK10 RL_CLK9 RL_CLK8 RL_CLK7 RL_CLK6 RL_CLK5 RL_CLK4 RL_CLK3 RL_CLK2 RL_CLK1 RL_CLK0 CRL_CLK
AC15 AC11 AF16 AC14 AD10
RN162 RN162
RN160 RN160 RN161 RN161 RN161 RN161 RN162 RN162
SBI_DD<7.0>\I
5F3> 7F3> 9F3>
SBI_DV5\I ADJUST\I C1FP\I
5D9> 7D9> 9D9> 5F3> 7F3<> 9F3> 28F3>
AAL3_RAM2_PAR<1.0>
18D2<>
SBI_DDP\I SBI_DPL\I ADETECT<3>\I TL_CLK<95.0>\I
5D9> 7D9> 9D9> 5D9> 7D9> 9D9> 28E9> 29D4>
SREFCLK\I
28F3>
19G9>
ANYPHY_TDAT<15.0>\I
19E9> 19F9>
ANYPHY_TSX\I ANYPHY_TADR<3.0>\I
19E9> 19E9> 19E9< 13B8> 10B8>
ANYPHY_TPAR\I ANYPHY_TENB\I ANYPHY_TPA\I
AB24 AA23 AC26 AB25 AB26 AA25 AA24
RATM_D15 RATM_D14 RATM_D13 RATM_D12 RATM_D11 RATM_D10 RATM_D9 RATM_D8 RATM_D7 RATM_D6 RATM_D5 RATM_D4 RATM_D3 RATM_D2 RATM_D1 RATM_D0 TPHY_ADD4 TPHY_ADD3 TPHY_ADD2 TPHY_ADD1 TPHY_ADD0 RATM_PAR RATM_ENB RATM_CLAV
AAL1GATOR-32 PM73122
TATM_D15 TATM_D14 TATM_D13 TATM_D12 TATM_D11 TATM_D10 TATM_D9 TATM_D8 TATM_D7 TATM_D6 TATM_D5 TATM_D4 TATM_D3 TATM_D2 TATM_D1 TATM_D0 RPHY_ADD_RSX RPHY_ADD3 RPHY_ADD2 RPHY_ADD1 RPHY_ADD0 RATM_CLK RATM_SOC TATM_PAR TATM_ENB TATM_CLAV TATM_CLK TATM_SOC
RDAT<15.0>\I
10D3> 13C3> 27D7> 22G3<
RADR<4.0>\I
22F3>
TPHY_CLK\I RSOC\I RPRTY\I RDENB\I RCA\I RPHY_CLK\I
24D4> 27C7> 10B3> 13B3> 27C7> 22F3< 10B3> 13B3> 27B7> 22F3< 24D4>
UTOPIA INTERFACE DRAWING: AAL1GATOR_32_3.1 AAL3 15:05:57 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN AAL1GATOR-32_3 LINE-UTOPIA INTER. ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:16
REVISIONS
ZONE DESCRIPTION DATE APPR
AC25 AD26 AB23 AD23 AC21 AF23 AE22 AD21 AC19 AE20 AD19 AF20 AE18 AD17 AF18 AC16 AE13 AD13 AF12 AE12 CHIP_ADDRESS<19.0>\I CGC_DOUT<11.0>\I AF10 CGC_LINES<14.0>\I SRTS_STRB<2>\I ADAP_STRB<2>\I NCLK<2>\I RN157 4.7K CGC_SER_D<2>\I CGC_VALID<2>\I
AAL1GATOR-32 PM73122 ACKB INTB TRSTB RSTB SYSCLK SCAN_MODEB TCLK MICRO/JTAG
AC22 AF24 AE23 AD22 AC20 AF22 AE21 AD20 AE19 AD18 AC17 AF19 AE17 AF21 AD14 AE14 AD12 AF11 AC12 AE11 AD11 AE10 AC24 AE25 AD24 AC23 AC18 AC13 AF17 AA26
AAL1GATOR-32 PM73122 VDD23 VSS27 VSS26 VDD22 VSS25 VDD21 VSS24 VDD20 VSS23 VDD19 VSS22 VDD18 VSS21 VDD17 VDD16 VSS20 VDD15 VSS19 VDD14 VSS18 VDD13 VSS17 VDD12 VSS16 VDD11 VSS15 VDD10 VSS14 VSS13 VDD9 VSS12 VDD8 VSS11 VDD7 VSS10 VDD6 VSS9 VDD5 VSS8 VDD4 VSS7 VDD3 VSS6 VDD2 VSS5 VDD1 VSS4 VDD0 VSS3 PCH_9 VSS2 PCH_8 VSS1 PCH_7 VSS0 PCH_6 PCH_5 PCH_4 PCH_3 PCH_2 PCH_1 POWER SUPPLY
AF26 AF25 AF14 AF13 AE26 AE24 AD25
28F3> 14E9> 11F9> 29D9< 14E9> 11E9> 29D9<
29C9< 29C9< 29B9> 29C4> 29C4>
CGC_DOUT3 CGC_DOUT2 CGC_DOUT1 CGC_DOUT0 CGC_LINE4 CGC_LINE3 CGC_LINE2 CGC_LINE1 CGC_LINE0 SRTS_STBH ADAP_STBH NCLK TL_CLK_OE CGC_SER_D CGC_VALID
L_AD<31.0>\I
25G3<> 28C3<> 11F5<> 14F5<> 3B10<> 4D9<> 6D9<> 8D9<> 22C4<> 21D10<>
RN157 RN163 RN163
4.7K 4.7K 4.7K
AAL3_ALE AAL_WRB AAL_RDB AAL3_CSB AAL3_ACKB AAL3_INTB
AAL_UP_CONTROL<13.0>\I
14E5<> 28E3<> 11F5<>
29B5<> 6C9< 21E6<> 22B8<> 3C10<> 4D9<> 14E5<> 11D5> 11E5<> 26C5> 28B3<> 8D9< 3E10>
RSTB\I AAL_SYSCLK\I
JTAG<2.0>\I TDO8 TDO9
0.01UF
C226 0.01UF
C225 0.01UF
C224 0.01UF
C223 0.01UF
C222 0.01UF
C221 0.01UF
C220 0.01UF
C219 0.01UF
C218 0.01UF
C217 0.01UF
C216 0.01UF
0.01UF
0.01UF
0.01UF
C212 0.01UF
C211 0.01UF
C215
C214
C213
DECOUPLING CAPS POWER PINS DRAWING: AAL1GATOR_32_3.2 AAL3 15:05:59 2001
C210
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN AAL1GATOR-32_3 POWER ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:17
REVISIONS
ZONE
0.01UF C232 0.01UF C231 0.01UF 0.01UF C229 0.01UF C228 0.01UF
DESCRIPTION
DATE
APPR
C230
AAL3_RAM1_D<15.0>
C227
80MHZ AAL3_RAM1_A<17.0>
VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1>
VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
AAL1GATOR-32 PM73122
17A18 16C17 15B18 14A19 13D17 12C18 11B19 10A20
RAM1_A17 RAM1_A16 RAM1_A15 RAM1_A14 RAM1_A13 RAM1_A12 RAM1_A11 RAM1_A10 RAM1_A9 RAM1_A8 RAM1_A7 RAM1_A6 RAM1_A5 RAM1_A4 RAM1_A3 RAM1_A2 RAM1_A1 RAM1_A0
4.7K
11D5>
RAM1_CLK
INTERFACE
4.7K
VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
RAM1_D15 RAM1_D14 RAM1_D13 RAM1_D12 RAM1_D11 RAM1_D10 RAM1_D9 RAM1_D8 RAM1_D7 RAM1_D6 RAM1_D5 RAM1_D4 RAM1_D3 RAM1_D2 RAM1_D1 RAM1_D0 RAM1_OEB RAM1_WEB1 RAM1_WEB0 RAM1_CSB RAM1_ADSCB RAM1_PAR1 RAM1_PAR0 SCAN_ENB
A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0>
CY71352 (256K
AAL3_RAM1_WE1B AAL3_RAM1_WE0B RN163 AAL3_RAM1_OEB AAL3_RAM1_CSB AAL3_RAM1_R/WB
4.7K
RN163
BWS1 BWS0 ADV/LD MODE
AAL3_RAM1_PAR<1.0>
80MHZ
16H9>
VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1>
AAL3_RAM2_A<17.0>
VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
16F9> 16G9> 16G9> 16G9> 16F9> 11D5>
A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0>
AAL3_RAM2_PAR<1.0> AAL3_RAM2_D<15.0>
16F4<> 16H9<>
CY71352 (256K
AAL3_RAM2_WE1B AAL3_RAM2_WE0B AAL3_RAM2_CSB RN164 AAL3_RAM2_OEB AAL3_RAM2_R/WB RAM2_CLK RN165
4.7K
VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
4.7K
BWS1 BWS0 ADV/LD MODE
DRAWING: AAL1GATOR_32_3.3 AAL3 15:06:01 2001
PMC-Sierra, Inc.
0.01UF C238 0.01UF C237 0.01UF 0.01UF C235 0.01UF C234 0.01UF C236 C233
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN AAL1GATOR-32_3 SRAM INTERFACE ENGINEER:
ISSUE DATE: 2001 REVISION NUMBER: PAGE:18
REVISIONS
ZONE DESCRIPTION DATE APPR
16C9<13C8< 10D8<
WRDAT<15> WRDAT<14> WRDAT<13> WRDAT<12> WRDAT<11> WRDAT<10> WRDAT<9> WRDAT<8> WRDAT<7> WRDAT<6> WRDAT<5> WRDAT<4> WRDAT<3> WRDAT<2> WRDAT<1> WRDAT<0> WRADR<2> WRADR<1> WRADR<0> WRENB WRPA WRPRTY WRSOP WRSX
AA25 AA24 AB25 AC26 AA23 AB24 AC25 AD26 AC24 AF24 AE23 AD22 AC21 AF23 AE22 AF20 AD19 AE20 AC20 AD21 AF21 AC19 AE21 4.7K AD20
WRDAT<15.0>\I
22G9>
ANYPHY_TDAT<15.0>\I
ANY-PHY/SCI-PHY
4.7K
RN136 RN136 RN167 RN167 RN167 RN167 RN168 RN168 RN168 RN168 RN169 RN169 RN169 RN169 RN170 RN170
AA26
16C9<13C8<10C8<
ANYPHY_TADR<3.0>\I
RN170 RN170 RN171 RN171
LTADR<11> LTADR<10> LTADR<9> LTADR<8> LTADR<7> LTADR<6> LTADR<5> LTADR<4> LTADR<3> LTADR<2> LTADR<1> LTADR<0> LTENB LTPA LTPRTY LTSOP LTSX LTCLK
LOOP ANY-PHY
RN172 RN172 RN172
4.7K 4.7K 4.7K WRENB\I WRPA\I
LTDAT<15> LTDAT<14> LTDAT<13> LTDAT<12> LTDAT<11> LTDAT<10> LTDAT<9> LTDAT<8> LTDAT<7> LTDAT<6> LTDAT<5> LTDAT<4> LTDAT<3> LTDAT<2> LTDAT<1> LTDAT<0>
22F9< 22F9> 22F9> 22F9>
WRPRTY\I WRSOP\I
16B9< 13B8< 10B8< 16B9>13B8>10B8> 16B9<13B8<10B8<
ANYPHY_TENB\I ANYPHY_TPA\I ANYPHY_TPAR\I
16C9< 13C8< 10C8< 24E4> 22E3>
ANYPHY_TSX\I LTCLK\I TDAT<15.0>\I
LOOP ANY-PHY/SCI-PHY
22D3>
TADR<4.0>\I
-LRDAT<15> LRDAT<14> LRDAT<13> LRDAT<12> LRDAT<11> LRDAT<10> LRDAT<9> LRDAT<8> LRDAT<7> LRDAT<6> LRDAT<5> LRDAT<4> LRDAT<3> LRDAT<2> LRDAT<1> LRDAT<0>
LRADR<5> LRADR<4> LRADR<3> LRADR<2> LRADR<1> LRADR<0> LRENB LRPRTY LRPA LRSOP LRSX LRCLK
ANY-PHY/SCI-PHY
WRCLK -WTDAT<15> WTDAT<14> WTDAT<13> WTDAT<12> WTDAT<11> WTDAT<10> WTDAT<9> WTDAT<8> WTDAT<7> WTDAT<6> WTDAT<5> WTDAT<4> WTDAT<3> WTDAT<2> WTDAT<1> WTDAT<0> WTADR<2> WTADR<1> WTADR<0> WTENB WTPA WTPRTY WTSOP WTSX WTCLK
WRCLK\I
24E4>
RN17 RN17 RN173 RN173 RN173 RN173 RN174 RN174 RN174 RN174 RN175 RN175 RN175 RN175 RN176 RN176
WTDAT<15.0>\I
22F9<
RN176 RN176 RN177 RN177 RN177
WTADR<2.0>\I
22E9<
WTENB\I WTPA\I WTPRTY\I WTSOP\I
22D9< 22D9> 22E9< 22D9<
RN172
4.7K
22D3> 22D3> 22D3<27E7> 22D3>
TWRENB\I TPRTY\I TCA\I TSOC\I
PM7326 S/UNI-APEX ANY-PHY/SCI-PHY
24D4>
LRCLK\I
4.7K
PM7326 S/UNI-APEX LOOP ANY-PHY SCI-PHY
DRAWING: APEX_1.1 15:06:06 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN APEX-1.1 ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:19
REVISIONS
ZONE
ISD<33.0> CBDQ<31.0>
0.01UF C294 0.01UF C296 0.01UF C298 0.01UF C308 0.01UF C310 0.01UF C312
DESCRIPTION
DATE
APPR
3E10> 21E6>
JTAG<2.0>\I
TDO11
VDD5 VDD4 VDD3 VDD2 VDD1 VDDQ10 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1
4.7K
4.7K
4.7K
4.7K
TSOP
RN86
RN86
RN86
RN86
SBGA CMD<33> CMD<32> CMD<31> CMD<30> CMD<29> CMD<28> CMD<27> CMD<26> CMD<25> CMD<24> CMD<23> CMD<22> CMD<21> CMD<20> CMD<19> CMD<18> CMD<17> CMD<16> CMD<15> CMD<14> CMD<13> CMD<12> CMD<11> CMD<10> CMD<9> CMD<8> CMD<7> CMD<6> CMD<5> CMD<4> CMD<3> CMD<2> CMD<1> CMD<0> CMP<1> CMP<0> CMA<19> CMA<18> CMA<17> CMA<16> CMA<15> CMA<14> CMA<13> CMA<12> CMA<11> CMA<10> CMA<9> CMA<8> CMA<7> CMA<6> CMA<5> CMA<4> CMA<3> CMA<2> CMA<1> CMA<0> CMAB*<18> CMAB*<17> CMRWB CMCEB
RN62
MT48LC4M16A2
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 VSSQ1 VSSQ2 VSSQ3 VSSQ4
CAS* RAS* DQML
DQMH
AD13 AF12 AE12 AD12 AF11 AC12 AE11 AD11 AE10 AC11 AD10 AC10 AE19 AD18 AC17 AF19 AE18 AD17 AF18 AC16 AE17 AD16 AE16 AC15 AE14 AE13
CBDQ<31> CBDQ<30> CBDQ<29> CBDQ<28> CBDQ<27> CBDQ<26> CBDQ<25> CBDQ<24> CBDQ<23> CBDQ<22> CBDQ<21> CBDQ<20> CBDQ<19> CBDQ<18> CBDQ<17> CBDQ<16> CBDQ<15> CBDQ<14> CBDQ<13> CBDQ<12> CBDQ<11> CBDQ<10> CBDQ<9> CBDQ<8> CBDQ<7> CBDQ<6> CBDQ<5> CBDQ<4> CBDQ<3> CBDQ<2> CBDQ<1> CBDQ<0> CBA<11> CBA<10> CBA<9> CBA<8> CBA<7> CBA<6> CBA<5> CBA<4> CBA<3> CBA<2> CBA<1> CBA<0> CBDQM<1> CBDQM<0> CBBS<1> CBBS<0> CBCSB CBWEB
CE1* CE3* CKE* LBO*
VDDQ1 VDDQ2 VDDQ3 VDDQ4
VDD1 VDD2 VDD3
PBGA
DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 NC30 NC29 NC28 NC27 NC26 NC25 NC24 NC23 NC22 NC21 NC20 NC19 NC18 NC17 NC16 NC15 NC14 NC13 NC12 NC11 NC10
4.7K R342
GS882Z18
SSRAM (512
R338
4.7K
VSS1 VSS2 VSS3
VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1
ZBT_CLK TDO12\I CMA<19.0>
3E10> 23E4<
21C5>
CBA<11.0>
VDD5 VDD4 VDD3 VDD2 VDD1 VDDQ10 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1
RN60 RN54 RN54 RN54 RN54 RN55 RN55 RN55 RN55 RN60 RN60 RN60
JTAG<2.0>\I
RN62 RN61 RN61 RN61
AF16 AD15 AE15 AD14 AC14 AF15
4.7K
4.7K
4.7K
4.7K
RN68 RN68 RN91 RN92 RN68 RN85 RN92 RN85 RN91 RN85 RN91 RN91 RN68 RN92 RN85 RN92
ZBT_CLK_INV MOTOROLA
RN89
RN89
RN89
RN89
TSOP
RN61 RN62 RN62
CBCASB CBRASB
VDDQ1 VDDQ2 VDDQ3 VDDQ4
VDD1 VDD2 VDD3
MT48LC4M16A2
VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1
4.7K
R289
VSSQ1 VSSQ2 VSSQ3 VSSQ4
CAS* RAS* DQML VSS1 VSS2 VSS3 DQMH
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
PM7326 S/UNI-APEX SRAM INTERFACE
CE1* CE3* CKE* LBO*
PBGA
DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 NC30 NC29 NC28 NC27 NC26 NC25 NC24 NC23 NC22 NC21 NC20 NC19 NC18 NC17 NC16 NC15 NC14 NC13 NC12 NC11 NC10
4.7K R340
GS882Z18
SSRAM (512
R341
R339
4.7K
OPTIONAL CONNECTIONS SUPPORTING DIFFERENT TYPE RAMS
4.7K R288
JP10
0.01UF
C295 0.01UF
C297 0.01UF
C307 0.01UF
C309 0.01UF
C311 0.01UF
C313
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:20
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
C282
C284
C286
C288
C290
C292
C283
C285
C287
C289
C291
C293
21C5>
SDRAM_CLK
0.01UF
DECOUPLING GS882Z18 POWER PINS DRAWING: TITLE=APEX_BLOCK ABBREV=APEX_BLOCK LAST_MODIFIED=Thu 15:06:12 2001
DECOUPLING MT48LC POWER PINS
TITLE: AAL1GATOR-32 DESIGN APEX-1.2 ENGINEER:
REVISIONS
ZONE DESCRIPTION DATE APPR
RN178 RN178 RN178 RN178
AD23 AC22 4.7K
0.01UF
C252 0.01UF
C261 0.01UF
C260 0.01UF
C259 0.01UF
C258 0.01UF
C257 0.01UF
C256 0.01UF
C255 0.01UF
C254 0.01UF
4.7K 4.7K 4.7K 4.7K
AE25 AD24 AC23 AC18 AC13 AB26 AF22 AF17 AF10
APEX_CSB APEX_WR APEX_ADSB APEX_BURSTB APEX_BLAST APEX_READYB APEX_INTHIB APEX_INTLOB APEX_WRDONEB APEX_BUSPOL APEX_BTERMB
APEX_UP_CONTROL<10.0>\I
22C4<> 17F5<> 14F5<> 6D9<> 4D9<> 3B10<> 11F5<> 8D9<> 28C3<> 25G3<>
L_AD<31.0>\I
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0>
ADSB BURSTB BLAST READYB INTHIB INTLOB WRDONEB BUSPOL BTERMB BCLK SYSCLK RSTB SCANEN SCANMB TRSTB
BCLK\I
VDD23 VDD22 VDD21 VDD20 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VDD0 PCH16 PCH15 PCH14 PCH13 PCH12 PCH11 PCH10 PCH9 PCH8 PCH7 PCH6 PCH5 PCH4 PCH3 PCH2 PCH1
C253 10UF
C262
VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0
AF26 AF25 AF14 AF13 AE26 AE24 AD25
24D4>
0.01UF C242 0.01UF C250 0.01UF C249 0.01UF C248 0.01UF C247 0.01UF C246 0.01UF C245 0.01UF C244 0.01UF C251 0.01UF C243 10UF C241
RSTB\I TDO11 TDO10\I JTAG<2.0>\I
4.7K
26C5> 28B3<> 29B5<> 3C10<> 4D9<> 11E5<> 14E5<> 17E6<> 22B8<> 6C9< 8D9< 20H4<
3E10>
PM7326 S/SUNI-APEX JTAG/MICRO
PM7326 S/UNI-APEX POWER BLOCK
10PF C263
50PPM 3.3V 80.000MHZ HCMOS
ACT125
0.01UF
0.1UF
C239
C240
NC/TS
ACT125
ZBT_CLK
20E1<
ACT125
SDRAM_CLK
20A10<
DRAWING: APEX_1.3 15:06:15 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN APEX-1.3 ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:21
REVISIONS
ZONE DESCRIPTION DATE APPR
19G3<
RDAT<15> RDAT<14> RDAT<13> RDAT<12> RDAT<11> RDAT<10> RDAT<9> RDAT<8> RDAT<7> RDAT<6> RDAT<5> RDAT<4> RDAT<3> RDAT<2> RDAT<1> RDAT<0>
4.7K 4.7K R100
WRDAT<15.0>\I
INGRESS OUTPUT SLAVE
INGRESS INPUT
MASTER
RN171 RN171 RN179 RN179 RN179 RN179 RN180 RN180 RN180 RN180 RN181 RN181 RN181 RN181 RN182 RN182
AG31 AF29 AF30 AF31 AE29 AD28 AE30 AE31 AD29 AC28 AD30 AD31 AC29 AC30 AC31 AB29 AB31 AB30 AA28
ODAT<15> ODAT<14> ODAT<13> ODAT<12> ODAT<11> ODAT<10> ODAT<9> ODAT<8> ODAT<7> ODAT<6> ODAT<5> ODAT<4> ODAT<3> ODAT<2> ODAT<1> ODAT<0> ORDENB OSOC OPRTY
RDAT<15.0>\I
10D3> 13C3> 16C3> 27D7>
19F3> 19F3< 19F3< 19F3<
WRENB\I WRPA\I WRSOP\I
RN182 RN182
WRPRTY\I RN183
RADDR<4>/RCA<3> RADDR<3>/RCA<2> RADDR<2>/RRDENB<4> RADDR<1>/RRDENB<3> RADDR<0>/RRDENB<2> RPRTY
AA29
RN185 RN185 RN185 RN185 RN186
RADR<4.0>\I
10C3< 13C3< 16C3< 27C7<
RPRTY\I RN186 RRDENB\I RCA\I RSOC\I
10B3> 13B3> 16B3> 27C7> 27C7< 10B3> 13B3> 16B3> 27B7> 27C7>
AA30 R101
OTSEN
OFCLK
RRDENB<1> RCA<1>
-19E2>
RFCLK
RSOC RAVALID/RCA<4>
WTDAT<15.0>\I
EGRESS OUTPUT
IDAT<15> IDAT<14> IDAT<13> IDAT<12> IDAT<11> IDAT<10> IDAT<9> IDAT<8> IDAT<7> IDAT<6> IDAT<5> IDAT<4> IDAT<3> IDAT<2> IDAT<1> IDAT<0>
IFCLK
RPOLL
EGRESS INPUT
TFCLK
TPOLL TDAT<15> TDAT<14> TDAT<13> TDAT<12> TDAT<11> TDAT<10> TDAT<9> TDAT<8> TDAT<7> TDAT<6> TDAT<5> TDAT<4> TDAT<3> TDAT<2> TDAT<1> TDAT<0>
19D2>
WTADR<2.0>\I
19D3> 19D3> 19D3< 19D3>
WTPRTY\I WTENB\I WTPA\I WTSOP\I
4.7K
IPRTY IWRENB<1> ICA<1> ISOC IAVALID/ICA<4> IPOLL PM7324 S/UNI-ATLAS SLAVE UTOPIA
MASTER
IADDR<4>/ICA<3> IADDR<3>/ICA<2> IADDR<2>/IWRENB<4> IADDR<1>/IWRENB<3> IADDR<0>/IWRENB<2>
RN186 RN186 RN187 RN187 RN187 RN187 RN188 RN188 RN188 RN188 RN189 RN189 RN189 RN189 RN190 RN190 RN190 RN190 RN191 RN191 RN191 RN191 RN192 RN192 RN192
TDAT<15.0>\I
19E9< 27G7<
SLAVE
RN183
4.7K R103
AA31
TADDR<4>/TCA<3> TADDR<3>/TCA<2> TADDR<2>/TWRENB<4> TADDR<1>/TWRENB<3> TADDR<0>/TWRENB<2> TPRTY TWRENB<1> TAVALID/TCA<4> TCA<1> TSOC PM7324 S/UNI-ATLAS MASTER UTOPIA
TADR<4.0>\I
19D9< 27F7<
TPRTY\I TWRENB\I TCA\I TSOC\I
19C9< 27F7< 19D9< 27F7< 19C9> 27E7> 19C9< 27F7<
24E4>
OFCLK\I
24E4>
RFCLK\I
AK22
28F3> 28F3<> 26C5> 17E6<> 11E5<> 3C10<> 4D9<> 14E5<> 21E6<> 28B3<> 29B5<> 6C9< 8D9<
CHIP_ADDRESS<19.0>\I ATLAS_UP_CONTROL<5.0>\I
A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> RSTB HALFSECCLK
RSTB\I
D<15> D<14> D<13> D<12> D<11> D<10> D<9> D<8> D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> INTB IDREQ EDREQ BUSYB
L_AD<31.0>\I
3B10<> 4D9<> 6D9<> 8D9<> 11F5<> 14F5<> 17F5<> 25G3<> 28C3<> 21D10<>
RN184 RN184
4.7K
4.7K
DRAWING: ATLAS_1.1 ATLAS1 15:06:18 2001
PM7324 S/UNI-ATLAS MICRO INTERFACE
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: ISSUE DATE: 2001
TITLE: AAL1GATOR-32 DESIGN REVISION NUMBER: ATLAS INGRESS EGRESS INTERFACE ENGINEER: PAGE:22
SRAM DECOUPLING CAPS POWER PINS
C327
REVISIONS
ZONE DESCRIPTION DATE APPR
0.01UF
C303 0.01UF
C304 0.01UF
C305 0.01UF
C306 0.01UF
C314 0.01UF
C315 0.01UF
C316 0.01UF
C317 0.01UF
C318 0.01UF
C319 0.01UF
C320 0.01UF
C321 0.01UF
C322 0.01UF
C323 0.01UF
C324 0.01UF
C325 0.01UF
C326 0.01UF
ISD<63> ISD<62> ISD<61> ISD<60> ISD<59> ISD<58> ISD<57> ISD<56> ISD<55> ISD<54> ISD<53> ISD<52> ISD<51> ISD<50> ISD<49> ISD<48> ISD<47> ISD<46> ISD<45> ISD<44> ISD<43> ISD<42> ISD<41> ISD<40> ISD<39> ISD<38> ISD<37> ISD<36> ISD<35> ISD<34> ISD<33> ISD<32> ISD<31> ISD<30> ISD<29> ISD<28> ISD<27> ISD<26> ISD<25> ISD<24> ISD<23> ISD<22> ISD<21> ISD<20> ISD<19> ISD<18> ISD<17> ISD<16> ISD<15> ISD<14> ISD<13> ISD<12> ISD<11> ISD<10> ISD<9> ISD<8> ISD<7> ISD<6> ISD<5> ISD<4> ISD<3> ISD<2> ISD<1> ISD<0> ISA<19> ISA<18> ISA<17> ISA<16> ISA<15> ISA<14> ISA<13> ISA<12> ISA<11> ISA<10> ISA<9> ISA<8> ISA<7> ISA<6> ISA<5> ISA<4> ISA<3> ISA<2> ISA<1> ISA<0> ISP<7> ISP<6> ISP<5> ISP<4> ISP<3> ISP<2> ISP<1> ISP<0> ISADSB ISRWB ISOEB
AJ10 AH11 AK10 AL10 AJ11 AH12 AK11 AL11 AJ12 AH13 AK12 AL12 AJ13 AK13 AL13 AJ14 AK14 AH15 AJ15 AL16 AK16 AJ16 AH16 AL17 AK17 AJ17 AK18 AH17 AJ18 AL19 AK19 AJ19 AL20 AK20 AH19 AJ20 AL21 AK21 AH20 AJ21 AL22 AJ23 AL24 AK24 AH23 AJ24 AL25 AK25 AH24 AJ25 AL26 AK26 AJ26 AL27 AK27 AH26 AJ27 AH31 AG29 AF28 AG30 AK23 AJ22 AL23
ISD<63.0>
ISA<19.0>
VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
GS841Z36T (256K
4.7K
4.7K
20E3>
TDO12\I
VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
3E10<
TDO13\I
ESP<3> ESP<2> ESP<1> ESP<0>
ESP<3.0>
VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
DQA<9> DQA<8> DQA<7> DQA<6> DQA<5> DQA<4> DQA<3> DQA<2> DQA<1> DQB<9> DQB<8> DQB<7> DQB<6> DQB<5> DQB<4> DQB<3> DQB<2> DQB<1> DQC<9> DQC<8> DQC<7> DQC<6> DQC<5> DQC<4> DQC<3> DQC<2> DQC<1> DQD<9> DQD<8> DQD<7> DQD<6> DQD<5> DQD<4> DQD<3> DQD<2> DQD<1>
ESD<31.0>
ESD<31> ESD<30> ESD<29> ESD<28> ESD<27> ESD<26> ESD<25> ESD<24> ESD<23> ESD<22> ESD<21> ESD<20> ESD<19> ESD<18> ESD<17> ESD<16> ESD<15> ESD<14> ESD<13> ESD<12> ESD<11> ESD<10> ESD<9> ESD<8> ESD<7> ESD<6> ESD<5> ESD<4> ESD<3> ESD<2> ESD<1> ESD<0>
A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
GS841Z36T (256K
4.7K
4.7K
DQA<9> DQA<8> DQA<7> DQA<6> DQA<5> DQA<4> DQA<3> DQA<2> DQA<1> DQB<9> DQB<8> DQB<7> DQB<6> DQB<5> DQB<4> DQB<3> DQB<2> DQB<1> DQC<9> DQC<8> DQC<7> DQC<6> DQC<5> DQC<4> DQC<3> DQC<2> DQC<1> DQD<9> DQD<8> DQD<7> DQD<6> DQD<5> DQD<4> DQD<3> DQD<2> DQD<1>
VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1>
ESA<19.0>
RN183 RN183 RN193 RN193 RN193 RN193 RN194 RN194 RN194 RN194 RN195 RN195 RN195 RN195 RN196 RN196 RN196
ESA<19> ESA<18> ESA<17> ESA<16> ESA<15> ESA<14> ESA<13> ESA<12> ESA<11> ESA<10> ESA<9> ESA<8> ESA<7> ESA<6> ESA<5> ESA<4> ESA<3> ESA<2> ESA<1> ESA<0>
RN196 RN197 RN197 RN197 RN197 RN198 RN198 RN198 RN198 RN199 RN199 RN199 RN199 RN200 RN200 RN200 RN200
A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
GS841Z36T (256K
4.7K
ESOEB ESRWB ESADSB
ESOEB ESRWB ESADSB
ISADSB ISRWB ISOEB
4.7K
ISP<7.0>
ESYSCLK
ISYSCLK TRSTB
AH21 0.1UF C278
POWER BLOCK PM7324
VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
PM7324 S/UNI-ATLAS SRAM INTERFACE
DQA<9> DQA<8> DQA<7> DQA<6> DQA<5> DQA<4> DQA<3> DQA<2> DQA<1> DQB<9> DQB<8> DQB<7> DQB<6> DQB<5> DQB<4> DQB<3> DQB<2> DQB<1> DQC<9> DQC<8> DQC<7> DQC<6> DQC<5> DQC<4> DQC<3> DQC<2> DQC<1> DQD<9> DQD<8> DQD<7> DQD<6> DQD<5> DQD<4> DQD<3> DQD<2> DQD<1>
JTAG<2.0>\I
3E10>
DRAWING: ATLAS_1.2 ATLAS 15:06:24 2001
VDD<40-1> VBIAS GND<48-1>
50PPM 3.3V 50.000MHZ HCMOS
ACT125
ESYSCLK
C209 0.01UF
0.1UF
C264
ACT125
NC/TS
ISYSCLK
PMC-Sierra, Inc.
C267 0.01UF C268 0.01UF C269 0.01UF C270 0.01UF C271 0.01UF C272 0.01UF C273 0.01UF C274 0.01UF C275 0.01UF C276 0.01UF C277 0.01UF C279 0.01UF C280 0.01UF C281 0.01UF C299 0.01UF C300 0.01UF C301 0.01UF
0.01UF C265 0.01UF C266 0.01UF C302
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN ATLAS-SSRAM INTERFACE ENGINEER:
ISSUE DATE: 2001 REVISION NUMBER: PAGE:23
SUNI-ATLAS DECOUPLING CAPS POWER PINS
REVISIONS
ZONE DESCRIPTION DATE APPR
RECEPTACLE_RA
AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 PRTY LENB CLAV0 CLAV1 CLAV2 CLAV3 CLKIO EXTREF TRG_IN TRG_OUT
EBBI80
22E3>
TDAT<15.0>\I
22D3> 22D3> 22D3> 22D3>
TPRTY\I TSOC\I TWRENB\I TADR<4.0>\I
22D3< 19C9>
TCA\I
UTOPIA2 INTERFACE
RECEPTACLE_RA
AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 PRTY LENB CLAV0 CLAV1 CLAV2 CLAV3 CLKIO EXTREF TRG_IN TRG_OUT
EBBI80
22G3< 16C3> 13C3> 10D3>
RDAT<15.0>\I
22F3< 16B3> 13B3> 10B3> 22F3< 16B3< 13B3< 10B3< 22F3> 22F3>
RPRTY\I RSOC\I RRDENB\I RADR<4.0>\I
22F3< 16B3> 13B3> 10B3>
RCA\I
DRAWING: ATLAS_1.6 ATLAS 15:05:15 2001
UTOPIA2 INTERFACE
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESGIN UTOPIA CONNECTOR ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:24
REVISIONS
ZONE DESCRIPTION DATE APPR
50PPM 3.3V 25.000MHZ HCMOS
0.1UF C399
R111
PI49FCT3807
NC/TS
RN15 RN15 RN15 RN15 RN16 RN16 RN16 RN16 RN17 RN17
WRCLK\I RFCLK\I OFCLK\I LTCLK\I LRCLK\I RPHY_CLK\I TPHY_CLK\I LCLK\I LCLK_CPLD\I BCLK\I
19E3< 22C7< 22D7< 19E9< 19C9< 10B3< 13B3< 16B3< 10B3< 13B3< 16B3< 25E2< 28B3< 29B5< 21E6<
0.01UF 0.01UF 0.01UF 0.01UF C403 C402 C401 C400
DECOUPLING CAPS
DRAWING: OSCIALLTOE_25M OSCILLATOR_25M 15:05:08 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN 25MHZ OSCILLATOR BLOCK ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:25
REVISIONS
ZONE DESCRIPTION DATE APPR
C419 0.01UF C418 0.01UF C417 0.01UF C416 0.01UF C415 0.01UF C414 0.01UF C413
C421 0.01UF
C420 0.01UF
0.1UF
7E9< 5E9< 9E9<
XCLK\I 50PPM 3.3V 51.840MHZ HCMOS
0.01UF 0.1UF C422 C423
NC/TS 50PPM 3.3V 19.440MHZ HCMOS
XC95288XL-PQ208 CPLD
XC95288XL-PQ208 CPLD GND_1 VCCINT_1 GND_2 VCCINT_2 GND_3 VCCINT_3 GND_4 VCCINT_4 GND_5 VCCINT_5 GND_6 GND_7 VCCIO_1 GND_8 VCCIO_2 GND_9 VCCIO_3 VCCIO_4 GND_10 GND_11 VCCIO_5 GND_12 VCCIO_6 GND_13 VCCIO_7 GND_14 VCCIO_8 GND_15 VCCIO_9 GND_16 VCCIO_10 GND_17 VCCIO_11 GND_18 VCCIO_12 GND_19 POWER
0.01UF 0.1UF C424 C425
NC/TS 32PPM 3.3V 37.056MHZ HCMOS
RES_ARRAY_4
RES_ARRAY_4
IO16<11> IO16<10> IO16<9> IO16<8> IO16<7> IO16<6> IO16<5> IO16<4> IO16<3> IO16<2> IO16<1> IO14<11> IO14<10> IO14<9> IO14<8> IO14<7> IO14<6> IO14<5> IO14<4> IO14<3> IO14<2> IO14<1> IO12<11> IO12<10> IO12<9> IO12<8> IO12<7> IO12<6> IO12<5> IO12<4> IO12<3> IO12<2> IO12<1> IO10<11> IO10<10> IO10<9> IO10<8> IO10<7> IO10<6> IO10<5> IO10<4> IO10<3> IO10<2> IO10<1> IO8<10> IO8<9> IO8<8> IO8<7> IO8<6> IO8<5> IO8<4> IO8<3> IO8<2> IO8<1> IO6<9> IO6<8> IO6<7> IO6<6> IO6<5> IO6<4> IO6<3> IO6<2> IO6<1> IO4<6> IO4<5> IO4<4> IO4<3> IO4<2> IO4<1> IO2<10> IO2<9> IO2<8> IO2<7> IO2<6> IO2<5> IO2<4> IO2<3> IO2<2> IO2<1> IO/GTS<4> IO/GTS<3> IO/GTS<2> IO/GTS<1>
IO15<11> IO15<10> IO15<9> IO15<8> IO15<7> IO15<6> IO15<5> IO15<4> IO15<3> IO15<2> IO15<1> IO13<11> IO13<10> IO13<9> IO13<8> IO13<7> IO13<6> IO13<5> IO13<4> IO13<3> IO13<2> IO13<1> IO11<11> IO11<10> IO11<9> IO11<8> IO11<7> IO11<6> IO11<5> IO11<4> IO11<3> IO11<2> IO11<1> IO9<11> IO9<10> IO9<9> IO9<8> IO9<7> IO9<6> IO9<5> IO9<4> IO9<3> IO9<2> IO9<1> IO7<10> IO7<9> IO7<8> IO7<7> IO7<6> IO7<5> IO7<4> IO7<3> IO7<2> IO7<1> IO5<9> IO5<8> IO5<7> IO5<6> IO5<5> IO5<4> IO5<3> IO5<2> IO5<1> IO3<8> IO3<7> IO3<6> IO3<5> IO3<4> IO3<3> IO3<2> IO3<1> IO1<10> IO1<9> IO1<8> IO1<7> IO1<6> IO1<5> IO1<4> IO1<3> IO1<2> IO1<1> IO/GCK<3> IO/GCK<2> IO/GCK<1> IO/GSR IOBLOCK
RN11 RN11 RN11 RN11 RN12 RN12 RN12 RN12
RES_ARRAY_4
CHIP_ADDRESS<19.0>\I LREFCLK\I C1FP\I LAC1\I SS1_DFP\I ATLAS_UP_CONTROL<5.0>\I
3B10< 4D9< 6D9< 8D9< 11G9< 14F9< 17E9< 22B8< 4F9< 6F9< 8F9< 5F3< 7F3< 9F3< 10F3<13F4<16F4< 4F9< 6F9< 8F9< 3E10< 22B8<>
16E4<13E4<10E4<
C426 0.01UF 0.1UF C427
NC/TS
ATLAS_INTB ATLAS_BUSYB ATLAS_RDB ATLAS_WRB ATLAS_CSB ATLAS_ALE
ADETECT<3.1>\I AACTIVE<3.1>\I
16F9> 13F9> 10F9>
SREFCLK\I FASTCLK\I CLK52M\I SS0_DCK\I SS13_ACK\I
RES_ARRAY_4
5F3< 7F3< 9F3< 10D3<13D4<16D4< 10D9< 13D9< 16D9< 5F9< 7F9< 9F9< 3E10< 3D10< 11F5<> 14E5<> 17E6<>
21F6<>
APEX_UP_CONTROL<10.0>\I
HCT541
AAL1GATOR_32 INTERRUPT LEDS
APEX_BUSPOL APEX_INTLOB APEX_INTHIB APEX_WRDONEB APEX_BTERMB APEX_READYB APEX_BURSTB APEX_BLAST APEX_WR
AAL_UP_CONTROL<13.0>\I
ATLAS INTERRUPT
RN13 RN13 RN13 RN13 RN14 RN14 RN14
AAL1_3 AAL1_2 AAL1_1
YELLOW APEX INTERRUPT LEDS
3C10<>
SPECTRA_UP_CONTROL<4.0>\I
APEX_CSB APEX_ADSB SPECTRA_WRB/RWB SPECTRA_RDB/E SPECTRA_CSB SPECTRA_ALE SPECTRA_INTB
AAL3_INTB AAL2_INTB AAL1_INTB TE3_INTB TE2_INTB TE1_INTB RN10 RN10 RN10 RN10
RES_ARRAY_4
TEMUX_UP_CONTROL<10.0>\I
4E9<> 6E9<> 8E9<>
TEMUX_3 TEMUX_2 TEMUX_1
3C1< 3D1<
TRCLK\I RRCLK\I
RES_ARRAY_4
TEMUX INTERRUPT LEDS
RN14 SPECTRA INTERRUPT YELLOW LEDS
L_AD<31.0>\I
3B10<> 4D9<> 6D9<> 8D9<> 11F5<> 14F5<> 17F5<> 21D10<> 22C4<> 25G3<>
25C2>
LA<28.2>\I
25C1>
UP_CONTROL<8.0>\I LBE<1.0>\I L_INTB\I L_BTERMB\I
L_BLASTB L_LW/RB L_READYB L_LSERRB L_ADSB L_WAITB L_DT_RB L_DENB L_ALE LBE0 LBE1
25C2> 25E2< 25F2<
R118
LCLK_CPLD\I RSTB\I
24D4> 29B5<> 6C9< 8D9< 3C10<> 4D9<> 11E5<> 14E5<> 17E6<> 21E6<> 22B8<> 26C5>
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: DRAWING: TITLE: AAL1GATOR-32 DESIGN CPLD_1 BLOCK CPLD_1 BLOCK CPL1 15:05:04 2001 ENGINEER: REVISION NUMBER: PAGE:26 ISSUE DATE: 2001
4.7K RN124
REVISIONS
ZONE DESCRIPTION DATE APPR
C440 0.01UF C439 0.01UF C438 0.01UF C437 0.01UF C436 0.01UF C435 0.01UF C434 0.01UF C442
0.01UF
0.1UF
C441
XC95288XL-PQ208 CPLD IO16<11> IO16<10> IO16<9> IO16<8> IO16<7> IO16<6> IO16<5> IO16<4> IO16<3> IO16<2> IO16<1> IO14<11> IO14<10> IO14<9> IO14<8> IO14<7> IO14<6> IO14<5> IO14<4> IO14<3> IO14<2> IO14<1> IO12<11> IO12<10> IO12<9> IO12<8> IO12<7> IO12<6> IO12<5> IO12<4> IO12<3> IO12<2> IO12<1> IO10<11> IO10<10> IO10<9> IO10<8> IO10<7> IO10<6> IO10<5> IO10<4> IO10<3> IO10<2> IO10<1> IO8<10> IO8<9> IO8<8> IO8<7> IO8<6> IO8<5> IO8<4> IO8<3> IO8<2> IO8<1> IO6<9> IO6<8> IO6<7> IO6<6> IO6<5> IO6<4> IO6<3> IO6<2> IO6<1> IO15<11> IO15<10> IO15<9> IO15<8> IO15<7> IO15<6> IO15<5> IO15<4> IO15<3> IO15<2> IO15<1> IO13<11> IO13<10> IO13<9> IO13<8> IO13<7> IO13<6> IO13<5> IO13<4> IO13<3> IO13<2> IO13<1> IO11<11> IO11<10> IO11<9> IO11<8> IO11<7> IO11<6> IO11<5> IO11<4> IO11<3> IO11<2> IO11<1> IO9<11> IO9<10> IO9<9> IO9<8> IO9<7> IO9<6> IO9<5> IO9<4> IO9<3> IO9<2> IO9<1> IO7<10> IO7<9> IO7<8> IO7<7> IO7<6> IO7<5> IO7<4> IO7<3> IO7<2> IO7<1> IO5<9> IO5<8> IO5<7> IO5<6> IO5<5> IO5<4> IO5<3> IO5<2> IO5<1> IO3<8> IO3<7> IO3<6> IO3<5> IO3<4> IO3<3> IO3<2> IO3<1> IO1<10> IO1<9> IO1<8> IO1<7> IO1<6> IO1<5> IO1<4> IO1<3> IO1<2> IO1<1> IO/GCK<3> IO/GCK<2> IO/GCK<1> IO/GSR
ANETWORK SRTS IMPLEMENTED CPLD 202P
XC95288XL-PQ208 CPLD GND_1 VCCINT_1 VCCINT_2 GND_2 VCCINT_3 GND_3 VCCINT_4 GND_4 VCCINT_5 GND_5 GND_6 GND_7 VCCIO_1 GND_8 VCCIO_2 GND_9 VCCIO_3 GND_10 VCCIO_4 GND_11 VCCIO_5 GND_12 VCCIO_6 GND_13 VCCIO_7 GND_14 VCCIO_8 GND_15 VCCIO_9 GND_16 VCCIO_10 GND_17 VCCIO_11 GND_18 VCCIO_12 GND_19 POWER
50PPM 3.3V 2.048MHZ HCMOS
C444
0.01UF
0.1UF
C445
NC/TS
50PPM 3.3V 1.544MHZ HCMOS
C443 0.01UF
0.1UF
C446
NC/TS
NETWORK_CLK
5C8> 17E9> 14E9> 11E9>
RECVCLK1\I CGC_LINES<14.0>\I
17E9> 14E9> 11F9>
CGC_DOUT<11.0>\I
TL_CLK<95.0>\I CTCLK<1.0>\I RL_CLK<5.0>\I
10E4<13E4<16E4< 6F2< 8F2< 10E9< 13E9< 16E9<
IO4<6> IO4<5> IO4<4> IO4<3> IO4<2> IO4<1> IO2<10> IO2<9> IO2<8> IO2<7> IO2<6> IO2<5> IO2<4> IO2<3> IO2<2> IO2<1> IO/GTS<4> IO/GTS<3> IO/GTS<2> IO/GTS<1>
ADAP_STRB<2.0>\I SRTS_STRB<2.0>\I
17E9> 14E9> 11E9> 17E9> 14E9> 11E9>
CECLK<2.0>\I CICLK<2.0>\I CGC_VALID<2.0>\I CGC_SER_D<2.0>\I
4F3< 6F2< 8F2< 4G3< 6F2< 8F2< 11E9< 14D9< 17E9< 11E9< 14D9< 17E9<
11D5> 17E9< 14D9< 11E9<
AAL_SYSCLK\I NCLK<2.0>\I
R127
LCLK_CPLD\I RSTB\I
24D4> 3C10<> 4D9<> 11E5<> 14E5<> 17E6<> 21E6<> 22B8<> 26C5> 28B3<> 6C9< 8D9<
IOBLOCK
DRAWING: CPLD_2 BLOCK CPL2 15:05:07 2001
RN125 4.7K
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN CPLD_2 BLOCK ENGINEER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:27
REVISIONS
ZONE DESCRIPTION DATE APPR
PCI_3_3V\I
PCI_VCC\I
26F2<
P_AD<31.0>
L_AD<31.0>\I
VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 DP<3> DP<2> DP<1> DP<0>
3B10<> 4D9<> 6D9<> 8D9<> 11F5<> 14F5<> 17F5<> 21D10<> 22C4<> 28C3<>
4.7K
4.7K R115
P_CBE<3.0> P_SERRB
RN20 RN20 RN20 RN22 RN22 RN22 RN22 RN24 RN24 RN24 RN24 RN25 RN25 RN25 RN25
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
RN188
RN187 P_ENUMB 4.7K
P_PAR
RN18 RN18
4.7K 4.7K
-A11
P_PERRB P_STOPB P_DEVSELB P_FRAMEB P_IRDYB P_TRDYB
RN111
RN110 RN109 RN108 RN107 RN106 RN105 RN104
1013 1032 1037 1042 1048
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0>
LAD<31> LAD<30> LAD<29> LAD<28> LAD<27> LAD<26> LAD<25> LAD<24> LAD<23> LAD<22> LAD<21> LAD<20> LAD<19> LAD<18> LAD<17> LAD<16> LAD<15> LAD<14> LAD<13> LAD<12> LAD<11> LAD<10> LAD<9> LAD<8> LAD<7> LAD<6> LAD<5> LAD<4> LAD<3> LAD<2> LAD<1> LAD<0>
L_BTERMB\I
28B9>
PART#PCI9054-AB50PI
BTERM* BIGEND* LHOLDA LHOLD BLAST* LW/R* BREQO READY* LSERR* ADS*
L_BLASTB L_LW/RB L_READYB L_LSERRB L_ADSB
PCI9054 J-MODE
RN103
-A10
C/BE<3>* C/BE<2>* C/BE<1>* C/BE<0>* PME* ENUM* DEVSEL* STOP* SERR* PERR* LOCK* FRAME* TRDY* IRDY* IDSEL REQ* RST* GNT* PCLK INTA*
RN102
RN101 P_LOCKB P_IDSEL
LBE2* LBE3* DMPAF/EOT* WAIT* BREQI CCS* LCLK LEDON/LEDIN LINT* LRESETO* USERI/DACK0/LLOCKI* USERO/DREQ0/LLOCKO* MODE<1> MODE<0> TEST VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1
L_WAITB LCLK\I 4.7K 4.7K 4.7K
24D4> 28B9>
L_INTB\I RN26 RN26 RN26
P_REQB P_CLK
RN99
LBE0* LBE1* LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LA<28> DEN* DT/R*
EEDI/O EESK EECS
RN21 RN21 RN21 RN21 RN23 RN23
RN100
RN26 4.7K
P_GNTB P_INTAB
HEADER3
P_RSTB
R112
NM93CS46
L_DT_RB L_DENB L_ALE
UP_CONTROL<8.0>\I
28B9<
ZPACK5X22A CPCI
4.7K RN112
1024-BIT SERIAL EEPROM
RN19 4.7K7 4.7K6 4.7K5 4.7K RN20 4.7K
LA<28.2>\I 28C9< LBE<1.0>\I 28B9<
C407 0.01UF
C406 0.01UF
C405 0.01UF
0.1UF
C409 0.1UF
C408 0.1UF
C410
0.1UF
C412
10UF
C411
10UF
C404
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: ISSUE DATE: 2001 REVISION NUMBER: PAGE:28
PLACE DECOUPLING CAPS NEAR CHIP.
DRAWING: PCI_BLOCK PCI_BLOCK
TITLE: AAL1GATOR-32 DESIGN CPCI PCI9054
15:05:13 2001 ENGINEER:
REVISIONS
ZONE DESCRIPTION DATE APPR
7.000A PCI_3_3V\I
25G10>
LT1580CQ
VCONT SENSE
0.33UF R121 C431 100UF C430 R119 C429 C428
VPOWER
2.000A +2.5V SUPER_GREEN
R120 68UF 68UF
VOUT
22UF C433 220UF
PCI_VCC\I
25G8>
C432
R122
+5.0V SUPER_GREEN
6.2V_1W
+3.3V SUPER_GREEN R123
PBNO
SENSE HYST
RESET RESET
R126
R124
RSTB\I
3C10<> 4D9<> 11E5<> 14E5<> 17E6<> 21E6<> 22B8<> 28B3<> 29B5<> 6C9< 8D9<
MAX700
1.0K R125
RESET CIRCUITRY
PMC-Sierra, Inc.
DRAWING: POWER_AND_RESET POWER_BLOCK 15:06:03 2001 ENGINEER: DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 DESIGN POWER RESET BLOCK ISSUE DATE: 2001 REVISION NUMBER: PAGE:29
RELEASED REFERENCE DESIGN PMC-1990887 ISSUE AAL1GATOR-32
APPENDIX MICROPROCESSOR CPLD VHDL CODE
PMC-Sierra, Inc. PROPRIETARY CONFIDENTIAL Copyright 2000 PMC-Sierra, Inc. rights reserved. part this documentation computer program used, modified, reproduced, distributed form means without prior written permission PMC-Sierra, Inc. This documentation computer program contains trade secrets, confidential business information commercial financial information (collectively, "information") PMC-Sierra, Inc., unlawful disclosure information cause irreparable harm result significant commercial competitive loss PMC-Sierra, Inc. PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. Canada Tel: 604-415-6000 Fax: 604-415-6206 email: apps@pmc-sierra.com Project :PMC-990887 File Name :adetect.vhd Path Designer Revision History Issue Date Initial Descriptions 10/12/99 Function This VHDL code AAL1gator-32 Reference Design. This code generates ADETECT signals AAL1gator-32 devices. -library ieee; ieee.std_logic_1164.all; entity ADETECTgenerator port input AACTIVE signals CPLD: AACTIVE std_logic_vector downto output ADETECT signals from CPLD: ADETECT std_logic_vector downto ADETECTgenerator; architecture ADETECTgenerator_arch ADETECTgenerator
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1990887 ISSUE AAL1GATOR-32
begin -process(AACTIVE) -begin ADETECT(1) AACTIVE(2) AACTIVE(3); ADETECT(2) AACTIVE(1) AACTIVE(3); ADETECT(3) AACTIVE(1) AACTIVE(2); -end process; ADETECTgenerator_arch;
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1990887 ISSUE AAL1GATOR-32
PMC-Sierra, Inc. PROPRIETARY CONFIDENTIAL Copyright 2000 PMC-Sierra, Inc. rights reserved. part this documentation computer program used, modified, reproduced, distributed form means without prior written permission PMC-Sierra, Inc. This documentation computer program contains trade secrets, confidential business information commercial financial information (collectively, "information") PMC-Sierra, Inc., unlawful disclosure information cause irreparable harm result significant commercial competitive loss PMC-Sierra, Inc. PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. Canada Tel: 604-415-6000 Fax: 604-415-6206 email: apps@pmc-sierra.com Project :PMC-990887 File Name :chipaddress.vhd Path Designer Revision History Issue Date Initial Descriptions 10/13/99 Preliminary Function This VHDL code ASAP-CES Reference Design. This code generates CHIP_ADDRESS<19.0> signals SPECTRA-155, TEMUX APEX, ATLAS AAL1gator-32 devices. -library ieee; ieee.std_logic_1164.all; ieee.std_logic_unsigned.all; entity CHIPADgeneration port input signals CPLD L_ADSB std_logic; L_ALE std_logic; L_DENB std_logic; L_DT_RB std_logic; L_READYB std_logic; L_BLASTB std_logic; L_LW_RB std_logic; L_AD inout std_logic_vector(31 downto reset signal
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1990887 ISSUE AAL1GATOR-32
RSTB inout std_logic; CPLD clock: LCLK_CPLD std_logic; output signals: CHIP_ADDRESS std_logic_vector(19 downto (others 'Z') CHIPADgeneration; architecture CHIPADgeneration CHIPADgeneration signal std_logic; signal std_logic; begin process(LCLK_CPLD, L_ADSB, L_ALE, L_DT_RB, L_DENB) begin (LCLK_CPLD'event LCLK_CPLD '1') then (L_ADSB L_ALE L_BLASTB L_DENB '1') then CHIP_ADDRESS(19 downto L_AD(19 downto -starting single read cycle: (L_LW_RB L_DT_RB L_READYB '1') then '0'; -starting single write cycle: elsif (L_LW_RB L_DT_RB L_READYB '1') then '0'; else CHIP_ADDRESS(19 downto (others 'X'); process; CHIPADgeneration;
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1990887 ISSUE AAL1GATOR-32
PMC-Sierra, Inc. PROPRIETARY CONFIDENTIAL Copyright 2000 PMC-Sierra, Inc. rights reserved. part this documentation computer program used, modified, reproduced, distributed form means without prior written permission PMC-Sierra, Inc. This documentation computer program contains trade secrets, confidential business information commercial financial information (collectively, "information") PMC-Sierra, Inc., unlawful disclosure information cause irreparable harm result significant commercial competitive loss PMC-Sierra, Inc. PMC-Sierra, Inc. 8555 Baxter Place Bur
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